1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7356 2007-02-14 11:00:28Z twisti $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
55 #include "vmcore/options.h"
58 /* emit_load *******************************************************************
60 Emits a possible load of an operand.
62 *******************************************************************************/
64 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
70 /* get required compiler data */
74 if (IS_INMEMORY(src->flags)) {
77 disp = src->vv.regoff * 8;
79 if (IS_FLT_DBL_TYPE(src->type)) {
80 if (IS_2_WORD_TYPE(src->type))
81 M_DLD(tempreg, REG_SP, disp);
83 M_FLD(tempreg, REG_SP, disp);
86 if (IS_INT_TYPE(src->type))
87 M_ILD(tempreg, REG_SP, disp);
89 M_LLD(tempreg, REG_SP, disp);
101 /* emit_store ******************************************************************
103 This function generates the code to store the result of an
104 operation back into a spilled pseudo-variable. If the
105 pseudo-variable has not been spilled in the first place, this
106 function will generate nothing.
108 *******************************************************************************/
110 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
119 /* get required compiler data */
124 /* do we have to generate a conditional move? */
126 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
127 /* the passed register d is actually the source register */
131 /* Only pass the opcode to codegen_reg_of_var to get the real
132 destination register. */
134 opcode = iptr->opc & ICMD_OPCODE_MASK;
136 /* get the real destination register */
138 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
140 /* and emit the conditional move */
142 emit_cmovxx(cd, iptr, s, d);
146 if (IS_INMEMORY(dst->flags)) {
149 disp = dst->vv.regoff * 8;
151 if (IS_FLT_DBL_TYPE(dst->type)) {
152 if (IS_2_WORD_TYPE(dst->type))
153 M_DST(d, REG_SP, disp);
155 M_FST(d, REG_SP, disp);
158 M_LST(d, REG_SP, disp);
163 /* emit_copy *******************************************************************
165 Generates a register/memory to register/memory copy.
167 *******************************************************************************/
169 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
174 /* get required compiler data */
178 if ((src->vv.regoff != dst->vv.regoff) ||
179 ((src->flags ^ dst->flags) & INMEMORY)) {
181 /* If one of the variables resides in memory, we can eliminate
182 the register move from/to the temporary register with the
183 order of getting the destination register and the load. */
185 if (IS_INMEMORY(src->flags)) {
186 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
187 s1 = emit_load(jd, iptr, src, d);
190 s1 = emit_load(jd, iptr, src, REG_IFTMP);
191 d = codegen_reg_of_var(iptr->opc, dst, s1);
195 if (IS_FLT_DBL_TYPE(src->type))
201 emit_store(jd, iptr, dst, d);
206 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
209 switch (iptr->flags.fields.condition) {
233 /* emit_arithmetic_check *******************************************************
235 Emit an ArithmeticException check.
237 *******************************************************************************/
239 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
241 if (INSTRUCTION_MUST_CHECK(iptr)) {
244 codegen_add_arithmeticexception_ref(cd);
249 /* emit_arrayindexoutofbounds_check ********************************************
251 Emit a ArrayIndexOutOfBoundsException check.
253 *******************************************************************************/
255 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
257 if (INSTRUCTION_MUST_CHECK(iptr)) {
258 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
259 M_ICMP(REG_ITMP3, s2);
261 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
266 /* emit_classcast_check ********************************************************
268 Emit a ClassCastException check.
270 *******************************************************************************/
272 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
274 vm_abort("IMPLEMENT ME!");
278 /* emit_nullpointer_check ******************************************************
280 Emit a NullPointerException check.
282 *******************************************************************************/
284 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
286 if (INSTRUCTION_MUST_CHECK(iptr)) {
289 codegen_add_nullpointerexception_ref(cd);
294 /* emit_exception_stubs ********************************************************
296 Generates the code for the exception stubs.
298 *******************************************************************************/
300 void emit_exception_stubs(jitdata *jd)
309 /* get required compiler data */
314 /* generate exception stubs */
318 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
319 /* back-patch the branch to this exception code */
321 branchmpc = er->branchpos;
322 targetmpc = cd->mcodeptr - cd->mcodebase;
324 md_codegen_patch_branch(cd, branchmpc, targetmpc);
328 /* Check if the exception is an
329 ArrayIndexOutOfBoundsException. If so, move index register
333 M_MOV(er->reg, rd->argintregs[4]);
335 /* calcuate exception address */
337 M_MOV_IMM(0, rd->argintregs[3]);
339 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
341 /* move function to call into REG_ITMP3 */
343 M_MOV_IMM(er->function, REG_ITMP3);
345 if (targetdisp == 0) {
346 targetdisp = cd->mcodeptr - cd->mcodebase;
348 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
349 M_MOV(REG_SP, rd->argintregs[1]);
350 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
352 M_ASUB_IMM(2 * 8, REG_SP);
353 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
357 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
358 M_AADD_IMM(2 * 8, REG_SP);
360 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
364 M_JMP_IMM((cd->mcodebase + targetdisp) -
365 (cd->mcodeptr + PATCHER_CALL_SIZE));
371 /* emit_patcher_stubs **********************************************************
373 Generates the code for the patcher stubs.
375 *******************************************************************************/
377 void emit_patcher_stubs(jitdata *jd)
387 /* get required compiler data */
391 /* generate code patching stub call code */
395 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
396 /* check size of code segment */
400 /* Get machine code which is patched back in later. A
401 `call rel32' is 5 bytes long (but read 8 bytes). */
403 savedmcodeptr = cd->mcodebase + pref->branchpos;
404 mcode = *((u8 *) savedmcodeptr);
406 /* patch in `call rel32' to call the following code */
408 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
409 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
411 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
413 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
415 /* move pointer to java_objectheader onto stack */
417 #if defined(ENABLE_THREADS)
418 /* create a virtual java_objectheader */
420 (void) dseg_add_unique_address(cd, NULL); /* flcword */
421 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
422 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
424 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
430 /* move machine code bytes and classinfo pointer into registers */
432 M_MOV_IMM(mcode, REG_ITMP3);
435 M_MOV_IMM(pref->ref, REG_ITMP3);
438 M_MOV_IMM(pref->disp, REG_ITMP3);
441 M_MOV_IMM(pref->patcher, REG_ITMP3);
444 if (targetdisp == 0) {
445 targetdisp = cd->mcodeptr - cd->mcodebase;
447 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
451 M_JMP_IMM((cd->mcodebase + targetdisp) -
452 (cd->mcodeptr + PATCHER_CALL_SIZE));
458 /* emit_replacement_stubs ******************************************************
460 Generates the code for the replacement stubs.
462 *******************************************************************************/
464 #if defined(ENABLE_REPLACEMENT)
465 void emit_replacement_stubs(jitdata *jd)
476 /* get required compiler data */
481 rplp = code->rplpoints;
483 /* store beginning of replacement stubs */
485 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
487 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
488 /* do not generate stubs for non-trappable points */
490 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
493 /* check code segment size */
497 /* note start of stub code */
500 savedmcodeptr = cd->mcodeptr;
503 /* push address of `rplpoint` struct */
505 M_MOV_IMM(rplp, REG_ITMP3);
508 /* jump to replacement function */
510 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
514 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
517 #endif /* defined(ENABLE_REPLACEMENT) */
520 /* emit_verbosecall_enter ******************************************************
522 Generates the code for the call trace.
524 *******************************************************************************/
527 void emit_verbosecall_enter(jitdata *jd)
535 /* get required compiler data */
543 /* mark trace code */
547 /* additional +1 is for 16-byte stack alignment */
549 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
551 /* save argument registers */
553 for (i = 0; i < INT_ARG_CNT; i++)
554 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
556 for (i = 0; i < FLT_ARG_CNT; i++)
557 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
559 /* save temporary registers for leaf methods */
561 if (jd->isleafmethod) {
562 for (i = 0; i < INT_TMP_CNT; i++)
563 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
565 for (i = 0; i < FLT_TMP_CNT; i++)
566 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
569 /* show integer hex code for float arguments */
571 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
572 /* If the paramtype is a float, we have to right shift all
573 following integer registers. */
575 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
576 for (k = INT_ARG_CNT - 2; k >= i; k--)
577 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
579 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
584 M_MOV_IMM(m, REG_ITMP2);
585 M_AST(REG_ITMP2, REG_SP, 0 * 8);
586 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
589 /* restore argument registers */
591 for (i = 0; i < INT_ARG_CNT; i++)
592 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
594 for (i = 0; i < FLT_ARG_CNT; i++)
595 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
597 /* restore temporary registers for leaf methods */
599 if (jd->isleafmethod) {
600 for (i = 0; i < INT_TMP_CNT; i++)
601 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
603 for (i = 0; i < FLT_TMP_CNT; i++)
604 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
607 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
609 /* mark trace code */
613 #endif /* !defined(NDEBUG) */
616 /* emit_verbosecall_exit *******************************************************
618 Generates the code for the call trace.
620 *******************************************************************************/
623 void emit_verbosecall_exit(jitdata *jd)
629 /* get required compiler data */
635 /* mark trace code */
639 M_ASUB_IMM(2 * 8, REG_SP);
641 M_LST(REG_RESULT, REG_SP, 0 * 8);
642 M_DST(REG_FRESULT, REG_SP, 1 * 8);
644 M_INTMOVE(REG_RESULT, REG_A0);
645 M_FLTMOVE(REG_FRESULT, REG_FA0);
646 M_FLTMOVE(REG_FRESULT, REG_FA1);
647 M_MOV_IMM(m, REG_A1);
649 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
652 M_LLD(REG_RESULT, REG_SP, 0 * 8);
653 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
655 M_AADD_IMM(2 * 8, REG_SP);
657 /* mark trace code */
661 #endif /* !defined(NDEBUG) */
664 /* code generation functions **************************************************/
666 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
668 if ((basereg == REG_SP) || (basereg == R12)) {
670 emit_address_byte(0, dreg, REG_SP);
671 emit_address_byte(0, REG_SP, REG_SP);
673 } else if (IS_IMM8(disp)) {
674 emit_address_byte(1, dreg, REG_SP);
675 emit_address_byte(0, REG_SP, REG_SP);
679 emit_address_byte(2, dreg, REG_SP);
680 emit_address_byte(0, REG_SP, REG_SP);
684 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
685 emit_address_byte(0,(dreg),(basereg));
687 } else if ((basereg) == RIP) {
688 emit_address_byte(0, dreg, RBP);
693 emit_address_byte(1, dreg, basereg);
697 emit_address_byte(2, dreg, basereg);
704 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
706 if ((basereg == REG_SP) || (basereg == R12)) {
707 emit_address_byte(2, dreg, REG_SP);
708 emit_address_byte(0, REG_SP, REG_SP);
712 emit_address_byte(2, dreg, basereg);
718 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
721 emit_address_byte(0, reg, 4);
722 emit_address_byte(scale, indexreg, 5);
725 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
726 emit_address_byte(0, reg, 4);
727 emit_address_byte(scale, indexreg, basereg);
729 else if (IS_IMM8(disp)) {
730 emit_address_byte(1, reg, 4);
731 emit_address_byte(scale, indexreg, basereg);
735 emit_address_byte(2, reg, 4);
736 emit_address_byte(scale, indexreg, basereg);
742 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
745 varinfo *v_s1,*v_s2,*v_dst;
748 /* get required compiler data */
752 v_s1 = VAROP(iptr->s1);
753 v_s2 = VAROP(iptr->sx.s23.s2);
754 v_dst = VAROP(iptr->dst);
756 s1 = v_s1->vv.regoff;
757 s2 = v_s2->vv.regoff;
758 d = v_dst->vv.regoff;
760 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
762 if (IS_INMEMORY(v_dst->flags)) {
763 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
765 M_ILD(RCX, REG_SP, s2 * 8);
766 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
769 M_ILD(RCX, REG_SP, s2 * 8);
770 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
771 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
772 M_IST(REG_ITMP2, REG_SP, d * 8);
775 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
776 /* s1 may be equal to RCX */
779 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
780 M_IST(s1, REG_SP, d * 8);
781 M_INTMOVE(REG_ITMP1, RCX);
784 M_IST(s1, REG_SP, d * 8);
785 M_ILD(RCX, REG_SP, s2 * 8);
789 M_ILD(RCX, REG_SP, s2 * 8);
790 M_IST(s1, REG_SP, d * 8);
793 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
795 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
798 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
802 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
803 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
804 M_IST(REG_ITMP2, REG_SP, d * 8);
808 /* s1 may be equal to RCX */
809 M_IST(s1, REG_SP, d * 8);
811 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
814 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
822 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
823 M_ILD(RCX, REG_SP, s2 * 8);
824 M_ILD(d, REG_SP, s1 * 8);
825 emit_shiftl_reg(cd, shift_op, d);
827 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
828 /* s1 may be equal to RCX */
830 M_ILD(RCX, REG_SP, s2 * 8);
831 emit_shiftl_reg(cd, shift_op, d);
833 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
835 M_ILD(d, REG_SP, s1 * 8);
836 emit_shiftl_reg(cd, shift_op, d);
839 /* s1 may be equal to RCX */
842 /* d cannot be used to backup s1 since this would
844 M_INTMOVE(s1, REG_ITMP3);
846 M_INTMOVE(REG_ITMP3, d);
854 /* d may be equal to s2 */
858 emit_shiftl_reg(cd, shift_op, d);
862 M_INTMOVE(REG_ITMP3, RCX);
864 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
869 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
872 varinfo *v_s1,*v_s2,*v_dst;
875 /* get required compiler data */
879 v_s1 = VAROP(iptr->s1);
880 v_s2 = VAROP(iptr->sx.s23.s2);
881 v_dst = VAROP(iptr->dst);
883 s1 = v_s1->vv.regoff;
884 s2 = v_s2->vv.regoff;
885 d = v_dst->vv.regoff;
887 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
889 if (IS_INMEMORY(v_dst->flags)) {
890 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
892 M_ILD(RCX, REG_SP, s2 * 8);
893 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
896 M_ILD(RCX, REG_SP, s2 * 8);
897 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
898 emit_shift_reg(cd, shift_op, REG_ITMP2);
899 M_LST(REG_ITMP2, REG_SP, d * 8);
902 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
903 /* s1 may be equal to RCX */
906 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
907 M_LST(s1, REG_SP, d * 8);
908 M_INTMOVE(REG_ITMP1, RCX);
911 M_LST(s1, REG_SP, d * 8);
912 M_ILD(RCX, REG_SP, s2 * 8);
916 M_ILD(RCX, REG_SP, s2 * 8);
917 M_LST(s1, REG_SP, d * 8);
920 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
922 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
925 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
929 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
930 emit_shift_reg(cd, shift_op, REG_ITMP2);
931 M_LST(REG_ITMP2, REG_SP, d * 8);
935 /* s1 may be equal to RCX */
936 M_LST(s1, REG_SP, d * 8);
938 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
941 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
949 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
950 M_ILD(RCX, REG_SP, s2 * 8);
951 M_LLD(d, REG_SP, s1 * 8);
952 emit_shift_reg(cd, shift_op, d);
954 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
955 /* s1 may be equal to RCX */
957 M_ILD(RCX, REG_SP, s2 * 8);
958 emit_shift_reg(cd, shift_op, d);
960 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
962 M_LLD(d, REG_SP, s1 * 8);
963 emit_shift_reg(cd, shift_op, d);
966 /* s1 may be equal to RCX */
969 /* d cannot be used to backup s1 since this would
971 M_INTMOVE(s1, REG_ITMP3);
973 M_INTMOVE(REG_ITMP3, d);
981 /* d may be equal to s2 */
985 emit_shift_reg(cd, shift_op, d);
989 M_INTMOVE(REG_ITMP3, RCX);
991 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
996 /* low-level code emitter functions *******************************************/
998 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1000 emit_rex(1,(reg),0,(dreg));
1001 *(cd->mcodeptr++) = 0x89;
1002 emit_reg((reg),(dreg));
1006 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1008 emit_rex(1,0,0,(reg));
1009 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1014 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1016 emit_rex(0,(reg),0,(dreg));
1017 *(cd->mcodeptr++) = 0x89;
1018 emit_reg((reg),(dreg));
1022 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1023 emit_rex(0,0,0,(reg));
1024 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1029 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1030 emit_rex(1,(reg),0,(basereg));
1031 *(cd->mcodeptr++) = 0x8b;
1032 emit_membase(cd, (basereg),(disp),(reg));
1037 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1038 * constant membase immediate length of 32bit
1040 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1041 emit_rex(1,(reg),0,(basereg));
1042 *(cd->mcodeptr++) = 0x8b;
1043 emit_membase32(cd, (basereg),(disp),(reg));
1047 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1049 emit_rex(0,(reg),0,(basereg));
1050 *(cd->mcodeptr++) = 0x8b;
1051 emit_membase(cd, (basereg),(disp),(reg));
1055 /* ATTENTION: Always emit a REX byte, because the instruction size can
1056 be smaller when all register indexes are smaller than 7. */
1057 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1059 emit_byte_rex((reg),0,(basereg));
1060 *(cd->mcodeptr++) = 0x8b;
1061 emit_membase32(cd, (basereg),(disp),(reg));
1065 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1066 emit_rex(1,(reg),0,(basereg));
1067 *(cd->mcodeptr++) = 0x89;
1068 emit_membase(cd, (basereg),(disp),(reg));
1072 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1073 emit_rex(1,(reg),0,(basereg));
1074 *(cd->mcodeptr++) = 0x89;
1075 emit_membase32(cd, (basereg),(disp),(reg));
1079 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1080 emit_rex(0,(reg),0,(basereg));
1081 *(cd->mcodeptr++) = 0x89;
1082 emit_membase(cd, (basereg),(disp),(reg));
1086 /* Always emit a REX byte, because the instruction size can be smaller when */
1087 /* all register indexes are smaller than 7. */
1088 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1089 emit_byte_rex((reg),0,(basereg));
1090 *(cd->mcodeptr++) = 0x89;
1091 emit_membase32(cd, (basereg),(disp),(reg));
1095 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1096 emit_rex(1,(reg),(indexreg),(basereg));
1097 *(cd->mcodeptr++) = 0x8b;
1098 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1102 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1103 emit_rex(0,(reg),(indexreg),(basereg));
1104 *(cd->mcodeptr++) = 0x8b;
1105 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1109 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1110 emit_rex(1,(reg),(indexreg),(basereg));
1111 *(cd->mcodeptr++) = 0x89;
1112 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1116 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1117 emit_rex(0,(reg),(indexreg),(basereg));
1118 *(cd->mcodeptr++) = 0x89;
1119 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1123 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1124 *(cd->mcodeptr++) = 0x66;
1125 emit_rex(0,(reg),(indexreg),(basereg));
1126 *(cd->mcodeptr++) = 0x89;
1127 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1131 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1132 emit_byte_rex((reg),(indexreg),(basereg));
1133 *(cd->mcodeptr++) = 0x88;
1134 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1138 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1139 emit_rex(1,0,0,(basereg));
1140 *(cd->mcodeptr++) = 0xc7;
1141 emit_membase(cd, (basereg),(disp),0);
1146 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1147 emit_rex(1,0,0,(basereg));
1148 *(cd->mcodeptr++) = 0xc7;
1149 emit_membase32(cd, (basereg),(disp),0);
1154 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1155 emit_rex(0,0,0,(basereg));
1156 *(cd->mcodeptr++) = 0xc7;
1157 emit_membase(cd, (basereg),(disp),0);
1162 /* Always emit a REX byte, because the instruction size can be smaller when */
1163 /* all register indexes are smaller than 7. */
1164 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1165 emit_byte_rex(0,0,(basereg));
1166 *(cd->mcodeptr++) = 0xc7;
1167 emit_membase32(cd, (basereg),(disp),0);
1172 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1174 emit_rex(1,(dreg),0,(reg));
1175 *(cd->mcodeptr++) = 0x0f;
1176 *(cd->mcodeptr++) = 0xbe;
1177 /* XXX: why do reg and dreg have to be exchanged */
1178 emit_reg((dreg),(reg));
1182 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1184 emit_rex(1,(dreg),0,(reg));
1185 *(cd->mcodeptr++) = 0x0f;
1186 *(cd->mcodeptr++) = 0xbf;
1187 /* XXX: why do reg and dreg have to be exchanged */
1188 emit_reg((dreg),(reg));
1192 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1194 emit_rex(1,(dreg),0,(reg));
1195 *(cd->mcodeptr++) = 0x63;
1196 /* XXX: why do reg and dreg have to be exchanged */
1197 emit_reg((dreg),(reg));
1201 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1203 emit_rex(1,(dreg),0,(reg));
1204 *(cd->mcodeptr++) = 0x0f;
1205 *(cd->mcodeptr++) = 0xb7;
1206 /* XXX: why do reg and dreg have to be exchanged */
1207 emit_reg((dreg),(reg));
1211 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1212 emit_rex(1,(reg),(indexreg),(basereg));
1213 *(cd->mcodeptr++) = 0x0f;
1214 *(cd->mcodeptr++) = 0xbf;
1215 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1219 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1220 emit_rex(1,(reg),(indexreg),(basereg));
1221 *(cd->mcodeptr++) = 0x0f;
1222 *(cd->mcodeptr++) = 0xbe;
1223 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1227 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1228 emit_rex(1,(reg),(indexreg),(basereg));
1229 *(cd->mcodeptr++) = 0x0f;
1230 *(cd->mcodeptr++) = 0xb7;
1231 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1235 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1237 emit_rex(1,0,(indexreg),(basereg));
1238 *(cd->mcodeptr++) = 0xc7;
1239 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1244 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1246 emit_rex(0,0,(indexreg),(basereg));
1247 *(cd->mcodeptr++) = 0xc7;
1248 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1253 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1255 *(cd->mcodeptr++) = 0x66;
1256 emit_rex(0,0,(indexreg),(basereg));
1257 *(cd->mcodeptr++) = 0xc7;
1258 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1263 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1265 emit_rex(0,0,(indexreg),(basereg));
1266 *(cd->mcodeptr++) = 0xc6;
1267 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1275 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1277 emit_rex(1,(reg),0,(dreg));
1278 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1279 emit_reg((reg),(dreg));
1283 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1285 emit_rex(0,(reg),0,(dreg));
1286 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1287 emit_reg((reg),(dreg));
1291 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1293 emit_rex(1,(reg),0,(basereg));
1294 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1295 emit_membase(cd, (basereg),(disp),(reg));
1299 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1301 emit_rex(0,(reg),0,(basereg));
1302 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1303 emit_membase(cd, (basereg),(disp),(reg));
1307 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1309 emit_rex(1,(reg),0,(basereg));
1310 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1311 emit_membase(cd, (basereg),(disp),(reg));
1315 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1317 emit_rex(0,(reg),0,(basereg));
1318 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1319 emit_membase(cd, (basereg),(disp),(reg));
1323 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1325 emit_rex(1,0,0,(dreg));
1326 *(cd->mcodeptr++) = 0x83;
1327 emit_reg((opc),(dreg));
1330 emit_rex(1,0,0,(dreg));
1331 *(cd->mcodeptr++) = 0x81;
1332 emit_reg((opc),(dreg));
1338 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1339 emit_rex(1,0,0,(dreg));
1340 *(cd->mcodeptr++) = 0x81;
1341 emit_reg((opc),(dreg));
1346 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1348 emit_rex(0,0,0,(dreg));
1349 *(cd->mcodeptr++) = 0x83;
1350 emit_reg((opc),(dreg));
1353 emit_rex(0,0,0,(dreg));
1354 *(cd->mcodeptr++) = 0x81;
1355 emit_reg((opc),(dreg));
1361 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1363 emit_rex(1,(basereg),0,0);
1364 *(cd->mcodeptr++) = 0x83;
1365 emit_membase(cd, (basereg),(disp),(opc));
1368 emit_rex(1,(basereg),0,0);
1369 *(cd->mcodeptr++) = 0x81;
1370 emit_membase(cd, (basereg),(disp),(opc));
1376 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1378 emit_rex(0,(basereg),0,0);
1379 *(cd->mcodeptr++) = 0x83;
1380 emit_membase(cd, (basereg),(disp),(opc));
1383 emit_rex(0,(basereg),0,0);
1384 *(cd->mcodeptr++) = 0x81;
1385 emit_membase(cd, (basereg),(disp),(opc));
1391 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1392 emit_rex(1,(reg),0,(dreg));
1393 *(cd->mcodeptr++) = 0x85;
1394 emit_reg((reg),(dreg));
1398 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1399 emit_rex(0,(reg),0,(dreg));
1400 *(cd->mcodeptr++) = 0x85;
1401 emit_reg((reg),(dreg));
1405 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1406 *(cd->mcodeptr++) = 0xf7;
1412 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1413 *(cd->mcodeptr++) = 0x66;
1414 *(cd->mcodeptr++) = 0xf7;
1420 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1421 *(cd->mcodeptr++) = 0xf6;
1427 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1428 emit_rex(1,(reg),0,(basereg));
1429 *(cd->mcodeptr++) = 0x8d;
1430 emit_membase(cd, (basereg),(disp),(reg));
1434 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1435 emit_rex(0,(reg),0,(basereg));
1436 *(cd->mcodeptr++) = 0x8d;
1437 emit_membase(cd, (basereg),(disp),(reg));
1442 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1444 emit_rex(0,0,0,(basereg));
1445 *(cd->mcodeptr++) = 0xff;
1446 emit_membase(cd, (basereg),(disp),0);
1451 void emit_cltd(codegendata *cd) {
1452 *(cd->mcodeptr++) = 0x99;
1456 void emit_cqto(codegendata *cd) {
1458 *(cd->mcodeptr++) = 0x99;
1463 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1464 emit_rex(1,(dreg),0,(reg));
1465 *(cd->mcodeptr++) = 0x0f;
1466 *(cd->mcodeptr++) = 0xaf;
1467 emit_reg((dreg),(reg));
1471 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1472 emit_rex(0,(dreg),0,(reg));
1473 *(cd->mcodeptr++) = 0x0f;
1474 *(cd->mcodeptr++) = 0xaf;
1475 emit_reg((dreg),(reg));
1479 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1480 emit_rex(1,(dreg),0,(basereg));
1481 *(cd->mcodeptr++) = 0x0f;
1482 *(cd->mcodeptr++) = 0xaf;
1483 emit_membase(cd, (basereg),(disp),(dreg));
1487 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1488 emit_rex(0,(dreg),0,(basereg));
1489 *(cd->mcodeptr++) = 0x0f;
1490 *(cd->mcodeptr++) = 0xaf;
1491 emit_membase(cd, (basereg),(disp),(dreg));
1495 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1496 if (IS_IMM8((imm))) {
1497 emit_rex(1,0,0,(dreg));
1498 *(cd->mcodeptr++) = 0x6b;
1502 emit_rex(1,0,0,(dreg));
1503 *(cd->mcodeptr++) = 0x69;
1510 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1511 if (IS_IMM8((imm))) {
1512 emit_rex(1,(dreg),0,(reg));
1513 *(cd->mcodeptr++) = 0x6b;
1514 emit_reg((dreg),(reg));
1517 emit_rex(1,(dreg),0,(reg));
1518 *(cd->mcodeptr++) = 0x69;
1519 emit_reg((dreg),(reg));
1525 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1526 if (IS_IMM8((imm))) {
1527 emit_rex(0,(dreg),0,(reg));
1528 *(cd->mcodeptr++) = 0x6b;
1529 emit_reg((dreg),(reg));
1532 emit_rex(0,(dreg),0,(reg));
1533 *(cd->mcodeptr++) = 0x69;
1534 emit_reg((dreg),(reg));
1540 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1541 if (IS_IMM8((imm))) {
1542 emit_rex(1,(dreg),0,(basereg));
1543 *(cd->mcodeptr++) = 0x6b;
1544 emit_membase(cd, (basereg),(disp),(dreg));
1547 emit_rex(1,(dreg),0,(basereg));
1548 *(cd->mcodeptr++) = 0x69;
1549 emit_membase(cd, (basereg),(disp),(dreg));
1555 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1556 if (IS_IMM8((imm))) {
1557 emit_rex(0,(dreg),0,(basereg));
1558 *(cd->mcodeptr++) = 0x6b;
1559 emit_membase(cd, (basereg),(disp),(dreg));
1562 emit_rex(0,(dreg),0,(basereg));
1563 *(cd->mcodeptr++) = 0x69;
1564 emit_membase(cd, (basereg),(disp),(dreg));
1570 void emit_idiv_reg(codegendata *cd, s8 reg) {
1571 emit_rex(1,0,0,(reg));
1572 *(cd->mcodeptr++) = 0xf7;
1577 void emit_idivl_reg(codegendata *cd, s8 reg) {
1578 emit_rex(0,0,0,(reg));
1579 *(cd->mcodeptr++) = 0xf7;
1585 void emit_ret(codegendata *cd) {
1586 *(cd->mcodeptr++) = 0xc3;
1594 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1595 emit_rex(1,0,0,(reg));
1596 *(cd->mcodeptr++) = 0xd3;
1597 emit_reg((opc),(reg));
1601 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1602 emit_rex(0,0,0,(reg));
1603 *(cd->mcodeptr++) = 0xd3;
1604 emit_reg((opc),(reg));
1608 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1609 emit_rex(1,0,0,(basereg));
1610 *(cd->mcodeptr++) = 0xd3;
1611 emit_membase(cd, (basereg),(disp),(opc));
1615 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1616 emit_rex(0,0,0,(basereg));
1617 *(cd->mcodeptr++) = 0xd3;
1618 emit_membase(cd, (basereg),(disp),(opc));
1622 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1624 emit_rex(1,0,0,(dreg));
1625 *(cd->mcodeptr++) = 0xd1;
1626 emit_reg((opc),(dreg));
1628 emit_rex(1,0,0,(dreg));
1629 *(cd->mcodeptr++) = 0xc1;
1630 emit_reg((opc),(dreg));
1636 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1638 emit_rex(0,0,0,(dreg));
1639 *(cd->mcodeptr++) = 0xd1;
1640 emit_reg((opc),(dreg));
1642 emit_rex(0,0,0,(dreg));
1643 *(cd->mcodeptr++) = 0xc1;
1644 emit_reg((opc),(dreg));
1650 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1652 emit_rex(1,0,0,(basereg));
1653 *(cd->mcodeptr++) = 0xd1;
1654 emit_membase(cd, (basereg),(disp),(opc));
1656 emit_rex(1,0,0,(basereg));
1657 *(cd->mcodeptr++) = 0xc1;
1658 emit_membase(cd, (basereg),(disp),(opc));
1664 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1666 emit_rex(0,0,0,(basereg));
1667 *(cd->mcodeptr++) = 0xd1;
1668 emit_membase(cd, (basereg),(disp),(opc));
1670 emit_rex(0,0,0,(basereg));
1671 *(cd->mcodeptr++) = 0xc1;
1672 emit_membase(cd, (basereg),(disp),(opc));
1682 void emit_jmp_imm(codegendata *cd, s8 imm) {
1683 *(cd->mcodeptr++) = 0xe9;
1688 void emit_jmp_reg(codegendata *cd, s8 reg) {
1689 emit_rex(0,0,0,(reg));
1690 *(cd->mcodeptr++) = 0xff;
1695 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1696 *(cd->mcodeptr++) = 0x0f;
1697 *(cd->mcodeptr++) = (0x80 + (opc));
1704 * conditional set and move operations
1707 /* we need the rex byte to get all low bytes */
1708 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1709 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1710 *(cd->mcodeptr++) = 0x0f;
1711 *(cd->mcodeptr++) = (0x90 + (opc));
1716 /* we need the rex byte to get all low bytes */
1717 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1718 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1719 *(cd->mcodeptr++) = 0x0f;
1720 *(cd->mcodeptr++) = (0x90 + (opc));
1721 emit_membase(cd, (basereg),(disp),0);
1725 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1727 emit_rex(1,(dreg),0,(reg));
1728 *(cd->mcodeptr++) = 0x0f;
1729 *(cd->mcodeptr++) = (0x40 + (opc));
1730 emit_reg((dreg),(reg));
1734 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1736 emit_rex(0,(dreg),0,(reg));
1737 *(cd->mcodeptr++) = 0x0f;
1738 *(cd->mcodeptr++) = (0x40 + (opc));
1739 emit_reg((dreg),(reg));
1744 void emit_neg_reg(codegendata *cd, s8 reg)
1746 emit_rex(1,0,0,(reg));
1747 *(cd->mcodeptr++) = 0xf7;
1752 void emit_negl_reg(codegendata *cd, s8 reg)
1754 emit_rex(0,0,0,(reg));
1755 *(cd->mcodeptr++) = 0xf7;
1760 void emit_push_reg(codegendata *cd, s8 reg) {
1761 emit_rex(0,0,0,(reg));
1762 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1766 void emit_push_imm(codegendata *cd, s8 imm) {
1767 *(cd->mcodeptr++) = 0x68;
1772 void emit_pop_reg(codegendata *cd, s8 reg) {
1773 emit_rex(0,0,0,(reg));
1774 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1778 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1779 emit_rex(1,(reg),0,(dreg));
1780 *(cd->mcodeptr++) = 0x87;
1781 emit_reg((reg),(dreg));
1785 void emit_nop(codegendata *cd) {
1786 *(cd->mcodeptr++) = 0x90;
1794 void emit_call_reg(codegendata *cd, s8 reg) {
1795 emit_rex(1,0,0,(reg));
1796 *(cd->mcodeptr++) = 0xff;
1801 void emit_call_imm(codegendata *cd, s8 imm) {
1802 *(cd->mcodeptr++) = 0xe8;
1807 void emit_call_mem(codegendata *cd, ptrint mem)
1809 *(cd->mcodeptr++) = 0xff;
1816 * floating point instructions (SSE2)
1818 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1819 *(cd->mcodeptr++) = 0xf2;
1820 emit_rex(0,(dreg),0,(reg));
1821 *(cd->mcodeptr++) = 0x0f;
1822 *(cd->mcodeptr++) = 0x58;
1823 emit_reg((dreg),(reg));
1827 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1828 *(cd->mcodeptr++) = 0xf3;
1829 emit_rex(0,(dreg),0,(reg));
1830 *(cd->mcodeptr++) = 0x0f;
1831 *(cd->mcodeptr++) = 0x58;
1832 emit_reg((dreg),(reg));
1836 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1837 *(cd->mcodeptr++) = 0xf3;
1838 emit_rex(1,(dreg),0,(reg));
1839 *(cd->mcodeptr++) = 0x0f;
1840 *(cd->mcodeptr++) = 0x2a;
1841 emit_reg((dreg),(reg));
1845 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1846 *(cd->mcodeptr++) = 0xf3;
1847 emit_rex(0,(dreg),0,(reg));
1848 *(cd->mcodeptr++) = 0x0f;
1849 *(cd->mcodeptr++) = 0x2a;
1850 emit_reg((dreg),(reg));
1854 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1855 *(cd->mcodeptr++) = 0xf2;
1856 emit_rex(1,(dreg),0,(reg));
1857 *(cd->mcodeptr++) = 0x0f;
1858 *(cd->mcodeptr++) = 0x2a;
1859 emit_reg((dreg),(reg));
1863 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1864 *(cd->mcodeptr++) = 0xf2;
1865 emit_rex(0,(dreg),0,(reg));
1866 *(cd->mcodeptr++) = 0x0f;
1867 *(cd->mcodeptr++) = 0x2a;
1868 emit_reg((dreg),(reg));
1872 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1873 *(cd->mcodeptr++) = 0xf3;
1874 emit_rex(0,(dreg),0,(reg));
1875 *(cd->mcodeptr++) = 0x0f;
1876 *(cd->mcodeptr++) = 0x5a;
1877 emit_reg((dreg),(reg));
1881 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1882 *(cd->mcodeptr++) = 0xf2;
1883 emit_rex(0,(dreg),0,(reg));
1884 *(cd->mcodeptr++) = 0x0f;
1885 *(cd->mcodeptr++) = 0x5a;
1886 emit_reg((dreg),(reg));
1890 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1891 *(cd->mcodeptr++) = 0xf3;
1892 emit_rex(1,(dreg),0,(reg));
1893 *(cd->mcodeptr++) = 0x0f;
1894 *(cd->mcodeptr++) = 0x2c;
1895 emit_reg((dreg),(reg));
1899 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1900 *(cd->mcodeptr++) = 0xf3;
1901 emit_rex(0,(dreg),0,(reg));
1902 *(cd->mcodeptr++) = 0x0f;
1903 *(cd->mcodeptr++) = 0x2c;
1904 emit_reg((dreg),(reg));
1908 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1909 *(cd->mcodeptr++) = 0xf2;
1910 emit_rex(1,(dreg),0,(reg));
1911 *(cd->mcodeptr++) = 0x0f;
1912 *(cd->mcodeptr++) = 0x2c;
1913 emit_reg((dreg),(reg));
1917 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1918 *(cd->mcodeptr++) = 0xf2;
1919 emit_rex(0,(dreg),0,(reg));
1920 *(cd->mcodeptr++) = 0x0f;
1921 *(cd->mcodeptr++) = 0x2c;
1922 emit_reg((dreg),(reg));
1926 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1927 *(cd->mcodeptr++) = 0xf3;
1928 emit_rex(0,(dreg),0,(reg));
1929 *(cd->mcodeptr++) = 0x0f;
1930 *(cd->mcodeptr++) = 0x5e;
1931 emit_reg((dreg),(reg));
1935 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1936 *(cd->mcodeptr++) = 0xf2;
1937 emit_rex(0,(dreg),0,(reg));
1938 *(cd->mcodeptr++) = 0x0f;
1939 *(cd->mcodeptr++) = 0x5e;
1940 emit_reg((dreg),(reg));
1944 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1945 *(cd->mcodeptr++) = 0x66;
1946 emit_rex(1,(freg),0,(reg));
1947 *(cd->mcodeptr++) = 0x0f;
1948 *(cd->mcodeptr++) = 0x6e;
1949 emit_reg((freg),(reg));
1953 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1954 *(cd->mcodeptr++) = 0x66;
1955 emit_rex(1,(freg),0,(reg));
1956 *(cd->mcodeptr++) = 0x0f;
1957 *(cd->mcodeptr++) = 0x7e;
1958 emit_reg((freg),(reg));
1962 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1963 *(cd->mcodeptr++) = 0x66;
1964 emit_rex(0,(reg),0,(basereg));
1965 *(cd->mcodeptr++) = 0x0f;
1966 *(cd->mcodeptr++) = 0x7e;
1967 emit_membase(cd, (basereg),(disp),(reg));
1971 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1972 *(cd->mcodeptr++) = 0x66;
1973 emit_rex(0,(reg),(indexreg),(basereg));
1974 *(cd->mcodeptr++) = 0x0f;
1975 *(cd->mcodeptr++) = 0x7e;
1976 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1980 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1981 *(cd->mcodeptr++) = 0x66;
1982 emit_rex(1,(dreg),0,(basereg));
1983 *(cd->mcodeptr++) = 0x0f;
1984 *(cd->mcodeptr++) = 0x6e;
1985 emit_membase(cd, (basereg),(disp),(dreg));
1989 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1990 *(cd->mcodeptr++) = 0x66;
1991 emit_rex(0,(dreg),0,(basereg));
1992 *(cd->mcodeptr++) = 0x0f;
1993 *(cd->mcodeptr++) = 0x6e;
1994 emit_membase(cd, (basereg),(disp),(dreg));
1998 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1999 *(cd->mcodeptr++) = 0x66;
2000 emit_rex(0,(dreg),(indexreg),(basereg));
2001 *(cd->mcodeptr++) = 0x0f;
2002 *(cd->mcodeptr++) = 0x6e;
2003 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2007 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2008 *(cd->mcodeptr++) = 0xf3;
2009 emit_rex(0,(dreg),0,(reg));
2010 *(cd->mcodeptr++) = 0x0f;
2011 *(cd->mcodeptr++) = 0x7e;
2012 emit_reg((dreg),(reg));
2016 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2017 *(cd->mcodeptr++) = 0x66;
2018 emit_rex(0,(reg),0,(basereg));
2019 *(cd->mcodeptr++) = 0x0f;
2020 *(cd->mcodeptr++) = 0xd6;
2021 emit_membase(cd, (basereg),(disp),(reg));
2025 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2026 *(cd->mcodeptr++) = 0xf3;
2027 emit_rex(0,(dreg),0,(basereg));
2028 *(cd->mcodeptr++) = 0x0f;
2029 *(cd->mcodeptr++) = 0x7e;
2030 emit_membase(cd, (basereg),(disp),(dreg));
2034 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2035 *(cd->mcodeptr++) = 0xf3;
2036 emit_rex(0,(reg),0,(dreg));
2037 *(cd->mcodeptr++) = 0x0f;
2038 *(cd->mcodeptr++) = 0x10;
2039 emit_reg((reg),(dreg));
2043 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2044 *(cd->mcodeptr++) = 0xf2;
2045 emit_rex(0,(reg),0,(dreg));
2046 *(cd->mcodeptr++) = 0x0f;
2047 *(cd->mcodeptr++) = 0x10;
2048 emit_reg((reg),(dreg));
2052 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2053 *(cd->mcodeptr++) = 0xf3;
2054 emit_rex(0,(reg),0,(basereg));
2055 *(cd->mcodeptr++) = 0x0f;
2056 *(cd->mcodeptr++) = 0x11;
2057 emit_membase(cd, (basereg),(disp),(reg));
2061 /* Always emit a REX byte, because the instruction size can be smaller when */
2062 /* all register indexes are smaller than 7. */
2063 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2064 *(cd->mcodeptr++) = 0xf3;
2065 emit_byte_rex((reg),0,(basereg));
2066 *(cd->mcodeptr++) = 0x0f;
2067 *(cd->mcodeptr++) = 0x11;
2068 emit_membase32(cd, (basereg),(disp),(reg));
2072 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2073 *(cd->mcodeptr++) = 0xf2;
2074 emit_rex(0,(reg),0,(basereg));
2075 *(cd->mcodeptr++) = 0x0f;
2076 *(cd->mcodeptr++) = 0x11;
2077 emit_membase(cd, (basereg),(disp),(reg));
2081 /* Always emit a REX byte, because the instruction size can be smaller when */
2082 /* all register indexes are smaller than 7. */
2083 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2084 *(cd->mcodeptr++) = 0xf2;
2085 emit_byte_rex((reg),0,(basereg));
2086 *(cd->mcodeptr++) = 0x0f;
2087 *(cd->mcodeptr++) = 0x11;
2088 emit_membase32(cd, (basereg),(disp),(reg));
2092 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2093 *(cd->mcodeptr++) = 0xf3;
2094 emit_rex(0,(dreg),0,(basereg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = 0x10;
2097 emit_membase(cd, (basereg),(disp),(dreg));
2101 /* Always emit a REX byte, because the instruction size can be smaller when */
2102 /* all register indexes are smaller than 7. */
2103 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2104 *(cd->mcodeptr++) = 0xf3;
2105 emit_byte_rex((dreg),0,(basereg));
2106 *(cd->mcodeptr++) = 0x0f;
2107 *(cd->mcodeptr++) = 0x10;
2108 emit_membase32(cd, (basereg),(disp),(dreg));
2112 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2114 emit_rex(0,(dreg),0,(basereg));
2115 *(cd->mcodeptr++) = 0x0f;
2116 *(cd->mcodeptr++) = 0x12;
2117 emit_membase(cd, (basereg),(disp),(dreg));
2121 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2123 emit_rex(0,(reg),0,(basereg));
2124 *(cd->mcodeptr++) = 0x0f;
2125 *(cd->mcodeptr++) = 0x13;
2126 emit_membase(cd, (basereg),(disp),(reg));
2130 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2131 *(cd->mcodeptr++) = 0xf2;
2132 emit_rex(0,(dreg),0,(basereg));
2133 *(cd->mcodeptr++) = 0x0f;
2134 *(cd->mcodeptr++) = 0x10;
2135 emit_membase(cd, (basereg),(disp),(dreg));
2139 /* Always emit a REX byte, because the instruction size can be smaller when */
2140 /* all register indexes are smaller than 7. */
2141 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2142 *(cd->mcodeptr++) = 0xf2;
2143 emit_byte_rex((dreg),0,(basereg));
2144 *(cd->mcodeptr++) = 0x0f;
2145 *(cd->mcodeptr++) = 0x10;
2146 emit_membase32(cd, (basereg),(disp),(dreg));
2150 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2152 *(cd->mcodeptr++) = 0x66;
2153 emit_rex(0,(dreg),0,(basereg));
2154 *(cd->mcodeptr++) = 0x0f;
2155 *(cd->mcodeptr++) = 0x12;
2156 emit_membase(cd, (basereg),(disp),(dreg));
2160 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2162 *(cd->mcodeptr++) = 0x66;
2163 emit_rex(0,(reg),0,(basereg));
2164 *(cd->mcodeptr++) = 0x0f;
2165 *(cd->mcodeptr++) = 0x13;
2166 emit_membase(cd, (basereg),(disp),(reg));
2170 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2171 *(cd->mcodeptr++) = 0xf3;
2172 emit_rex(0,(reg),(indexreg),(basereg));
2173 *(cd->mcodeptr++) = 0x0f;
2174 *(cd->mcodeptr++) = 0x11;
2175 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2179 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2180 *(cd->mcodeptr++) = 0xf2;
2181 emit_rex(0,(reg),(indexreg),(basereg));
2182 *(cd->mcodeptr++) = 0x0f;
2183 *(cd->mcodeptr++) = 0x11;
2184 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2188 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2189 *(cd->mcodeptr++) = 0xf3;
2190 emit_rex(0,(dreg),(indexreg),(basereg));
2191 *(cd->mcodeptr++) = 0x0f;
2192 *(cd->mcodeptr++) = 0x10;
2193 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2197 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2198 *(cd->mcodeptr++) = 0xf2;
2199 emit_rex(0,(dreg),(indexreg),(basereg));
2200 *(cd->mcodeptr++) = 0x0f;
2201 *(cd->mcodeptr++) = 0x10;
2202 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2206 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2207 *(cd->mcodeptr++) = 0xf3;
2208 emit_rex(0,(dreg),0,(reg));
2209 *(cd->mcodeptr++) = 0x0f;
2210 *(cd->mcodeptr++) = 0x59;
2211 emit_reg((dreg),(reg));
2215 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2216 *(cd->mcodeptr++) = 0xf2;
2217 emit_rex(0,(dreg),0,(reg));
2218 *(cd->mcodeptr++) = 0x0f;
2219 *(cd->mcodeptr++) = 0x59;
2220 emit_reg((dreg),(reg));
2224 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2225 *(cd->mcodeptr++) = 0xf3;
2226 emit_rex(0,(dreg),0,(reg));
2227 *(cd->mcodeptr++) = 0x0f;
2228 *(cd->mcodeptr++) = 0x5c;
2229 emit_reg((dreg),(reg));
2233 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2234 *(cd->mcodeptr++) = 0xf2;
2235 emit_rex(0,(dreg),0,(reg));
2236 *(cd->mcodeptr++) = 0x0f;
2237 *(cd->mcodeptr++) = 0x5c;
2238 emit_reg((dreg),(reg));
2242 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2243 emit_rex(0,(dreg),0,(reg));
2244 *(cd->mcodeptr++) = 0x0f;
2245 *(cd->mcodeptr++) = 0x2e;
2246 emit_reg((dreg),(reg));
2250 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2251 *(cd->mcodeptr++) = 0x66;
2252 emit_rex(0,(dreg),0,(reg));
2253 *(cd->mcodeptr++) = 0x0f;
2254 *(cd->mcodeptr++) = 0x2e;
2255 emit_reg((dreg),(reg));
2259 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2260 emit_rex(0,(dreg),0,(reg));
2261 *(cd->mcodeptr++) = 0x0f;
2262 *(cd->mcodeptr++) = 0x57;
2263 emit_reg((dreg),(reg));
2267 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2268 emit_rex(0,(dreg),0,(basereg));
2269 *(cd->mcodeptr++) = 0x0f;
2270 *(cd->mcodeptr++) = 0x57;
2271 emit_membase(cd, (basereg),(disp),(dreg));
2275 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2276 *(cd->mcodeptr++) = 0x66;
2277 emit_rex(0,(dreg),0,(reg));
2278 *(cd->mcodeptr++) = 0x0f;
2279 *(cd->mcodeptr++) = 0x57;
2280 emit_reg((dreg),(reg));
2284 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2285 *(cd->mcodeptr++) = 0x66;
2286 emit_rex(0,(dreg),0,(basereg));
2287 *(cd->mcodeptr++) = 0x0f;
2288 *(cd->mcodeptr++) = 0x57;
2289 emit_membase(cd, (basereg),(disp),(dreg));
2293 /* system instructions ********************************************************/
2295 void emit_rdtsc(codegendata *cd)
2297 *(cd->mcodeptr++) = 0x0f;
2298 *(cd->mcodeptr++) = 0x31;
2303 * These are local overrides for various environment variables in Emacs.
2304 * Please do not remove this and leave it at the end of the file, where
2305 * Emacs will automagically detect them.
2306 * ---------------------------------------------------------------------
2309 * indent-tabs-mode: t