1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7644 2007-04-03 11:37:30Z twisti $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
47 #include "vm/exceptions.h"
49 #include "vm/jit/abi-asm.h"
50 #include "vm/jit/asmpart.h"
51 #include "vm/jit/codegen-common.h"
52 #include "vm/jit/emit-common.h"
53 #include "vm/jit/jit.h"
54 #include "vm/jit/replace.h"
56 #include "vmcore/options.h"
59 /* emit_load *******************************************************************
61 Emits a possible load of an operand.
63 *******************************************************************************/
65 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
71 /* get required compiler data */
75 if (IS_INMEMORY(src->flags)) {
78 disp = src->vv.regoff * 8;
82 M_ILD(tempreg, REG_SP, disp);
86 M_LLD(tempreg, REG_SP, disp);
89 M_FLD(tempreg, REG_SP, disp);
92 M_DLD(tempreg, REG_SP, disp);
95 vm_abort("emit_load: unknown type %d", src->type);
101 reg = src->vv.regoff;
107 /* emit_store ******************************************************************
109 This function generates the code to store the result of an
110 operation back into a spilled pseudo-variable. If the
111 pseudo-variable has not been spilled in the first place, this
112 function will generate nothing.
114 *******************************************************************************/
116 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
125 /* get required compiler data */
130 /* do we have to generate a conditional move? */
132 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
133 /* the passed register d is actually the source register */
137 /* Only pass the opcode to codegen_reg_of_var to get the real
138 destination register. */
140 opcode = iptr->opc & ICMD_OPCODE_MASK;
142 /* get the real destination register */
144 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
146 /* and emit the conditional move */
148 emit_cmovxx(cd, iptr, s, d);
152 if (IS_INMEMORY(dst->flags)) {
155 disp = dst->vv.regoff * 8;
161 M_LST(d, REG_SP, disp);
164 M_FST(d, REG_SP, disp);
167 M_DST(d, REG_SP, disp);
170 vm_abort("emit_store: unknown type %d", dst->type);
176 /* emit_copy *******************************************************************
178 Generates a register/memory to register/memory copy.
180 *******************************************************************************/
182 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
187 /* get required compiler data */
191 if ((src->vv.regoff != dst->vv.regoff) ||
192 ((src->flags ^ dst->flags) & INMEMORY)) {
194 /* If one of the variables resides in memory, we can eliminate
195 the register move from/to the temporary register with the
196 order of getting the destination register and the load. */
198 if (IS_INMEMORY(src->flags)) {
199 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
200 s1 = emit_load(jd, iptr, src, d);
203 s1 = emit_load(jd, iptr, src, REG_IFTMP);
204 d = codegen_reg_of_var(iptr->opc, dst, s1);
219 vm_abort("emit_copy: unknown type %d", src->type);
223 emit_store(jd, iptr, dst, d);
228 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
231 switch (iptr->flags.fields.condition) {
255 /* emit_branch *****************************************************************
257 Emits the code for conditional and unconditional branchs.
259 *******************************************************************************/
261 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
265 /* NOTE: A displacement overflow cannot happen. */
267 /* check which branch to generate */
269 if (condition == BRANCH_UNCONDITIONAL) {
271 /* calculate the different displacements */
273 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
275 M_JMP_IMM(branchdisp);
278 /* calculate the different displacements */
280 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
314 vm_abort("emit_branch: unknown condition %d", condition);
320 /* emit_arithmetic_check *******************************************************
322 Emit an ArithmeticException check.
324 *******************************************************************************/
326 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
328 if (INSTRUCTION_MUST_CHECK(iptr)) {
331 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
336 /* emit_arrayindexoutofbounds_check ********************************************
338 Emit a ArrayIndexOutOfBoundsException check.
340 *******************************************************************************/
342 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
344 if (INSTRUCTION_MUST_CHECK(iptr)) {
345 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
346 M_ICMP(REG_ITMP3, s2);
348 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
353 /* emit_classcast_check ********************************************************
355 Emit a ClassCastException check.
357 *******************************************************************************/
359 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
361 if (INSTRUCTION_MUST_CHECK(iptr)) {
373 vm_abort("emit_classcast_check: unknown condition %d", condition);
375 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
380 /* emit_nullpointer_check ******************************************************
382 Emit a NullPointerException check.
384 *******************************************************************************/
386 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
388 if (INSTRUCTION_MUST_CHECK(iptr)) {
391 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
396 /* emit_exception_check ********************************************************
398 Emit an Exception check.
400 *******************************************************************************/
402 void emit_exception_check(codegendata *cd, instruction *iptr)
404 if (INSTRUCTION_MUST_CHECK(iptr)) {
407 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
412 /* emit_patcher_stubs **********************************************************
414 Generates the code for the patcher stubs.
416 *******************************************************************************/
418 void emit_patcher_stubs(jitdata *jd)
428 /* get required compiler data */
432 /* generate code patching stub call code */
436 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
437 /* check size of code segment */
441 /* Get machine code which is patched back in later. A
442 `call rel32' is 5 bytes long (but read 8 bytes). */
444 savedmcodeptr = cd->mcodebase + pref->branchpos;
445 mcode = *((u8 *) savedmcodeptr);
447 /* patch in `call rel32' to call the following code */
449 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
450 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
452 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
454 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
456 /* move pointer to java_objectheader onto stack */
458 #if defined(ENABLE_THREADS)
459 /* create a virtual java_objectheader */
461 (void) dseg_add_unique_address(cd, NULL); /* flcword */
462 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
463 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
465 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
471 /* move machine code bytes and classinfo pointer into registers */
473 M_MOV_IMM(mcode, REG_ITMP3);
476 M_MOV_IMM(pref->ref, REG_ITMP3);
479 M_MOV_IMM(pref->disp, REG_ITMP3);
482 M_MOV_IMM(pref->patcher, REG_ITMP3);
485 if (targetdisp == 0) {
486 targetdisp = cd->mcodeptr - cd->mcodebase;
488 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
492 M_JMP_IMM((cd->mcodebase + targetdisp) -
493 (cd->mcodeptr + PATCHER_CALL_SIZE));
499 /* emit_replacement_stubs ******************************************************
501 Generates the code for the replacement stubs.
503 *******************************************************************************/
505 #if defined(ENABLE_REPLACEMENT)
506 void emit_replacement_stubs(jitdata *jd)
516 /* get required compiler data */
521 rplp = code->rplpoints;
523 /* store beginning of replacement stubs */
525 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
527 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
528 /* do not generate stubs for non-trappable points */
530 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
533 /* check code segment size */
537 /* note start of stub code */
540 savedmcodeptr = cd->mcodeptr;
543 /* push address of `rplpoint` struct */
545 M_MOV_IMM(rplp, REG_ITMP3);
548 /* jump to replacement function */
550 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
554 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
557 #endif /* defined(ENABLE_REPLACEMENT) */
560 /* emit_verbosecall_enter ******************************************************
562 Generates the code for the call trace.
564 *******************************************************************************/
567 void emit_verbosecall_enter(jitdata *jd)
575 /* get required compiler data */
583 /* mark trace code */
587 /* additional +1 is for 16-byte stack alignment */
589 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
591 /* save argument registers */
593 for (i = 0; i < INT_ARG_CNT; i++)
594 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
596 for (i = 0; i < FLT_ARG_CNT; i++)
597 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
599 /* save temporary registers for leaf methods */
601 if (jd->isleafmethod) {
602 for (i = 0; i < INT_TMP_CNT; i++)
603 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
605 for (i = 0; i < FLT_TMP_CNT; i++)
606 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
609 /* show integer hex code for float arguments */
611 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
612 /* If the paramtype is a float, we have to right shift all
613 following integer registers. */
615 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
616 for (k = INT_ARG_CNT - 2; k >= i; k--)
617 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
619 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
624 M_MOV_IMM(m, REG_ITMP2);
625 M_AST(REG_ITMP2, REG_SP, 0 * 8);
626 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
629 /* restore argument registers */
631 for (i = 0; i < INT_ARG_CNT; i++)
632 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
634 for (i = 0; i < FLT_ARG_CNT; i++)
635 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
637 /* restore temporary registers for leaf methods */
639 if (jd->isleafmethod) {
640 for (i = 0; i < INT_TMP_CNT; i++)
641 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
643 for (i = 0; i < FLT_TMP_CNT; i++)
644 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
647 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
649 /* mark trace code */
653 #endif /* !defined(NDEBUG) */
656 /* emit_verbosecall_exit *******************************************************
658 Generates the code for the call trace.
660 *******************************************************************************/
663 void emit_verbosecall_exit(jitdata *jd)
669 /* get required compiler data */
675 /* mark trace code */
679 M_ASUB_IMM(2 * 8, REG_SP);
681 M_LST(REG_RESULT, REG_SP, 0 * 8);
682 M_DST(REG_FRESULT, REG_SP, 1 * 8);
684 M_INTMOVE(REG_RESULT, REG_A0);
685 M_FLTMOVE(REG_FRESULT, REG_FA0);
686 M_FLTMOVE(REG_FRESULT, REG_FA1);
687 M_MOV_IMM(m, REG_A1);
689 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
692 M_LLD(REG_RESULT, REG_SP, 0 * 8);
693 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
695 M_AADD_IMM(2 * 8, REG_SP);
697 /* mark trace code */
701 #endif /* !defined(NDEBUG) */
704 /* code generation functions **************************************************/
706 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
708 if ((basereg == REG_SP) || (basereg == R12)) {
710 emit_address_byte(0, dreg, REG_SP);
711 emit_address_byte(0, REG_SP, REG_SP);
713 } else if (IS_IMM8(disp)) {
714 emit_address_byte(1, dreg, REG_SP);
715 emit_address_byte(0, REG_SP, REG_SP);
719 emit_address_byte(2, dreg, REG_SP);
720 emit_address_byte(0, REG_SP, REG_SP);
724 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
725 emit_address_byte(0,(dreg),(basereg));
727 } else if ((basereg) == RIP) {
728 emit_address_byte(0, dreg, RBP);
733 emit_address_byte(1, dreg, basereg);
737 emit_address_byte(2, dreg, basereg);
744 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
746 if ((basereg == REG_SP) || (basereg == R12)) {
747 emit_address_byte(2, dreg, REG_SP);
748 emit_address_byte(0, REG_SP, REG_SP);
752 emit_address_byte(2, dreg, basereg);
758 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
761 emit_address_byte(0, reg, 4);
762 emit_address_byte(scale, indexreg, 5);
765 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
766 emit_address_byte(0, reg, 4);
767 emit_address_byte(scale, indexreg, basereg);
769 else if (IS_IMM8(disp)) {
770 emit_address_byte(1, reg, 4);
771 emit_address_byte(scale, indexreg, basereg);
775 emit_address_byte(2, reg, 4);
776 emit_address_byte(scale, indexreg, basereg);
782 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
785 varinfo *v_s1,*v_s2,*v_dst;
788 /* get required compiler data */
792 v_s1 = VAROP(iptr->s1);
793 v_s2 = VAROP(iptr->sx.s23.s2);
794 v_dst = VAROP(iptr->dst);
796 s1 = v_s1->vv.regoff;
797 s2 = v_s2->vv.regoff;
798 d = v_dst->vv.regoff;
800 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
802 if (IS_INMEMORY(v_dst->flags)) {
803 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
805 M_ILD(RCX, REG_SP, s2 * 8);
806 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
809 M_ILD(RCX, REG_SP, s2 * 8);
810 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
811 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
812 M_IST(REG_ITMP2, REG_SP, d * 8);
815 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
816 /* s1 may be equal to RCX */
819 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
820 M_IST(s1, REG_SP, d * 8);
821 M_INTMOVE(REG_ITMP1, RCX);
824 M_IST(s1, REG_SP, d * 8);
825 M_ILD(RCX, REG_SP, s2 * 8);
829 M_ILD(RCX, REG_SP, s2 * 8);
830 M_IST(s1, REG_SP, d * 8);
833 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
835 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
838 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
842 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
843 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
844 M_IST(REG_ITMP2, REG_SP, d * 8);
848 /* s1 may be equal to RCX */
849 M_IST(s1, REG_SP, d * 8);
851 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
854 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
862 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
863 M_ILD(RCX, REG_SP, s2 * 8);
864 M_ILD(d, REG_SP, s1 * 8);
865 emit_shiftl_reg(cd, shift_op, d);
867 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
868 /* s1 may be equal to RCX */
870 M_ILD(RCX, REG_SP, s2 * 8);
871 emit_shiftl_reg(cd, shift_op, d);
873 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
875 M_ILD(d, REG_SP, s1 * 8);
876 emit_shiftl_reg(cd, shift_op, d);
879 /* s1 may be equal to RCX */
882 /* d cannot be used to backup s1 since this would
884 M_INTMOVE(s1, REG_ITMP3);
886 M_INTMOVE(REG_ITMP3, d);
894 /* d may be equal to s2 */
898 emit_shiftl_reg(cd, shift_op, d);
902 M_INTMOVE(REG_ITMP3, RCX);
904 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
909 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
912 varinfo *v_s1,*v_s2,*v_dst;
915 /* get required compiler data */
919 v_s1 = VAROP(iptr->s1);
920 v_s2 = VAROP(iptr->sx.s23.s2);
921 v_dst = VAROP(iptr->dst);
923 s1 = v_s1->vv.regoff;
924 s2 = v_s2->vv.regoff;
925 d = v_dst->vv.regoff;
927 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
929 if (IS_INMEMORY(v_dst->flags)) {
930 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
932 M_ILD(RCX, REG_SP, s2 * 8);
933 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
936 M_ILD(RCX, REG_SP, s2 * 8);
937 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
938 emit_shift_reg(cd, shift_op, REG_ITMP2);
939 M_LST(REG_ITMP2, REG_SP, d * 8);
942 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
943 /* s1 may be equal to RCX */
946 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
947 M_LST(s1, REG_SP, d * 8);
948 M_INTMOVE(REG_ITMP1, RCX);
951 M_LST(s1, REG_SP, d * 8);
952 M_ILD(RCX, REG_SP, s2 * 8);
956 M_ILD(RCX, REG_SP, s2 * 8);
957 M_LST(s1, REG_SP, d * 8);
960 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
962 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
965 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
969 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
970 emit_shift_reg(cd, shift_op, REG_ITMP2);
971 M_LST(REG_ITMP2, REG_SP, d * 8);
975 /* s1 may be equal to RCX */
976 M_LST(s1, REG_SP, d * 8);
978 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
981 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
989 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
990 M_ILD(RCX, REG_SP, s2 * 8);
991 M_LLD(d, REG_SP, s1 * 8);
992 emit_shift_reg(cd, shift_op, d);
994 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
995 /* s1 may be equal to RCX */
997 M_ILD(RCX, REG_SP, s2 * 8);
998 emit_shift_reg(cd, shift_op, d);
1000 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1002 M_LLD(d, REG_SP, s1 * 8);
1003 emit_shift_reg(cd, shift_op, d);
1006 /* s1 may be equal to RCX */
1009 /* d cannot be used to backup s1 since this would
1011 M_INTMOVE(s1, REG_ITMP3);
1013 M_INTMOVE(REG_ITMP3, d);
1021 /* d may be equal to s2 */
1025 emit_shift_reg(cd, shift_op, d);
1029 M_INTMOVE(REG_ITMP3, RCX);
1031 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1036 /* low-level code emitter functions *******************************************/
1038 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1040 emit_rex(1,(reg),0,(dreg));
1041 *(cd->mcodeptr++) = 0x89;
1042 emit_reg((reg),(dreg));
1046 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1048 emit_rex(1,0,0,(reg));
1049 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1054 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1056 emit_rex(0,(reg),0,(dreg));
1057 *(cd->mcodeptr++) = 0x89;
1058 emit_reg((reg),(dreg));
1062 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1063 emit_rex(0,0,0,(reg));
1064 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1069 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1070 emit_rex(1,(reg),0,(basereg));
1071 *(cd->mcodeptr++) = 0x8b;
1072 emit_membase(cd, (basereg),(disp),(reg));
1077 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1078 * constant membase immediate length of 32bit
1080 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1081 emit_rex(1,(reg),0,(basereg));
1082 *(cd->mcodeptr++) = 0x8b;
1083 emit_membase32(cd, (basereg),(disp),(reg));
1087 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1089 emit_rex(0,(reg),0,(basereg));
1090 *(cd->mcodeptr++) = 0x8b;
1091 emit_membase(cd, (basereg),(disp),(reg));
1095 /* ATTENTION: Always emit a REX byte, because the instruction size can
1096 be smaller when all register indexes are smaller than 7. */
1097 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1099 emit_byte_rex((reg),0,(basereg));
1100 *(cd->mcodeptr++) = 0x8b;
1101 emit_membase32(cd, (basereg),(disp),(reg));
1105 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1106 emit_rex(1,(reg),0,(basereg));
1107 *(cd->mcodeptr++) = 0x89;
1108 emit_membase(cd, (basereg),(disp),(reg));
1112 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1113 emit_rex(1,(reg),0,(basereg));
1114 *(cd->mcodeptr++) = 0x89;
1115 emit_membase32(cd, (basereg),(disp),(reg));
1119 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1120 emit_rex(0,(reg),0,(basereg));
1121 *(cd->mcodeptr++) = 0x89;
1122 emit_membase(cd, (basereg),(disp),(reg));
1126 /* Always emit a REX byte, because the instruction size can be smaller when */
1127 /* all register indexes are smaller than 7. */
1128 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1129 emit_byte_rex((reg),0,(basereg));
1130 *(cd->mcodeptr++) = 0x89;
1131 emit_membase32(cd, (basereg),(disp),(reg));
1135 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1136 emit_rex(1,(reg),(indexreg),(basereg));
1137 *(cd->mcodeptr++) = 0x8b;
1138 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1142 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1143 emit_rex(0,(reg),(indexreg),(basereg));
1144 *(cd->mcodeptr++) = 0x8b;
1145 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1149 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1150 emit_rex(1,(reg),(indexreg),(basereg));
1151 *(cd->mcodeptr++) = 0x89;
1152 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1156 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1157 emit_rex(0,(reg),(indexreg),(basereg));
1158 *(cd->mcodeptr++) = 0x89;
1159 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1163 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1164 *(cd->mcodeptr++) = 0x66;
1165 emit_rex(0,(reg),(indexreg),(basereg));
1166 *(cd->mcodeptr++) = 0x89;
1167 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1171 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1172 emit_byte_rex((reg),(indexreg),(basereg));
1173 *(cd->mcodeptr++) = 0x88;
1174 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1178 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1179 emit_rex(1,0,0,(basereg));
1180 *(cd->mcodeptr++) = 0xc7;
1181 emit_membase(cd, (basereg),(disp),0);
1186 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1187 emit_rex(1,0,0,(basereg));
1188 *(cd->mcodeptr++) = 0xc7;
1189 emit_membase32(cd, (basereg),(disp),0);
1194 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1195 emit_rex(0,0,0,(basereg));
1196 *(cd->mcodeptr++) = 0xc7;
1197 emit_membase(cd, (basereg),(disp),0);
1202 /* Always emit a REX byte, because the instruction size can be smaller when */
1203 /* all register indexes are smaller than 7. */
1204 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1205 emit_byte_rex(0,0,(basereg));
1206 *(cd->mcodeptr++) = 0xc7;
1207 emit_membase32(cd, (basereg),(disp),0);
1212 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1214 emit_rex(1,(dreg),0,(reg));
1215 *(cd->mcodeptr++) = 0x0f;
1216 *(cd->mcodeptr++) = 0xbe;
1217 /* XXX: why do reg and dreg have to be exchanged */
1218 emit_reg((dreg),(reg));
1222 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1224 emit_rex(1,(dreg),0,(reg));
1225 *(cd->mcodeptr++) = 0x0f;
1226 *(cd->mcodeptr++) = 0xbf;
1227 /* XXX: why do reg and dreg have to be exchanged */
1228 emit_reg((dreg),(reg));
1232 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1234 emit_rex(1,(dreg),0,(reg));
1235 *(cd->mcodeptr++) = 0x63;
1236 /* XXX: why do reg and dreg have to be exchanged */
1237 emit_reg((dreg),(reg));
1241 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1243 emit_rex(1,(dreg),0,(reg));
1244 *(cd->mcodeptr++) = 0x0f;
1245 *(cd->mcodeptr++) = 0xb7;
1246 /* XXX: why do reg and dreg have to be exchanged */
1247 emit_reg((dreg),(reg));
1251 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1252 emit_rex(1,(reg),(indexreg),(basereg));
1253 *(cd->mcodeptr++) = 0x0f;
1254 *(cd->mcodeptr++) = 0xbf;
1255 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1259 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1260 emit_rex(1,(reg),(indexreg),(basereg));
1261 *(cd->mcodeptr++) = 0x0f;
1262 *(cd->mcodeptr++) = 0xbe;
1263 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1267 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1268 emit_rex(1,(reg),(indexreg),(basereg));
1269 *(cd->mcodeptr++) = 0x0f;
1270 *(cd->mcodeptr++) = 0xb7;
1271 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1275 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1277 emit_rex(1,0,(indexreg),(basereg));
1278 *(cd->mcodeptr++) = 0xc7;
1279 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1284 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1286 emit_rex(0,0,(indexreg),(basereg));
1287 *(cd->mcodeptr++) = 0xc7;
1288 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1293 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1295 *(cd->mcodeptr++) = 0x66;
1296 emit_rex(0,0,(indexreg),(basereg));
1297 *(cd->mcodeptr++) = 0xc7;
1298 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1303 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1305 emit_rex(0,0,(indexreg),(basereg));
1306 *(cd->mcodeptr++) = 0xc6;
1307 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1312 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1314 emit_rex(1, dreg, 0, 0);
1315 *(cd->mcodeptr++) = 0x8b;
1316 emit_address_byte(0, dreg, 4);
1324 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1326 emit_rex(1,(reg),0,(dreg));
1327 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1328 emit_reg((reg),(dreg));
1332 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1334 emit_rex(0,(reg),0,(dreg));
1335 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1336 emit_reg((reg),(dreg));
1340 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1342 emit_rex(1,(reg),0,(basereg));
1343 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1344 emit_membase(cd, (basereg),(disp),(reg));
1348 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1350 emit_rex(0,(reg),0,(basereg));
1351 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1352 emit_membase(cd, (basereg),(disp),(reg));
1356 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1358 emit_rex(1,(reg),0,(basereg));
1359 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1360 emit_membase(cd, (basereg),(disp),(reg));
1364 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1366 emit_rex(0,(reg),0,(basereg));
1367 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1368 emit_membase(cd, (basereg),(disp),(reg));
1372 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1374 emit_rex(1,0,0,(dreg));
1375 *(cd->mcodeptr++) = 0x83;
1376 emit_reg((opc),(dreg));
1379 emit_rex(1,0,0,(dreg));
1380 *(cd->mcodeptr++) = 0x81;
1381 emit_reg((opc),(dreg));
1387 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1389 emit_rex(1,0,0,(dreg));
1390 *(cd->mcodeptr++) = 0x81;
1391 emit_reg((opc),(dreg));
1396 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1398 emit_rex(0,0,0,(dreg));
1399 *(cd->mcodeptr++) = 0x81;
1400 emit_reg((opc),(dreg));
1405 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1407 emit_rex(0,0,0,(dreg));
1408 *(cd->mcodeptr++) = 0x83;
1409 emit_reg((opc),(dreg));
1412 emit_rex(0,0,0,(dreg));
1413 *(cd->mcodeptr++) = 0x81;
1414 emit_reg((opc),(dreg));
1420 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1422 emit_rex(1,(basereg),0,0);
1423 *(cd->mcodeptr++) = 0x83;
1424 emit_membase(cd, (basereg),(disp),(opc));
1427 emit_rex(1,(basereg),0,0);
1428 *(cd->mcodeptr++) = 0x81;
1429 emit_membase(cd, (basereg),(disp),(opc));
1435 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1437 emit_rex(0,(basereg),0,0);
1438 *(cd->mcodeptr++) = 0x83;
1439 emit_membase(cd, (basereg),(disp),(opc));
1442 emit_rex(0,(basereg),0,0);
1443 *(cd->mcodeptr++) = 0x81;
1444 emit_membase(cd, (basereg),(disp),(opc));
1450 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1451 emit_rex(1,(reg),0,(dreg));
1452 *(cd->mcodeptr++) = 0x85;
1453 emit_reg((reg),(dreg));
1457 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1458 emit_rex(0,(reg),0,(dreg));
1459 *(cd->mcodeptr++) = 0x85;
1460 emit_reg((reg),(dreg));
1464 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1465 *(cd->mcodeptr++) = 0xf7;
1471 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1472 *(cd->mcodeptr++) = 0x66;
1473 *(cd->mcodeptr++) = 0xf7;
1479 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1480 *(cd->mcodeptr++) = 0xf6;
1486 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1487 emit_rex(1,(reg),0,(basereg));
1488 *(cd->mcodeptr++) = 0x8d;
1489 emit_membase(cd, (basereg),(disp),(reg));
1493 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1494 emit_rex(0,(reg),0,(basereg));
1495 *(cd->mcodeptr++) = 0x8d;
1496 emit_membase(cd, (basereg),(disp),(reg));
1501 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1503 emit_rex(0,0,0,(basereg));
1504 *(cd->mcodeptr++) = 0xff;
1505 emit_membase(cd, (basereg),(disp),0);
1510 void emit_cltd(codegendata *cd) {
1511 *(cd->mcodeptr++) = 0x99;
1515 void emit_cqto(codegendata *cd) {
1517 *(cd->mcodeptr++) = 0x99;
1522 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1523 emit_rex(1,(dreg),0,(reg));
1524 *(cd->mcodeptr++) = 0x0f;
1525 *(cd->mcodeptr++) = 0xaf;
1526 emit_reg((dreg),(reg));
1530 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1531 emit_rex(0,(dreg),0,(reg));
1532 *(cd->mcodeptr++) = 0x0f;
1533 *(cd->mcodeptr++) = 0xaf;
1534 emit_reg((dreg),(reg));
1538 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1539 emit_rex(1,(dreg),0,(basereg));
1540 *(cd->mcodeptr++) = 0x0f;
1541 *(cd->mcodeptr++) = 0xaf;
1542 emit_membase(cd, (basereg),(disp),(dreg));
1546 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1547 emit_rex(0,(dreg),0,(basereg));
1548 *(cd->mcodeptr++) = 0x0f;
1549 *(cd->mcodeptr++) = 0xaf;
1550 emit_membase(cd, (basereg),(disp),(dreg));
1554 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1555 if (IS_IMM8((imm))) {
1556 emit_rex(1,0,0,(dreg));
1557 *(cd->mcodeptr++) = 0x6b;
1561 emit_rex(1,0,0,(dreg));
1562 *(cd->mcodeptr++) = 0x69;
1569 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1570 if (IS_IMM8((imm))) {
1571 emit_rex(1,(dreg),0,(reg));
1572 *(cd->mcodeptr++) = 0x6b;
1573 emit_reg((dreg),(reg));
1576 emit_rex(1,(dreg),0,(reg));
1577 *(cd->mcodeptr++) = 0x69;
1578 emit_reg((dreg),(reg));
1584 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1585 if (IS_IMM8((imm))) {
1586 emit_rex(0,(dreg),0,(reg));
1587 *(cd->mcodeptr++) = 0x6b;
1588 emit_reg((dreg),(reg));
1591 emit_rex(0,(dreg),0,(reg));
1592 *(cd->mcodeptr++) = 0x69;
1593 emit_reg((dreg),(reg));
1599 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1600 if (IS_IMM8((imm))) {
1601 emit_rex(1,(dreg),0,(basereg));
1602 *(cd->mcodeptr++) = 0x6b;
1603 emit_membase(cd, (basereg),(disp),(dreg));
1606 emit_rex(1,(dreg),0,(basereg));
1607 *(cd->mcodeptr++) = 0x69;
1608 emit_membase(cd, (basereg),(disp),(dreg));
1614 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1615 if (IS_IMM8((imm))) {
1616 emit_rex(0,(dreg),0,(basereg));
1617 *(cd->mcodeptr++) = 0x6b;
1618 emit_membase(cd, (basereg),(disp),(dreg));
1621 emit_rex(0,(dreg),0,(basereg));
1622 *(cd->mcodeptr++) = 0x69;
1623 emit_membase(cd, (basereg),(disp),(dreg));
1629 void emit_idiv_reg(codegendata *cd, s8 reg) {
1630 emit_rex(1,0,0,(reg));
1631 *(cd->mcodeptr++) = 0xf7;
1636 void emit_idivl_reg(codegendata *cd, s8 reg) {
1637 emit_rex(0,0,0,(reg));
1638 *(cd->mcodeptr++) = 0xf7;
1644 void emit_ret(codegendata *cd) {
1645 *(cd->mcodeptr++) = 0xc3;
1653 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1654 emit_rex(1,0,0,(reg));
1655 *(cd->mcodeptr++) = 0xd3;
1656 emit_reg((opc),(reg));
1660 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1661 emit_rex(0,0,0,(reg));
1662 *(cd->mcodeptr++) = 0xd3;
1663 emit_reg((opc),(reg));
1667 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1668 emit_rex(1,0,0,(basereg));
1669 *(cd->mcodeptr++) = 0xd3;
1670 emit_membase(cd, (basereg),(disp),(opc));
1674 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1675 emit_rex(0,0,0,(basereg));
1676 *(cd->mcodeptr++) = 0xd3;
1677 emit_membase(cd, (basereg),(disp),(opc));
1681 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1683 emit_rex(1,0,0,(dreg));
1684 *(cd->mcodeptr++) = 0xd1;
1685 emit_reg((opc),(dreg));
1687 emit_rex(1,0,0,(dreg));
1688 *(cd->mcodeptr++) = 0xc1;
1689 emit_reg((opc),(dreg));
1695 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1697 emit_rex(0,0,0,(dreg));
1698 *(cd->mcodeptr++) = 0xd1;
1699 emit_reg((opc),(dreg));
1701 emit_rex(0,0,0,(dreg));
1702 *(cd->mcodeptr++) = 0xc1;
1703 emit_reg((opc),(dreg));
1709 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1711 emit_rex(1,0,0,(basereg));
1712 *(cd->mcodeptr++) = 0xd1;
1713 emit_membase(cd, (basereg),(disp),(opc));
1715 emit_rex(1,0,0,(basereg));
1716 *(cd->mcodeptr++) = 0xc1;
1717 emit_membase(cd, (basereg),(disp),(opc));
1723 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1725 emit_rex(0,0,0,(basereg));
1726 *(cd->mcodeptr++) = 0xd1;
1727 emit_membase(cd, (basereg),(disp),(opc));
1729 emit_rex(0,0,0,(basereg));
1730 *(cd->mcodeptr++) = 0xc1;
1731 emit_membase(cd, (basereg),(disp),(opc));
1741 void emit_jmp_imm(codegendata *cd, s8 imm) {
1742 *(cd->mcodeptr++) = 0xe9;
1747 void emit_jmp_reg(codegendata *cd, s8 reg) {
1748 emit_rex(0,0,0,(reg));
1749 *(cd->mcodeptr++) = 0xff;
1754 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1755 *(cd->mcodeptr++) = 0x0f;
1756 *(cd->mcodeptr++) = (0x80 + (opc));
1763 * conditional set and move operations
1766 /* we need the rex byte to get all low bytes */
1767 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1769 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1770 *(cd->mcodeptr++) = 0x0f;
1771 *(cd->mcodeptr++) = (0x90 + (opc));
1776 /* we need the rex byte to get all low bytes */
1777 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1779 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1780 *(cd->mcodeptr++) = 0x0f;
1781 *(cd->mcodeptr++) = (0x90 + (opc));
1782 emit_membase(cd, (basereg),(disp),0);
1786 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1788 emit_rex(1,(dreg),0,(reg));
1789 *(cd->mcodeptr++) = 0x0f;
1790 *(cd->mcodeptr++) = (0x40 + (opc));
1791 emit_reg((dreg),(reg));
1795 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1797 emit_rex(0,(dreg),0,(reg));
1798 *(cd->mcodeptr++) = 0x0f;
1799 *(cd->mcodeptr++) = (0x40 + (opc));
1800 emit_reg((dreg),(reg));
1804 void emit_neg_reg(codegendata *cd, s8 reg)
1806 emit_rex(1,0,0,(reg));
1807 *(cd->mcodeptr++) = 0xf7;
1812 void emit_negl_reg(codegendata *cd, s8 reg)
1814 emit_rex(0,0,0,(reg));
1815 *(cd->mcodeptr++) = 0xf7;
1820 void emit_push_reg(codegendata *cd, s8 reg) {
1821 emit_rex(0,0,0,(reg));
1822 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1826 void emit_push_imm(codegendata *cd, s8 imm) {
1827 *(cd->mcodeptr++) = 0x68;
1832 void emit_pop_reg(codegendata *cd, s8 reg) {
1833 emit_rex(0,0,0,(reg));
1834 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1838 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1839 emit_rex(1,(reg),0,(dreg));
1840 *(cd->mcodeptr++) = 0x87;
1841 emit_reg((reg),(dreg));
1845 void emit_nop(codegendata *cd) {
1846 *(cd->mcodeptr++) = 0x90;
1854 void emit_call_reg(codegendata *cd, s8 reg)
1856 emit_rex(0,0,0,(reg));
1857 *(cd->mcodeptr++) = 0xff;
1862 void emit_call_imm(codegendata *cd, s8 imm)
1864 *(cd->mcodeptr++) = 0xe8;
1869 void emit_call_mem(codegendata *cd, ptrint mem)
1871 *(cd->mcodeptr++) = 0xff;
1878 * floating point instructions (SSE2)
1880 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1881 *(cd->mcodeptr++) = 0xf2;
1882 emit_rex(0,(dreg),0,(reg));
1883 *(cd->mcodeptr++) = 0x0f;
1884 *(cd->mcodeptr++) = 0x58;
1885 emit_reg((dreg),(reg));
1889 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1890 *(cd->mcodeptr++) = 0xf3;
1891 emit_rex(0,(dreg),0,(reg));
1892 *(cd->mcodeptr++) = 0x0f;
1893 *(cd->mcodeptr++) = 0x58;
1894 emit_reg((dreg),(reg));
1898 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1899 *(cd->mcodeptr++) = 0xf3;
1900 emit_rex(1,(dreg),0,(reg));
1901 *(cd->mcodeptr++) = 0x0f;
1902 *(cd->mcodeptr++) = 0x2a;
1903 emit_reg((dreg),(reg));
1907 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1908 *(cd->mcodeptr++) = 0xf3;
1909 emit_rex(0,(dreg),0,(reg));
1910 *(cd->mcodeptr++) = 0x0f;
1911 *(cd->mcodeptr++) = 0x2a;
1912 emit_reg((dreg),(reg));
1916 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1917 *(cd->mcodeptr++) = 0xf2;
1918 emit_rex(1,(dreg),0,(reg));
1919 *(cd->mcodeptr++) = 0x0f;
1920 *(cd->mcodeptr++) = 0x2a;
1921 emit_reg((dreg),(reg));
1925 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1926 *(cd->mcodeptr++) = 0xf2;
1927 emit_rex(0,(dreg),0,(reg));
1928 *(cd->mcodeptr++) = 0x0f;
1929 *(cd->mcodeptr++) = 0x2a;
1930 emit_reg((dreg),(reg));
1934 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1935 *(cd->mcodeptr++) = 0xf3;
1936 emit_rex(0,(dreg),0,(reg));
1937 *(cd->mcodeptr++) = 0x0f;
1938 *(cd->mcodeptr++) = 0x5a;
1939 emit_reg((dreg),(reg));
1943 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1944 *(cd->mcodeptr++) = 0xf2;
1945 emit_rex(0,(dreg),0,(reg));
1946 *(cd->mcodeptr++) = 0x0f;
1947 *(cd->mcodeptr++) = 0x5a;
1948 emit_reg((dreg),(reg));
1952 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1953 *(cd->mcodeptr++) = 0xf3;
1954 emit_rex(1,(dreg),0,(reg));
1955 *(cd->mcodeptr++) = 0x0f;
1956 *(cd->mcodeptr++) = 0x2c;
1957 emit_reg((dreg),(reg));
1961 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1962 *(cd->mcodeptr++) = 0xf3;
1963 emit_rex(0,(dreg),0,(reg));
1964 *(cd->mcodeptr++) = 0x0f;
1965 *(cd->mcodeptr++) = 0x2c;
1966 emit_reg((dreg),(reg));
1970 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1971 *(cd->mcodeptr++) = 0xf2;
1972 emit_rex(1,(dreg),0,(reg));
1973 *(cd->mcodeptr++) = 0x0f;
1974 *(cd->mcodeptr++) = 0x2c;
1975 emit_reg((dreg),(reg));
1979 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1980 *(cd->mcodeptr++) = 0xf2;
1981 emit_rex(0,(dreg),0,(reg));
1982 *(cd->mcodeptr++) = 0x0f;
1983 *(cd->mcodeptr++) = 0x2c;
1984 emit_reg((dreg),(reg));
1988 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1989 *(cd->mcodeptr++) = 0xf3;
1990 emit_rex(0,(dreg),0,(reg));
1991 *(cd->mcodeptr++) = 0x0f;
1992 *(cd->mcodeptr++) = 0x5e;
1993 emit_reg((dreg),(reg));
1997 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1998 *(cd->mcodeptr++) = 0xf2;
1999 emit_rex(0,(dreg),0,(reg));
2000 *(cd->mcodeptr++) = 0x0f;
2001 *(cd->mcodeptr++) = 0x5e;
2002 emit_reg((dreg),(reg));
2006 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2007 *(cd->mcodeptr++) = 0x66;
2008 emit_rex(1,(freg),0,(reg));
2009 *(cd->mcodeptr++) = 0x0f;
2010 *(cd->mcodeptr++) = 0x6e;
2011 emit_reg((freg),(reg));
2015 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2016 *(cd->mcodeptr++) = 0x66;
2017 emit_rex(1,(freg),0,(reg));
2018 *(cd->mcodeptr++) = 0x0f;
2019 *(cd->mcodeptr++) = 0x7e;
2020 emit_reg((freg),(reg));
2024 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2025 *(cd->mcodeptr++) = 0x66;
2026 emit_rex(0,(reg),0,(basereg));
2027 *(cd->mcodeptr++) = 0x0f;
2028 *(cd->mcodeptr++) = 0x7e;
2029 emit_membase(cd, (basereg),(disp),(reg));
2033 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2034 *(cd->mcodeptr++) = 0x66;
2035 emit_rex(0,(reg),(indexreg),(basereg));
2036 *(cd->mcodeptr++) = 0x0f;
2037 *(cd->mcodeptr++) = 0x7e;
2038 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2042 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2043 *(cd->mcodeptr++) = 0x66;
2044 emit_rex(1,(dreg),0,(basereg));
2045 *(cd->mcodeptr++) = 0x0f;
2046 *(cd->mcodeptr++) = 0x6e;
2047 emit_membase(cd, (basereg),(disp),(dreg));
2051 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2052 *(cd->mcodeptr++) = 0x66;
2053 emit_rex(0,(dreg),0,(basereg));
2054 *(cd->mcodeptr++) = 0x0f;
2055 *(cd->mcodeptr++) = 0x6e;
2056 emit_membase(cd, (basereg),(disp),(dreg));
2060 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2061 *(cd->mcodeptr++) = 0x66;
2062 emit_rex(0,(dreg),(indexreg),(basereg));
2063 *(cd->mcodeptr++) = 0x0f;
2064 *(cd->mcodeptr++) = 0x6e;
2065 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2069 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2070 *(cd->mcodeptr++) = 0xf3;
2071 emit_rex(0,(dreg),0,(reg));
2072 *(cd->mcodeptr++) = 0x0f;
2073 *(cd->mcodeptr++) = 0x7e;
2074 emit_reg((dreg),(reg));
2078 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2079 *(cd->mcodeptr++) = 0x66;
2080 emit_rex(0,(reg),0,(basereg));
2081 *(cd->mcodeptr++) = 0x0f;
2082 *(cd->mcodeptr++) = 0xd6;
2083 emit_membase(cd, (basereg),(disp),(reg));
2087 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2088 *(cd->mcodeptr++) = 0xf3;
2089 emit_rex(0,(dreg),0,(basereg));
2090 *(cd->mcodeptr++) = 0x0f;
2091 *(cd->mcodeptr++) = 0x7e;
2092 emit_membase(cd, (basereg),(disp),(dreg));
2096 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2097 *(cd->mcodeptr++) = 0xf3;
2098 emit_rex(0,(reg),0,(dreg));
2099 *(cd->mcodeptr++) = 0x0f;
2100 *(cd->mcodeptr++) = 0x10;
2101 emit_reg((reg),(dreg));
2105 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2106 *(cd->mcodeptr++) = 0xf2;
2107 emit_rex(0,(reg),0,(dreg));
2108 *(cd->mcodeptr++) = 0x0f;
2109 *(cd->mcodeptr++) = 0x10;
2110 emit_reg((reg),(dreg));
2114 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2115 *(cd->mcodeptr++) = 0xf3;
2116 emit_rex(0,(reg),0,(basereg));
2117 *(cd->mcodeptr++) = 0x0f;
2118 *(cd->mcodeptr++) = 0x11;
2119 emit_membase(cd, (basereg),(disp),(reg));
2123 /* Always emit a REX byte, because the instruction size can be smaller when */
2124 /* all register indexes are smaller than 7. */
2125 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2126 *(cd->mcodeptr++) = 0xf3;
2127 emit_byte_rex((reg),0,(basereg));
2128 *(cd->mcodeptr++) = 0x0f;
2129 *(cd->mcodeptr++) = 0x11;
2130 emit_membase32(cd, (basereg),(disp),(reg));
2134 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2135 *(cd->mcodeptr++) = 0xf2;
2136 emit_rex(0,(reg),0,(basereg));
2137 *(cd->mcodeptr++) = 0x0f;
2138 *(cd->mcodeptr++) = 0x11;
2139 emit_membase(cd, (basereg),(disp),(reg));
2143 /* Always emit a REX byte, because the instruction size can be smaller when */
2144 /* all register indexes are smaller than 7. */
2145 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2146 *(cd->mcodeptr++) = 0xf2;
2147 emit_byte_rex((reg),0,(basereg));
2148 *(cd->mcodeptr++) = 0x0f;
2149 *(cd->mcodeptr++) = 0x11;
2150 emit_membase32(cd, (basereg),(disp),(reg));
2154 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2155 *(cd->mcodeptr++) = 0xf3;
2156 emit_rex(0,(dreg),0,(basereg));
2157 *(cd->mcodeptr++) = 0x0f;
2158 *(cd->mcodeptr++) = 0x10;
2159 emit_membase(cd, (basereg),(disp),(dreg));
2163 /* Always emit a REX byte, because the instruction size can be smaller when */
2164 /* all register indexes are smaller than 7. */
2165 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2166 *(cd->mcodeptr++) = 0xf3;
2167 emit_byte_rex((dreg),0,(basereg));
2168 *(cd->mcodeptr++) = 0x0f;
2169 *(cd->mcodeptr++) = 0x10;
2170 emit_membase32(cd, (basereg),(disp),(dreg));
2174 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2176 emit_rex(0,(dreg),0,(basereg));
2177 *(cd->mcodeptr++) = 0x0f;
2178 *(cd->mcodeptr++) = 0x12;
2179 emit_membase(cd, (basereg),(disp),(dreg));
2183 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2185 emit_rex(0,(reg),0,(basereg));
2186 *(cd->mcodeptr++) = 0x0f;
2187 *(cd->mcodeptr++) = 0x13;
2188 emit_membase(cd, (basereg),(disp),(reg));
2192 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2193 *(cd->mcodeptr++) = 0xf2;
2194 emit_rex(0,(dreg),0,(basereg));
2195 *(cd->mcodeptr++) = 0x0f;
2196 *(cd->mcodeptr++) = 0x10;
2197 emit_membase(cd, (basereg),(disp),(dreg));
2201 /* Always emit a REX byte, because the instruction size can be smaller when */
2202 /* all register indexes are smaller than 7. */
2203 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2204 *(cd->mcodeptr++) = 0xf2;
2205 emit_byte_rex((dreg),0,(basereg));
2206 *(cd->mcodeptr++) = 0x0f;
2207 *(cd->mcodeptr++) = 0x10;
2208 emit_membase32(cd, (basereg),(disp),(dreg));
2212 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2214 *(cd->mcodeptr++) = 0x66;
2215 emit_rex(0,(dreg),0,(basereg));
2216 *(cd->mcodeptr++) = 0x0f;
2217 *(cd->mcodeptr++) = 0x12;
2218 emit_membase(cd, (basereg),(disp),(dreg));
2222 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2224 *(cd->mcodeptr++) = 0x66;
2225 emit_rex(0,(reg),0,(basereg));
2226 *(cd->mcodeptr++) = 0x0f;
2227 *(cd->mcodeptr++) = 0x13;
2228 emit_membase(cd, (basereg),(disp),(reg));
2232 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2233 *(cd->mcodeptr++) = 0xf3;
2234 emit_rex(0,(reg),(indexreg),(basereg));
2235 *(cd->mcodeptr++) = 0x0f;
2236 *(cd->mcodeptr++) = 0x11;
2237 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2241 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2242 *(cd->mcodeptr++) = 0xf2;
2243 emit_rex(0,(reg),(indexreg),(basereg));
2244 *(cd->mcodeptr++) = 0x0f;
2245 *(cd->mcodeptr++) = 0x11;
2246 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2250 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2251 *(cd->mcodeptr++) = 0xf3;
2252 emit_rex(0,(dreg),(indexreg),(basereg));
2253 *(cd->mcodeptr++) = 0x0f;
2254 *(cd->mcodeptr++) = 0x10;
2255 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2259 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2260 *(cd->mcodeptr++) = 0xf2;
2261 emit_rex(0,(dreg),(indexreg),(basereg));
2262 *(cd->mcodeptr++) = 0x0f;
2263 *(cd->mcodeptr++) = 0x10;
2264 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2268 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2269 *(cd->mcodeptr++) = 0xf3;
2270 emit_rex(0,(dreg),0,(reg));
2271 *(cd->mcodeptr++) = 0x0f;
2272 *(cd->mcodeptr++) = 0x59;
2273 emit_reg((dreg),(reg));
2277 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2278 *(cd->mcodeptr++) = 0xf2;
2279 emit_rex(0,(dreg),0,(reg));
2280 *(cd->mcodeptr++) = 0x0f;
2281 *(cd->mcodeptr++) = 0x59;
2282 emit_reg((dreg),(reg));
2286 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2287 *(cd->mcodeptr++) = 0xf3;
2288 emit_rex(0,(dreg),0,(reg));
2289 *(cd->mcodeptr++) = 0x0f;
2290 *(cd->mcodeptr++) = 0x5c;
2291 emit_reg((dreg),(reg));
2295 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2296 *(cd->mcodeptr++) = 0xf2;
2297 emit_rex(0,(dreg),0,(reg));
2298 *(cd->mcodeptr++) = 0x0f;
2299 *(cd->mcodeptr++) = 0x5c;
2300 emit_reg((dreg),(reg));
2304 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2305 emit_rex(0,(dreg),0,(reg));
2306 *(cd->mcodeptr++) = 0x0f;
2307 *(cd->mcodeptr++) = 0x2e;
2308 emit_reg((dreg),(reg));
2312 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2313 *(cd->mcodeptr++) = 0x66;
2314 emit_rex(0,(dreg),0,(reg));
2315 *(cd->mcodeptr++) = 0x0f;
2316 *(cd->mcodeptr++) = 0x2e;
2317 emit_reg((dreg),(reg));
2321 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2322 emit_rex(0,(dreg),0,(reg));
2323 *(cd->mcodeptr++) = 0x0f;
2324 *(cd->mcodeptr++) = 0x57;
2325 emit_reg((dreg),(reg));
2329 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2330 emit_rex(0,(dreg),0,(basereg));
2331 *(cd->mcodeptr++) = 0x0f;
2332 *(cd->mcodeptr++) = 0x57;
2333 emit_membase(cd, (basereg),(disp),(dreg));
2337 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2338 *(cd->mcodeptr++) = 0x66;
2339 emit_rex(0,(dreg),0,(reg));
2340 *(cd->mcodeptr++) = 0x0f;
2341 *(cd->mcodeptr++) = 0x57;
2342 emit_reg((dreg),(reg));
2346 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2347 *(cd->mcodeptr++) = 0x66;
2348 emit_rex(0,(dreg),0,(basereg));
2349 *(cd->mcodeptr++) = 0x0f;
2350 *(cd->mcodeptr++) = 0x57;
2351 emit_membase(cd, (basereg),(disp),(dreg));
2355 /* system instructions ********************************************************/
2357 void emit_rdtsc(codegendata *cd)
2359 *(cd->mcodeptr++) = 0x0f;
2360 *(cd->mcodeptr++) = 0x31;
2365 * These are local overrides for various environment variables in Emacs.
2366 * Please do not remove this and leave it at the end of the file, where
2367 * Emacs will automagically detect them.
2368 * ---------------------------------------------------------------------
2371 * indent-tabs-mode: t