1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/builtin.h"
43 #include "vm/exceptions.h"
45 #include "vm/jit/abi.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/replace.h"
53 #include "vmcore/options.h"
56 /* emit_load *******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff;
79 M_ILD(tempreg, REG_SP, disp);
83 M_LLD(tempreg, REG_SP, disp);
86 M_FLD(tempreg, REG_SP, disp);
89 M_DLD(tempreg, REG_SP, disp);
92 vm_abort("emit_load: unknown type %d", src->type);
104 /* emit_store ******************************************************************
106 This function generates the code to store the result of an
107 operation back into a spilled pseudo-variable. If the
108 pseudo-variable has not been spilled in the first place, this
109 function will generate nothing.
111 *******************************************************************************/
113 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
122 /* get required compiler data */
127 /* do we have to generate a conditional move? */
129 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
130 /* the passed register d is actually the source register */
134 /* Only pass the opcode to codegen_reg_of_var to get the real
135 destination register. */
137 opcode = iptr->opc & ICMD_OPCODE_MASK;
139 /* get the real destination register */
141 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
143 /* and emit the conditional move */
145 emit_cmovxx(cd, iptr, s, d);
149 if (IS_INMEMORY(dst->flags)) {
152 disp = dst->vv.regoff;
158 M_LST(d, REG_SP, disp);
161 M_FST(d, REG_SP, disp);
164 M_DST(d, REG_SP, disp);
167 vm_abort("emit_store: unknown type %d", dst->type);
173 /* emit_copy *******************************************************************
175 Generates a register/memory to register/memory copy.
177 *******************************************************************************/
179 void emit_copy(jitdata *jd, instruction *iptr)
186 /* get required compiler data */
190 /* get source and destination variables */
192 src = VAROP(iptr->s1);
193 dst = VAROP(iptr->dst);
195 if ((src->vv.regoff != dst->vv.regoff) ||
196 ((src->flags ^ dst->flags) & INMEMORY)) {
198 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
199 /* emit nothing, as the value won't be used anyway */
203 /* If one of the variables resides in memory, we can eliminate
204 the register move from/to the temporary register with the
205 order of getting the destination register and the load. */
207 if (IS_INMEMORY(src->flags)) {
208 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
209 s1 = emit_load(jd, iptr, src, d);
212 s1 = emit_load(jd, iptr, src, REG_IFTMP);
213 d = codegen_reg_of_var(iptr->opc, dst, s1);
228 vm_abort("emit_copy: unknown type %d", src->type);
232 emit_store(jd, iptr, dst, d);
237 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
240 switch (iptr->flags.fields.condition) {
264 /* emit_branch *****************************************************************
266 Emits the code for conditional and unconditional branchs.
268 *******************************************************************************/
270 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
274 /* NOTE: A displacement overflow cannot happen. */
276 /* check which branch to generate */
278 if (condition == BRANCH_UNCONDITIONAL) {
280 /* calculate the different displacements */
282 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
284 M_JMP_IMM(branchdisp);
287 /* calculate the different displacements */
289 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
323 vm_abort("emit_branch: unknown condition %d", condition);
329 /* emit_arithmetic_check *******************************************************
331 Emit an ArithmeticException check.
333 *******************************************************************************/
335 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
337 if (INSTRUCTION_MUST_CHECK(iptr)) {
340 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
345 /* emit_arrayindexoutofbounds_check ********************************************
347 Emit a ArrayIndexOutOfBoundsException check.
349 *******************************************************************************/
351 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
353 if (INSTRUCTION_MUST_CHECK(iptr)) {
354 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
355 M_ICMP(REG_ITMP3, s2);
357 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
362 /* emit_arraystore_check *******************************************************
364 Emit an ArrayStoreException check.
366 *******************************************************************************/
368 void emit_arraystore_check(codegendata *cd, instruction *iptr)
370 if (INSTRUCTION_MUST_CHECK(iptr)) {
373 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_ARRAYSTORE);
378 /* emit_classcast_check ********************************************************
380 Emit a ClassCastException check.
382 *******************************************************************************/
384 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
386 if (INSTRUCTION_MUST_CHECK(iptr)) {
398 vm_abort("emit_classcast_check: unknown condition %d", condition);
400 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
405 /* emit_nullpointer_check ******************************************************
407 Emit a NullPointerException check.
409 *******************************************************************************/
411 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
413 if (INSTRUCTION_MUST_CHECK(iptr)) {
416 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
421 /* emit_exception_check ********************************************************
423 Emit an Exception check.
425 *******************************************************************************/
427 void emit_exception_check(codegendata *cd, instruction *iptr)
429 if (INSTRUCTION_MUST_CHECK(iptr)) {
432 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
437 /* emit_patcher_stubs **********************************************************
439 Generates the code for the patcher stubs.
441 *******************************************************************************/
443 void emit_patcher_stubs(jitdata *jd)
453 /* get required compiler data */
457 /* generate code patching stub call code */
461 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
462 /* check size of code segment */
466 /* Get machine code which is patched back in later. A
467 `call rel32' is 5 bytes long (but read 8 bytes). */
469 savedmcodeptr = cd->mcodebase + pref->branchpos;
470 mcode = *((u8 *) savedmcodeptr);
472 /* patch in `call rel32' to call the following code */
474 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
475 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
477 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
479 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
481 /* move pointer to java_objectheader onto stack */
483 #if defined(ENABLE_THREADS)
484 /* create a virtual java_objectheader */
486 (void) dseg_add_unique_address(cd, NULL); /* flcword */
487 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
488 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
490 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
496 /* move machine code bytes and classinfo pointer into registers */
498 M_MOV_IMM(mcode, REG_ITMP3);
501 M_MOV_IMM(pref->ref, REG_ITMP3);
504 M_MOV_IMM(pref->disp, REG_ITMP3);
507 M_MOV_IMM(pref->patcher, REG_ITMP3);
510 if (targetdisp == 0) {
511 targetdisp = cd->mcodeptr - cd->mcodebase;
513 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
517 M_JMP_IMM((cd->mcodebase + targetdisp) -
518 (cd->mcodeptr + PATCHER_CALL_SIZE));
524 /* emit_trap *******************************************************************
526 Emit a trap instruction and return the original machine code.
528 *******************************************************************************/
530 uint32_t emit_trap(codegendata *cd)
534 /* Get machine code which is patched back in later. The
535 trap is 1 instruction word long. */
537 mcode = *((uint32_t *) cd->mcodeptr);
545 /* emit_verbosecall_enter ******************************************************
547 Generates the code for the call trace.
549 *******************************************************************************/
552 void emit_verbosecall_enter(jitdata *jd)
560 /* get required compiler data */
568 /* mark trace code */
572 /* additional +1 is for 16-byte stack alignment */
574 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
576 /* save argument registers */
578 for (i = 0; i < INT_ARG_CNT; i++)
579 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
581 for (i = 0; i < FLT_ARG_CNT; i++)
582 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
584 /* save temporary registers for leaf methods */
586 if (jd->isleafmethod) {
587 for (i = 0; i < INT_TMP_CNT; i++)
588 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
590 for (i = 0; i < FLT_TMP_CNT; i++)
591 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
594 /* show integer hex code for float arguments */
596 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
597 /* If the paramtype is a float, we have to right shift all
598 following integer registers. */
600 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
601 for (k = INT_ARG_CNT - 2; k >= i; k--)
602 M_MOV(abi_registers_integer_argument[k],
603 abi_registers_integer_argument[k + 1]);
605 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
606 abi_registers_integer_argument[i]);
611 M_MOV_IMM(m, REG_ITMP2);
612 M_AST(REG_ITMP2, REG_SP, 0 * 8);
613 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
616 /* restore argument registers */
618 for (i = 0; i < INT_ARG_CNT; i++)
619 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
621 for (i = 0; i < FLT_ARG_CNT; i++)
622 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
624 /* restore temporary registers for leaf methods */
626 if (jd->isleafmethod) {
627 for (i = 0; i < INT_TMP_CNT; i++)
628 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
630 for (i = 0; i < FLT_TMP_CNT; i++)
631 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
634 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
636 /* mark trace code */
640 #endif /* !defined(NDEBUG) */
643 /* emit_verbosecall_exit *******************************************************
645 Generates the code for the call trace.
647 *******************************************************************************/
650 void emit_verbosecall_exit(jitdata *jd)
656 /* get required compiler data */
662 /* mark trace code */
666 M_ASUB_IMM(2 * 8, REG_SP);
668 M_LST(REG_RESULT, REG_SP, 0 * 8);
669 M_DST(REG_FRESULT, REG_SP, 1 * 8);
671 M_INTMOVE(REG_RESULT, REG_A0);
672 M_FLTMOVE(REG_FRESULT, REG_FA0);
673 M_FLTMOVE(REG_FRESULT, REG_FA1);
674 M_MOV_IMM(m, REG_A1);
676 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
679 M_LLD(REG_RESULT, REG_SP, 0 * 8);
680 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
682 M_AADD_IMM(2 * 8, REG_SP);
684 /* mark trace code */
688 #endif /* !defined(NDEBUG) */
691 /* code generation functions **************************************************/
693 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
695 if ((basereg == REG_SP) || (basereg == R12)) {
697 emit_address_byte(0, dreg, REG_SP);
698 emit_address_byte(0, REG_SP, REG_SP);
700 } else if (IS_IMM8(disp)) {
701 emit_address_byte(1, dreg, REG_SP);
702 emit_address_byte(0, REG_SP, REG_SP);
706 emit_address_byte(2, dreg, REG_SP);
707 emit_address_byte(0, REG_SP, REG_SP);
711 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
712 emit_address_byte(0,(dreg),(basereg));
714 } else if ((basereg) == RIP) {
715 emit_address_byte(0, dreg, RBP);
720 emit_address_byte(1, dreg, basereg);
724 emit_address_byte(2, dreg, basereg);
731 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
733 if ((basereg == REG_SP) || (basereg == R12)) {
734 emit_address_byte(2, dreg, REG_SP);
735 emit_address_byte(0, REG_SP, REG_SP);
739 emit_address_byte(2, dreg, basereg);
745 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
748 emit_address_byte(0, reg, 4);
749 emit_address_byte(scale, indexreg, 5);
752 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
753 emit_address_byte(0, reg, 4);
754 emit_address_byte(scale, indexreg, basereg);
756 else if (IS_IMM8(disp)) {
757 emit_address_byte(1, reg, 4);
758 emit_address_byte(scale, indexreg, basereg);
762 emit_address_byte(2, reg, 4);
763 emit_address_byte(scale, indexreg, basereg);
769 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
772 varinfo *v_s1,*v_s2,*v_dst;
775 /* get required compiler data */
779 v_s1 = VAROP(iptr->s1);
780 v_s2 = VAROP(iptr->sx.s23.s2);
781 v_dst = VAROP(iptr->dst);
783 s1 = v_s1->vv.regoff;
784 s2 = v_s2->vv.regoff;
785 d = v_dst->vv.regoff;
787 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
789 if (IS_INMEMORY(v_dst->flags)) {
790 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
792 M_ILD(RCX, REG_SP, s2);
793 emit_shiftl_membase(cd, shift_op, REG_SP, d);
796 M_ILD(RCX, REG_SP, s2);
797 M_ILD(REG_ITMP2, REG_SP, s1);
798 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
799 M_IST(REG_ITMP2, REG_SP, d);
802 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
803 /* s1 may be equal to RCX */
806 M_ILD(REG_ITMP1, REG_SP, s2);
807 M_IST(s1, REG_SP, d);
808 M_INTMOVE(REG_ITMP1, RCX);
811 M_IST(s1, REG_SP, d);
812 M_ILD(RCX, REG_SP, s2);
816 M_ILD(RCX, REG_SP, s2);
817 M_IST(s1, REG_SP, d);
820 emit_shiftl_membase(cd, shift_op, REG_SP, d);
822 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
825 emit_shiftl_membase(cd, shift_op, REG_SP, d);
829 M_ILD(REG_ITMP2, REG_SP, s1);
830 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
831 M_IST(REG_ITMP2, REG_SP, d);
835 /* s1 may be equal to RCX */
836 M_IST(s1, REG_SP, d);
838 emit_shiftl_membase(cd, shift_op, REG_SP, d);
841 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
849 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
850 M_ILD(RCX, REG_SP, s2);
851 M_ILD(d, REG_SP, s1);
852 emit_shiftl_reg(cd, shift_op, d);
854 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
855 /* s1 may be equal to RCX */
857 M_ILD(RCX, REG_SP, s2);
858 emit_shiftl_reg(cd, shift_op, d);
860 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
862 M_ILD(d, REG_SP, s1);
863 emit_shiftl_reg(cd, shift_op, d);
866 /* s1 may be equal to RCX */
869 /* d cannot be used to backup s1 since this would
871 M_INTMOVE(s1, REG_ITMP3);
873 M_INTMOVE(REG_ITMP3, d);
881 /* d may be equal to s2 */
885 emit_shiftl_reg(cd, shift_op, d);
889 M_INTMOVE(REG_ITMP3, RCX);
891 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
896 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
899 varinfo *v_s1,*v_s2,*v_dst;
902 /* get required compiler data */
906 v_s1 = VAROP(iptr->s1);
907 v_s2 = VAROP(iptr->sx.s23.s2);
908 v_dst = VAROP(iptr->dst);
910 s1 = v_s1->vv.regoff;
911 s2 = v_s2->vv.regoff;
912 d = v_dst->vv.regoff;
914 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
916 if (IS_INMEMORY(v_dst->flags)) {
917 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
919 M_ILD(RCX, REG_SP, s2);
920 emit_shift_membase(cd, shift_op, REG_SP, d);
923 M_ILD(RCX, REG_SP, s2);
924 M_LLD(REG_ITMP2, REG_SP, s1);
925 emit_shift_reg(cd, shift_op, REG_ITMP2);
926 M_LST(REG_ITMP2, REG_SP, d);
929 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
930 /* s1 may be equal to RCX */
933 M_ILD(REG_ITMP1, REG_SP, s2);
934 M_LST(s1, REG_SP, d);
935 M_INTMOVE(REG_ITMP1, RCX);
938 M_LST(s1, REG_SP, d);
939 M_ILD(RCX, REG_SP, s2);
943 M_ILD(RCX, REG_SP, s2);
944 M_LST(s1, REG_SP, d);
947 emit_shift_membase(cd, shift_op, REG_SP, d);
949 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
952 emit_shift_membase(cd, shift_op, REG_SP, d);
956 M_LLD(REG_ITMP2, REG_SP, s1);
957 emit_shift_reg(cd, shift_op, REG_ITMP2);
958 M_LST(REG_ITMP2, REG_SP, d);
962 /* s1 may be equal to RCX */
963 M_LST(s1, REG_SP, d);
965 emit_shift_membase(cd, shift_op, REG_SP, d);
968 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
976 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
977 M_ILD(RCX, REG_SP, s2);
978 M_LLD(d, REG_SP, s1);
979 emit_shift_reg(cd, shift_op, d);
981 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
982 /* s1 may be equal to RCX */
984 M_ILD(RCX, REG_SP, s2);
985 emit_shift_reg(cd, shift_op, d);
987 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
989 M_LLD(d, REG_SP, s1);
990 emit_shift_reg(cd, shift_op, d);
993 /* s1 may be equal to RCX */
996 /* d cannot be used to backup s1 since this would
998 M_INTMOVE(s1, REG_ITMP3);
1000 M_INTMOVE(REG_ITMP3, d);
1008 /* d may be equal to s2 */
1012 emit_shift_reg(cd, shift_op, d);
1016 M_INTMOVE(REG_ITMP3, RCX);
1018 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1023 /* low-level code emitter functions *******************************************/
1025 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1027 emit_rex(1,(reg),0,(dreg));
1028 *(cd->mcodeptr++) = 0x89;
1029 emit_reg((reg),(dreg));
1033 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1035 emit_rex(1,0,0,(reg));
1036 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1041 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1043 emit_rex(0,(reg),0,(dreg));
1044 *(cd->mcodeptr++) = 0x89;
1045 emit_reg((reg),(dreg));
1049 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1050 emit_rex(0,0,0,(reg));
1051 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1056 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1057 emit_rex(1,(reg),0,(basereg));
1058 *(cd->mcodeptr++) = 0x8b;
1059 emit_membase(cd, (basereg),(disp),(reg));
1064 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1065 * constant membase immediate length of 32bit
1067 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1068 emit_rex(1,(reg),0,(basereg));
1069 *(cd->mcodeptr++) = 0x8b;
1070 emit_membase32(cd, (basereg),(disp),(reg));
1074 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1076 emit_rex(0,(reg),0,(basereg));
1077 *(cd->mcodeptr++) = 0x8b;
1078 emit_membase(cd, (basereg),(disp),(reg));
1082 /* ATTENTION: Always emit a REX byte, because the instruction size can
1083 be smaller when all register indexes are smaller than 7. */
1084 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1086 emit_byte_rex((reg),0,(basereg));
1087 *(cd->mcodeptr++) = 0x8b;
1088 emit_membase32(cd, (basereg),(disp),(reg));
1092 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1093 emit_rex(1,(reg),0,(basereg));
1094 *(cd->mcodeptr++) = 0x89;
1095 emit_membase(cd, (basereg),(disp),(reg));
1099 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1100 emit_rex(1,(reg),0,(basereg));
1101 *(cd->mcodeptr++) = 0x89;
1102 emit_membase32(cd, (basereg),(disp),(reg));
1106 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1107 emit_rex(0,(reg),0,(basereg));
1108 *(cd->mcodeptr++) = 0x89;
1109 emit_membase(cd, (basereg),(disp),(reg));
1113 /* Always emit a REX byte, because the instruction size can be smaller when */
1114 /* all register indexes are smaller than 7. */
1115 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1116 emit_byte_rex((reg),0,(basereg));
1117 *(cd->mcodeptr++) = 0x89;
1118 emit_membase32(cd, (basereg),(disp),(reg));
1122 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1123 emit_rex(1,(reg),(indexreg),(basereg));
1124 *(cd->mcodeptr++) = 0x8b;
1125 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1129 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1130 emit_rex(0,(reg),(indexreg),(basereg));
1131 *(cd->mcodeptr++) = 0x8b;
1132 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1136 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1137 emit_rex(1,(reg),(indexreg),(basereg));
1138 *(cd->mcodeptr++) = 0x89;
1139 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1143 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1144 emit_rex(0,(reg),(indexreg),(basereg));
1145 *(cd->mcodeptr++) = 0x89;
1146 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1150 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1151 *(cd->mcodeptr++) = 0x66;
1152 emit_rex(0,(reg),(indexreg),(basereg));
1153 *(cd->mcodeptr++) = 0x89;
1154 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1158 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1159 emit_byte_rex((reg),(indexreg),(basereg));
1160 *(cd->mcodeptr++) = 0x88;
1161 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1165 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1166 emit_rex(1,0,0,(basereg));
1167 *(cd->mcodeptr++) = 0xc7;
1168 emit_membase(cd, (basereg),(disp),0);
1173 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1174 emit_rex(1,0,0,(basereg));
1175 *(cd->mcodeptr++) = 0xc7;
1176 emit_membase32(cd, (basereg),(disp),0);
1181 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1182 emit_rex(0,0,0,(basereg));
1183 *(cd->mcodeptr++) = 0xc7;
1184 emit_membase(cd, (basereg),(disp),0);
1189 /* Always emit a REX byte, because the instruction size can be smaller when */
1190 /* all register indexes are smaller than 7. */
1191 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1192 emit_byte_rex(0,0,(basereg));
1193 *(cd->mcodeptr++) = 0xc7;
1194 emit_membase32(cd, (basereg),(disp),0);
1199 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1201 emit_rex(1,(dreg),0,(reg));
1202 *(cd->mcodeptr++) = 0x0f;
1203 *(cd->mcodeptr++) = 0xbe;
1204 /* XXX: why do reg and dreg have to be exchanged */
1205 emit_reg((dreg),(reg));
1209 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1211 emit_rex(1,(dreg),0,(reg));
1212 *(cd->mcodeptr++) = 0x0f;
1213 *(cd->mcodeptr++) = 0xbf;
1214 /* XXX: why do reg and dreg have to be exchanged */
1215 emit_reg((dreg),(reg));
1219 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1221 emit_rex(1,(dreg),0,(reg));
1222 *(cd->mcodeptr++) = 0x63;
1223 /* XXX: why do reg and dreg have to be exchanged */
1224 emit_reg((dreg),(reg));
1228 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1230 emit_rex(1,(dreg),0,(reg));
1231 *(cd->mcodeptr++) = 0x0f;
1232 *(cd->mcodeptr++) = 0xb7;
1233 /* XXX: why do reg and dreg have to be exchanged */
1234 emit_reg((dreg),(reg));
1238 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1239 emit_rex(1,(reg),(indexreg),(basereg));
1240 *(cd->mcodeptr++) = 0x0f;
1241 *(cd->mcodeptr++) = 0xbf;
1242 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1246 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1247 emit_rex(1,(reg),(indexreg),(basereg));
1248 *(cd->mcodeptr++) = 0x0f;
1249 *(cd->mcodeptr++) = 0xbe;
1250 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1254 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1255 emit_rex(1,(reg),(indexreg),(basereg));
1256 *(cd->mcodeptr++) = 0x0f;
1257 *(cd->mcodeptr++) = 0xb7;
1258 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1262 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1264 emit_rex(1,0,(indexreg),(basereg));
1265 *(cd->mcodeptr++) = 0xc7;
1266 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1271 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1273 emit_rex(0,0,(indexreg),(basereg));
1274 *(cd->mcodeptr++) = 0xc7;
1275 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1280 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1282 *(cd->mcodeptr++) = 0x66;
1283 emit_rex(0,0,(indexreg),(basereg));
1284 *(cd->mcodeptr++) = 0xc7;
1285 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1290 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1292 emit_rex(0,0,(indexreg),(basereg));
1293 *(cd->mcodeptr++) = 0xc6;
1294 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1299 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1301 emit_rex(1, dreg, 0, 0);
1302 *(cd->mcodeptr++) = 0x8b;
1303 emit_address_byte(0, dreg, 4);
1311 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1313 emit_rex(1,(reg),0,(dreg));
1314 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1315 emit_reg((reg),(dreg));
1319 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1321 emit_rex(0,(reg),0,(dreg));
1322 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1323 emit_reg((reg),(dreg));
1327 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1329 emit_rex(1,(reg),0,(basereg));
1330 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1331 emit_membase(cd, (basereg),(disp),(reg));
1335 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1337 emit_rex(0,(reg),0,(basereg));
1338 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1339 emit_membase(cd, (basereg),(disp),(reg));
1343 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1345 emit_rex(1,(reg),0,(basereg));
1346 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1347 emit_membase(cd, (basereg),(disp),(reg));
1351 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1353 emit_rex(0,(reg),0,(basereg));
1354 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1355 emit_membase(cd, (basereg),(disp),(reg));
1359 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1361 emit_rex(1,0,0,(dreg));
1362 *(cd->mcodeptr++) = 0x83;
1363 emit_reg((opc),(dreg));
1366 emit_rex(1,0,0,(dreg));
1367 *(cd->mcodeptr++) = 0x81;
1368 emit_reg((opc),(dreg));
1374 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1376 emit_rex(1,0,0,(dreg));
1377 *(cd->mcodeptr++) = 0x81;
1378 emit_reg((opc),(dreg));
1383 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1385 emit_rex(0,0,0,(dreg));
1386 *(cd->mcodeptr++) = 0x81;
1387 emit_reg((opc),(dreg));
1392 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1394 emit_rex(0,0,0,(dreg));
1395 *(cd->mcodeptr++) = 0x83;
1396 emit_reg((opc),(dreg));
1399 emit_rex(0,0,0,(dreg));
1400 *(cd->mcodeptr++) = 0x81;
1401 emit_reg((opc),(dreg));
1407 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1409 emit_rex(1,(basereg),0,0);
1410 *(cd->mcodeptr++) = 0x83;
1411 emit_membase(cd, (basereg),(disp),(opc));
1414 emit_rex(1,(basereg),0,0);
1415 *(cd->mcodeptr++) = 0x81;
1416 emit_membase(cd, (basereg),(disp),(opc));
1422 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1424 emit_rex(0,(basereg),0,0);
1425 *(cd->mcodeptr++) = 0x83;
1426 emit_membase(cd, (basereg),(disp),(opc));
1429 emit_rex(0,(basereg),0,0);
1430 *(cd->mcodeptr++) = 0x81;
1431 emit_membase(cd, (basereg),(disp),(opc));
1437 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1438 emit_rex(1,(reg),0,(dreg));
1439 *(cd->mcodeptr++) = 0x85;
1440 emit_reg((reg),(dreg));
1444 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1445 emit_rex(0,(reg),0,(dreg));
1446 *(cd->mcodeptr++) = 0x85;
1447 emit_reg((reg),(dreg));
1451 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1452 *(cd->mcodeptr++) = 0xf7;
1458 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1459 *(cd->mcodeptr++) = 0x66;
1460 *(cd->mcodeptr++) = 0xf7;
1466 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1467 *(cd->mcodeptr++) = 0xf6;
1473 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1474 emit_rex(1,(reg),0,(basereg));
1475 *(cd->mcodeptr++) = 0x8d;
1476 emit_membase(cd, (basereg),(disp),(reg));
1480 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1481 emit_rex(0,(reg),0,(basereg));
1482 *(cd->mcodeptr++) = 0x8d;
1483 emit_membase(cd, (basereg),(disp),(reg));
1488 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1490 emit_rex(0,0,0,(basereg));
1491 *(cd->mcodeptr++) = 0xff;
1492 emit_membase(cd, (basereg),(disp),0);
1497 void emit_cltd(codegendata *cd) {
1498 *(cd->mcodeptr++) = 0x99;
1502 void emit_cqto(codegendata *cd) {
1504 *(cd->mcodeptr++) = 0x99;
1509 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1510 emit_rex(1,(dreg),0,(reg));
1511 *(cd->mcodeptr++) = 0x0f;
1512 *(cd->mcodeptr++) = 0xaf;
1513 emit_reg((dreg),(reg));
1517 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1518 emit_rex(0,(dreg),0,(reg));
1519 *(cd->mcodeptr++) = 0x0f;
1520 *(cd->mcodeptr++) = 0xaf;
1521 emit_reg((dreg),(reg));
1525 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1526 emit_rex(1,(dreg),0,(basereg));
1527 *(cd->mcodeptr++) = 0x0f;
1528 *(cd->mcodeptr++) = 0xaf;
1529 emit_membase(cd, (basereg),(disp),(dreg));
1533 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1534 emit_rex(0,(dreg),0,(basereg));
1535 *(cd->mcodeptr++) = 0x0f;
1536 *(cd->mcodeptr++) = 0xaf;
1537 emit_membase(cd, (basereg),(disp),(dreg));
1541 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1542 if (IS_IMM8((imm))) {
1543 emit_rex(1,0,0,(dreg));
1544 *(cd->mcodeptr++) = 0x6b;
1548 emit_rex(1,0,0,(dreg));
1549 *(cd->mcodeptr++) = 0x69;
1556 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1557 if (IS_IMM8((imm))) {
1558 emit_rex(1,(dreg),0,(reg));
1559 *(cd->mcodeptr++) = 0x6b;
1560 emit_reg((dreg),(reg));
1563 emit_rex(1,(dreg),0,(reg));
1564 *(cd->mcodeptr++) = 0x69;
1565 emit_reg((dreg),(reg));
1571 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1572 if (IS_IMM8((imm))) {
1573 emit_rex(0,(dreg),0,(reg));
1574 *(cd->mcodeptr++) = 0x6b;
1575 emit_reg((dreg),(reg));
1578 emit_rex(0,(dreg),0,(reg));
1579 *(cd->mcodeptr++) = 0x69;
1580 emit_reg((dreg),(reg));
1586 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1587 if (IS_IMM8((imm))) {
1588 emit_rex(1,(dreg),0,(basereg));
1589 *(cd->mcodeptr++) = 0x6b;
1590 emit_membase(cd, (basereg),(disp),(dreg));
1593 emit_rex(1,(dreg),0,(basereg));
1594 *(cd->mcodeptr++) = 0x69;
1595 emit_membase(cd, (basereg),(disp),(dreg));
1601 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1602 if (IS_IMM8((imm))) {
1603 emit_rex(0,(dreg),0,(basereg));
1604 *(cd->mcodeptr++) = 0x6b;
1605 emit_membase(cd, (basereg),(disp),(dreg));
1608 emit_rex(0,(dreg),0,(basereg));
1609 *(cd->mcodeptr++) = 0x69;
1610 emit_membase(cd, (basereg),(disp),(dreg));
1616 void emit_idiv_reg(codegendata *cd, s8 reg) {
1617 emit_rex(1,0,0,(reg));
1618 *(cd->mcodeptr++) = 0xf7;
1623 void emit_idivl_reg(codegendata *cd, s8 reg) {
1624 emit_rex(0,0,0,(reg));
1625 *(cd->mcodeptr++) = 0xf7;
1631 void emit_ret(codegendata *cd) {
1632 *(cd->mcodeptr++) = 0xc3;
1640 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1641 emit_rex(1,0,0,(reg));
1642 *(cd->mcodeptr++) = 0xd3;
1643 emit_reg((opc),(reg));
1647 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1648 emit_rex(0,0,0,(reg));
1649 *(cd->mcodeptr++) = 0xd3;
1650 emit_reg((opc),(reg));
1654 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1655 emit_rex(1,0,0,(basereg));
1656 *(cd->mcodeptr++) = 0xd3;
1657 emit_membase(cd, (basereg),(disp),(opc));
1661 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1662 emit_rex(0,0,0,(basereg));
1663 *(cd->mcodeptr++) = 0xd3;
1664 emit_membase(cd, (basereg),(disp),(opc));
1668 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1670 emit_rex(1,0,0,(dreg));
1671 *(cd->mcodeptr++) = 0xd1;
1672 emit_reg((opc),(dreg));
1674 emit_rex(1,0,0,(dreg));
1675 *(cd->mcodeptr++) = 0xc1;
1676 emit_reg((opc),(dreg));
1682 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1684 emit_rex(0,0,0,(dreg));
1685 *(cd->mcodeptr++) = 0xd1;
1686 emit_reg((opc),(dreg));
1688 emit_rex(0,0,0,(dreg));
1689 *(cd->mcodeptr++) = 0xc1;
1690 emit_reg((opc),(dreg));
1696 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1698 emit_rex(1,0,0,(basereg));
1699 *(cd->mcodeptr++) = 0xd1;
1700 emit_membase(cd, (basereg),(disp),(opc));
1702 emit_rex(1,0,0,(basereg));
1703 *(cd->mcodeptr++) = 0xc1;
1704 emit_membase(cd, (basereg),(disp),(opc));
1710 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1712 emit_rex(0,0,0,(basereg));
1713 *(cd->mcodeptr++) = 0xd1;
1714 emit_membase(cd, (basereg),(disp),(opc));
1716 emit_rex(0,0,0,(basereg));
1717 *(cd->mcodeptr++) = 0xc1;
1718 emit_membase(cd, (basereg),(disp),(opc));
1728 void emit_jmp_imm(codegendata *cd, s8 imm) {
1729 *(cd->mcodeptr++) = 0xe9;
1734 void emit_jmp_reg(codegendata *cd, s8 reg) {
1735 emit_rex(0,0,0,(reg));
1736 *(cd->mcodeptr++) = 0xff;
1741 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1742 *(cd->mcodeptr++) = 0x0f;
1743 *(cd->mcodeptr++) = (0x80 + (opc));
1750 * conditional set and move operations
1753 /* we need the rex byte to get all low bytes */
1754 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1756 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1757 *(cd->mcodeptr++) = 0x0f;
1758 *(cd->mcodeptr++) = (0x90 + (opc));
1763 /* we need the rex byte to get all low bytes */
1764 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1766 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1767 *(cd->mcodeptr++) = 0x0f;
1768 *(cd->mcodeptr++) = (0x90 + (opc));
1769 emit_membase(cd, (basereg),(disp),0);
1773 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1775 emit_rex(1,(dreg),0,(reg));
1776 *(cd->mcodeptr++) = 0x0f;
1777 *(cd->mcodeptr++) = (0x40 + (opc));
1778 emit_reg((dreg),(reg));
1782 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1784 emit_rex(0,(dreg),0,(reg));
1785 *(cd->mcodeptr++) = 0x0f;
1786 *(cd->mcodeptr++) = (0x40 + (opc));
1787 emit_reg((dreg),(reg));
1791 void emit_neg_reg(codegendata *cd, s8 reg)
1793 emit_rex(1,0,0,(reg));
1794 *(cd->mcodeptr++) = 0xf7;
1799 void emit_negl_reg(codegendata *cd, s8 reg)
1801 emit_rex(0,0,0,(reg));
1802 *(cd->mcodeptr++) = 0xf7;
1807 void emit_push_reg(codegendata *cd, s8 reg) {
1808 emit_rex(0,0,0,(reg));
1809 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1813 void emit_push_imm(codegendata *cd, s8 imm) {
1814 *(cd->mcodeptr++) = 0x68;
1819 void emit_pop_reg(codegendata *cd, s8 reg) {
1820 emit_rex(0,0,0,(reg));
1821 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1825 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1826 emit_rex(1,(reg),0,(dreg));
1827 *(cd->mcodeptr++) = 0x87;
1828 emit_reg((reg),(dreg));
1832 void emit_nop(codegendata *cd) {
1833 *(cd->mcodeptr++) = 0x90;
1841 void emit_call_reg(codegendata *cd, s8 reg)
1843 emit_rex(0,0,0,(reg));
1844 *(cd->mcodeptr++) = 0xff;
1849 void emit_call_imm(codegendata *cd, s8 imm)
1851 *(cd->mcodeptr++) = 0xe8;
1856 void emit_call_mem(codegendata *cd, ptrint mem)
1858 *(cd->mcodeptr++) = 0xff;
1865 * floating point instructions (SSE2)
1867 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1868 *(cd->mcodeptr++) = 0xf2;
1869 emit_rex(0,(dreg),0,(reg));
1870 *(cd->mcodeptr++) = 0x0f;
1871 *(cd->mcodeptr++) = 0x58;
1872 emit_reg((dreg),(reg));
1876 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1877 *(cd->mcodeptr++) = 0xf3;
1878 emit_rex(0,(dreg),0,(reg));
1879 *(cd->mcodeptr++) = 0x0f;
1880 *(cd->mcodeptr++) = 0x58;
1881 emit_reg((dreg),(reg));
1885 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1886 *(cd->mcodeptr++) = 0xf3;
1887 emit_rex(1,(dreg),0,(reg));
1888 *(cd->mcodeptr++) = 0x0f;
1889 *(cd->mcodeptr++) = 0x2a;
1890 emit_reg((dreg),(reg));
1894 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1895 *(cd->mcodeptr++) = 0xf3;
1896 emit_rex(0,(dreg),0,(reg));
1897 *(cd->mcodeptr++) = 0x0f;
1898 *(cd->mcodeptr++) = 0x2a;
1899 emit_reg((dreg),(reg));
1903 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1904 *(cd->mcodeptr++) = 0xf2;
1905 emit_rex(1,(dreg),0,(reg));
1906 *(cd->mcodeptr++) = 0x0f;
1907 *(cd->mcodeptr++) = 0x2a;
1908 emit_reg((dreg),(reg));
1912 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1913 *(cd->mcodeptr++) = 0xf2;
1914 emit_rex(0,(dreg),0,(reg));
1915 *(cd->mcodeptr++) = 0x0f;
1916 *(cd->mcodeptr++) = 0x2a;
1917 emit_reg((dreg),(reg));
1921 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1922 *(cd->mcodeptr++) = 0xf3;
1923 emit_rex(0,(dreg),0,(reg));
1924 *(cd->mcodeptr++) = 0x0f;
1925 *(cd->mcodeptr++) = 0x5a;
1926 emit_reg((dreg),(reg));
1930 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1931 *(cd->mcodeptr++) = 0xf2;
1932 emit_rex(0,(dreg),0,(reg));
1933 *(cd->mcodeptr++) = 0x0f;
1934 *(cd->mcodeptr++) = 0x5a;
1935 emit_reg((dreg),(reg));
1939 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1940 *(cd->mcodeptr++) = 0xf3;
1941 emit_rex(1,(dreg),0,(reg));
1942 *(cd->mcodeptr++) = 0x0f;
1943 *(cd->mcodeptr++) = 0x2c;
1944 emit_reg((dreg),(reg));
1948 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1949 *(cd->mcodeptr++) = 0xf3;
1950 emit_rex(0,(dreg),0,(reg));
1951 *(cd->mcodeptr++) = 0x0f;
1952 *(cd->mcodeptr++) = 0x2c;
1953 emit_reg((dreg),(reg));
1957 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1958 *(cd->mcodeptr++) = 0xf2;
1959 emit_rex(1,(dreg),0,(reg));
1960 *(cd->mcodeptr++) = 0x0f;
1961 *(cd->mcodeptr++) = 0x2c;
1962 emit_reg((dreg),(reg));
1966 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1967 *(cd->mcodeptr++) = 0xf2;
1968 emit_rex(0,(dreg),0,(reg));
1969 *(cd->mcodeptr++) = 0x0f;
1970 *(cd->mcodeptr++) = 0x2c;
1971 emit_reg((dreg),(reg));
1975 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1976 *(cd->mcodeptr++) = 0xf3;
1977 emit_rex(0,(dreg),0,(reg));
1978 *(cd->mcodeptr++) = 0x0f;
1979 *(cd->mcodeptr++) = 0x5e;
1980 emit_reg((dreg),(reg));
1984 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1985 *(cd->mcodeptr++) = 0xf2;
1986 emit_rex(0,(dreg),0,(reg));
1987 *(cd->mcodeptr++) = 0x0f;
1988 *(cd->mcodeptr++) = 0x5e;
1989 emit_reg((dreg),(reg));
1993 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1994 *(cd->mcodeptr++) = 0x66;
1995 emit_rex(1,(freg),0,(reg));
1996 *(cd->mcodeptr++) = 0x0f;
1997 *(cd->mcodeptr++) = 0x6e;
1998 emit_reg((freg),(reg));
2002 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2003 *(cd->mcodeptr++) = 0x66;
2004 emit_rex(1,(freg),0,(reg));
2005 *(cd->mcodeptr++) = 0x0f;
2006 *(cd->mcodeptr++) = 0x7e;
2007 emit_reg((freg),(reg));
2011 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2012 *(cd->mcodeptr++) = 0x66;
2013 emit_rex(0,(reg),0,(basereg));
2014 *(cd->mcodeptr++) = 0x0f;
2015 *(cd->mcodeptr++) = 0x7e;
2016 emit_membase(cd, (basereg),(disp),(reg));
2020 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2021 *(cd->mcodeptr++) = 0x66;
2022 emit_rex(0,(reg),(indexreg),(basereg));
2023 *(cd->mcodeptr++) = 0x0f;
2024 *(cd->mcodeptr++) = 0x7e;
2025 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2029 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2030 *(cd->mcodeptr++) = 0x66;
2031 emit_rex(1,(dreg),0,(basereg));
2032 *(cd->mcodeptr++) = 0x0f;
2033 *(cd->mcodeptr++) = 0x6e;
2034 emit_membase(cd, (basereg),(disp),(dreg));
2038 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2039 *(cd->mcodeptr++) = 0x66;
2040 emit_rex(0,(dreg),0,(basereg));
2041 *(cd->mcodeptr++) = 0x0f;
2042 *(cd->mcodeptr++) = 0x6e;
2043 emit_membase(cd, (basereg),(disp),(dreg));
2047 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2048 *(cd->mcodeptr++) = 0x66;
2049 emit_rex(0,(dreg),(indexreg),(basereg));
2050 *(cd->mcodeptr++) = 0x0f;
2051 *(cd->mcodeptr++) = 0x6e;
2052 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2056 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2057 *(cd->mcodeptr++) = 0xf3;
2058 emit_rex(0,(dreg),0,(reg));
2059 *(cd->mcodeptr++) = 0x0f;
2060 *(cd->mcodeptr++) = 0x7e;
2061 emit_reg((dreg),(reg));
2065 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2066 *(cd->mcodeptr++) = 0x66;
2067 emit_rex(0,(reg),0,(basereg));
2068 *(cd->mcodeptr++) = 0x0f;
2069 *(cd->mcodeptr++) = 0xd6;
2070 emit_membase(cd, (basereg),(disp),(reg));
2074 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2075 *(cd->mcodeptr++) = 0xf3;
2076 emit_rex(0,(dreg),0,(basereg));
2077 *(cd->mcodeptr++) = 0x0f;
2078 *(cd->mcodeptr++) = 0x7e;
2079 emit_membase(cd, (basereg),(disp),(dreg));
2083 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2084 *(cd->mcodeptr++) = 0xf3;
2085 emit_rex(0,(reg),0,(dreg));
2086 *(cd->mcodeptr++) = 0x0f;
2087 *(cd->mcodeptr++) = 0x10;
2088 emit_reg((reg),(dreg));
2092 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2093 *(cd->mcodeptr++) = 0xf2;
2094 emit_rex(0,(reg),0,(dreg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = 0x10;
2097 emit_reg((reg),(dreg));
2101 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2102 *(cd->mcodeptr++) = 0xf3;
2103 emit_rex(0,(reg),0,(basereg));
2104 *(cd->mcodeptr++) = 0x0f;
2105 *(cd->mcodeptr++) = 0x11;
2106 emit_membase(cd, (basereg),(disp),(reg));
2110 /* Always emit a REX byte, because the instruction size can be smaller when */
2111 /* all register indexes are smaller than 7. */
2112 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2113 *(cd->mcodeptr++) = 0xf3;
2114 emit_byte_rex((reg),0,(basereg));
2115 *(cd->mcodeptr++) = 0x0f;
2116 *(cd->mcodeptr++) = 0x11;
2117 emit_membase32(cd, (basereg),(disp),(reg));
2121 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2122 *(cd->mcodeptr++) = 0xf2;
2123 emit_rex(0,(reg),0,(basereg));
2124 *(cd->mcodeptr++) = 0x0f;
2125 *(cd->mcodeptr++) = 0x11;
2126 emit_membase(cd, (basereg),(disp),(reg));
2130 /* Always emit a REX byte, because the instruction size can be smaller when */
2131 /* all register indexes are smaller than 7. */
2132 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2133 *(cd->mcodeptr++) = 0xf2;
2134 emit_byte_rex((reg),0,(basereg));
2135 *(cd->mcodeptr++) = 0x0f;
2136 *(cd->mcodeptr++) = 0x11;
2137 emit_membase32(cd, (basereg),(disp),(reg));
2141 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2142 *(cd->mcodeptr++) = 0xf3;
2143 emit_rex(0,(dreg),0,(basereg));
2144 *(cd->mcodeptr++) = 0x0f;
2145 *(cd->mcodeptr++) = 0x10;
2146 emit_membase(cd, (basereg),(disp),(dreg));
2150 /* Always emit a REX byte, because the instruction size can be smaller when */
2151 /* all register indexes are smaller than 7. */
2152 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2153 *(cd->mcodeptr++) = 0xf3;
2154 emit_byte_rex((dreg),0,(basereg));
2155 *(cd->mcodeptr++) = 0x0f;
2156 *(cd->mcodeptr++) = 0x10;
2157 emit_membase32(cd, (basereg),(disp),(dreg));
2161 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2163 emit_rex(0,(dreg),0,(basereg));
2164 *(cd->mcodeptr++) = 0x0f;
2165 *(cd->mcodeptr++) = 0x12;
2166 emit_membase(cd, (basereg),(disp),(dreg));
2170 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2172 emit_rex(0,(reg),0,(basereg));
2173 *(cd->mcodeptr++) = 0x0f;
2174 *(cd->mcodeptr++) = 0x13;
2175 emit_membase(cd, (basereg),(disp),(reg));
2179 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2180 *(cd->mcodeptr++) = 0xf2;
2181 emit_rex(0,(dreg),0,(basereg));
2182 *(cd->mcodeptr++) = 0x0f;
2183 *(cd->mcodeptr++) = 0x10;
2184 emit_membase(cd, (basereg),(disp),(dreg));
2188 /* Always emit a REX byte, because the instruction size can be smaller when */
2189 /* all register indexes are smaller than 7. */
2190 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2191 *(cd->mcodeptr++) = 0xf2;
2192 emit_byte_rex((dreg),0,(basereg));
2193 *(cd->mcodeptr++) = 0x0f;
2194 *(cd->mcodeptr++) = 0x10;
2195 emit_membase32(cd, (basereg),(disp),(dreg));
2199 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2201 *(cd->mcodeptr++) = 0x66;
2202 emit_rex(0,(dreg),0,(basereg));
2203 *(cd->mcodeptr++) = 0x0f;
2204 *(cd->mcodeptr++) = 0x12;
2205 emit_membase(cd, (basereg),(disp),(dreg));
2209 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2211 *(cd->mcodeptr++) = 0x66;
2212 emit_rex(0,(reg),0,(basereg));
2213 *(cd->mcodeptr++) = 0x0f;
2214 *(cd->mcodeptr++) = 0x13;
2215 emit_membase(cd, (basereg),(disp),(reg));
2219 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2220 *(cd->mcodeptr++) = 0xf3;
2221 emit_rex(0,(reg),(indexreg),(basereg));
2222 *(cd->mcodeptr++) = 0x0f;
2223 *(cd->mcodeptr++) = 0x11;
2224 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2228 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2229 *(cd->mcodeptr++) = 0xf2;
2230 emit_rex(0,(reg),(indexreg),(basereg));
2231 *(cd->mcodeptr++) = 0x0f;
2232 *(cd->mcodeptr++) = 0x11;
2233 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2237 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2238 *(cd->mcodeptr++) = 0xf3;
2239 emit_rex(0,(dreg),(indexreg),(basereg));
2240 *(cd->mcodeptr++) = 0x0f;
2241 *(cd->mcodeptr++) = 0x10;
2242 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2246 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2247 *(cd->mcodeptr++) = 0xf2;
2248 emit_rex(0,(dreg),(indexreg),(basereg));
2249 *(cd->mcodeptr++) = 0x0f;
2250 *(cd->mcodeptr++) = 0x10;
2251 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2255 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2256 *(cd->mcodeptr++) = 0xf3;
2257 emit_rex(0,(dreg),0,(reg));
2258 *(cd->mcodeptr++) = 0x0f;
2259 *(cd->mcodeptr++) = 0x59;
2260 emit_reg((dreg),(reg));
2264 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2265 *(cd->mcodeptr++) = 0xf2;
2266 emit_rex(0,(dreg),0,(reg));
2267 *(cd->mcodeptr++) = 0x0f;
2268 *(cd->mcodeptr++) = 0x59;
2269 emit_reg((dreg),(reg));
2273 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2274 *(cd->mcodeptr++) = 0xf3;
2275 emit_rex(0,(dreg),0,(reg));
2276 *(cd->mcodeptr++) = 0x0f;
2277 *(cd->mcodeptr++) = 0x5c;
2278 emit_reg((dreg),(reg));
2282 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2283 *(cd->mcodeptr++) = 0xf2;
2284 emit_rex(0,(dreg),0,(reg));
2285 *(cd->mcodeptr++) = 0x0f;
2286 *(cd->mcodeptr++) = 0x5c;
2287 emit_reg((dreg),(reg));
2291 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2292 emit_rex(0,(dreg),0,(reg));
2293 *(cd->mcodeptr++) = 0x0f;
2294 *(cd->mcodeptr++) = 0x2e;
2295 emit_reg((dreg),(reg));
2299 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2300 *(cd->mcodeptr++) = 0x66;
2301 emit_rex(0,(dreg),0,(reg));
2302 *(cd->mcodeptr++) = 0x0f;
2303 *(cd->mcodeptr++) = 0x2e;
2304 emit_reg((dreg),(reg));
2308 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2309 emit_rex(0,(dreg),0,(reg));
2310 *(cd->mcodeptr++) = 0x0f;
2311 *(cd->mcodeptr++) = 0x57;
2312 emit_reg((dreg),(reg));
2316 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2317 emit_rex(0,(dreg),0,(basereg));
2318 *(cd->mcodeptr++) = 0x0f;
2319 *(cd->mcodeptr++) = 0x57;
2320 emit_membase(cd, (basereg),(disp),(dreg));
2324 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2325 *(cd->mcodeptr++) = 0x66;
2326 emit_rex(0,(dreg),0,(reg));
2327 *(cd->mcodeptr++) = 0x0f;
2328 *(cd->mcodeptr++) = 0x57;
2329 emit_reg((dreg),(reg));
2333 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2334 *(cd->mcodeptr++) = 0x66;
2335 emit_rex(0,(dreg),0,(basereg));
2336 *(cd->mcodeptr++) = 0x0f;
2337 *(cd->mcodeptr++) = 0x57;
2338 emit_membase(cd, (basereg),(disp),(dreg));
2342 /* system instructions ********************************************************/
2344 void emit_rdtsc(codegendata *cd)
2346 *(cd->mcodeptr++) = 0x0f;
2347 *(cd->mcodeptr++) = 0x31;
2352 * These are local overrides for various environment variables in Emacs.
2353 * Please do not remove this and leave it at the end of the file, where
2354 * Emacs will automagically detect them.
2355 * ---------------------------------------------------------------------
2358 * indent-tabs-mode: t