1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/jit/abi.h"
43 #include "vm/jit/abi-asm.h"
44 #include "vm/jit/asmpart.h"
45 #include "vm/jit/codegen-common.h"
46 #include "vm/jit/emit-common.h"
47 #include "vm/jit/jit.h"
48 #include "vm/jit/patcher-common.h"
49 #include "vm/jit/replace.h"
50 #include "vm/jit/trace.h"
51 #include "vm/jit/trap.h"
53 #include "vmcore/options.h"
56 /* emit_load *******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff;
79 M_ILD(tempreg, REG_SP, disp);
83 M_LLD(tempreg, REG_SP, disp);
86 M_FLD(tempreg, REG_SP, disp);
89 M_DLD(tempreg, REG_SP, disp);
92 vm_abort("emit_load: unknown type %d", src->type);
104 /* emit_store ******************************************************************
106 This function generates the code to store the result of an
107 operation back into a spilled pseudo-variable. If the
108 pseudo-variable has not been spilled in the first place, this
109 function will generate nothing.
111 *******************************************************************************/
113 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
118 /* get required compiler data */
122 if (IS_INMEMORY(dst->flags)) {
125 disp = dst->vv.regoff;
131 M_LST(d, REG_SP, disp);
134 M_FST(d, REG_SP, disp);
137 M_DST(d, REG_SP, disp);
140 vm_abort("emit_store: unknown type %d", dst->type);
146 /* emit_copy *******************************************************************
148 Generates a register/memory to register/memory copy.
150 *******************************************************************************/
152 void emit_copy(jitdata *jd, instruction *iptr)
159 /* get required compiler data */
163 /* get source and destination variables */
165 src = VAROP(iptr->s1);
166 dst = VAROP(iptr->dst);
168 if ((src->vv.regoff != dst->vv.regoff) ||
169 ((src->flags ^ dst->flags) & INMEMORY)) {
171 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
172 /* emit nothing, as the value won't be used anyway */
176 /* If one of the variables resides in memory, we can eliminate
177 the register move from/to the temporary register with the
178 order of getting the destination register and the load. */
180 if (IS_INMEMORY(src->flags)) {
181 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
182 s1 = emit_load(jd, iptr, src, d);
185 s1 = emit_load(jd, iptr, src, REG_IFTMP);
186 d = codegen_reg_of_var(iptr->opc, dst, s1);
201 vm_abort("emit_copy: unknown type %d", src->type);
205 emit_store(jd, iptr, dst, d);
210 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
213 switch (iptr->flags.fields.condition) {
237 /* emit_branch *****************************************************************
239 Emits the code for conditional and unconditional branchs.
241 *******************************************************************************/
243 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
247 /* NOTE: A displacement overflow cannot happen. */
249 /* check which branch to generate */
251 if (condition == BRANCH_UNCONDITIONAL) {
253 /* calculate the different displacements */
255 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
257 M_JMP_IMM(branchdisp);
260 /* calculate the different displacements */
262 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
296 vm_abort("emit_branch: unknown condition %d", condition);
302 /* emit_arithmetic_check *******************************************************
304 Emit an ArithmeticException check.
306 *******************************************************************************/
308 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
310 if (INSTRUCTION_MUST_CHECK(iptr)) {
313 M_ALD_MEM(reg, TRAP_ArithmeticException);
318 /* emit_arrayindexoutofbounds_check ********************************************
320 Emit a ArrayIndexOutOfBoundsException check.
322 *******************************************************************************/
324 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
326 if (INSTRUCTION_MUST_CHECK(iptr)) {
327 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
328 M_ICMP(REG_ITMP3, s2);
330 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
335 /* emit_arraystore_check *******************************************************
337 Emit an ArrayStoreException check.
339 *******************************************************************************/
341 void emit_arraystore_check(codegendata *cd, instruction *iptr)
343 if (INSTRUCTION_MUST_CHECK(iptr)) {
346 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
351 /* emit_classcast_check ********************************************************
353 Emit a ClassCastException check.
355 *******************************************************************************/
357 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
359 if (INSTRUCTION_MUST_CHECK(iptr)) {
377 vm_abort("emit_classcast_check: unknown condition %d", condition);
379 M_ALD_MEM(s1, TRAP_ClassCastException);
384 /* emit_nullpointer_check ******************************************************
386 Emit a NullPointerException check.
388 *******************************************************************************/
390 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
392 if (INSTRUCTION_MUST_CHECK(iptr)) {
395 M_ALD_MEM(reg, TRAP_NullPointerException);
400 /* emit_exception_check ********************************************************
402 Emit an Exception check.
404 *******************************************************************************/
406 void emit_exception_check(codegendata *cd, instruction *iptr)
408 if (INSTRUCTION_MUST_CHECK(iptr)) {
411 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
416 /* emit_trap_compiler **********************************************************
418 Emit a trap instruction which calls the JIT compiler.
420 *******************************************************************************/
422 void emit_trap_compiler(codegendata *cd)
424 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
428 /* emit_trap *******************************************************************
430 Emit a trap instruction and return the original machine code.
432 *******************************************************************************/
434 uint32_t emit_trap(codegendata *cd)
438 /* Get machine code which is patched back in later. The trap is 2
441 mcode = *((uint16_t *) cd->mcodeptr);
443 /* XXX This needs to be change to INT3 when the debugging problems
444 with gdb are resolved. */
452 /* emit_verbosecall_enter ******************************************************
454 Generates the code for the call trace.
456 *******************************************************************************/
459 void emit_verbosecall_enter(jitdata *jd)
469 /* get required compiler data */
478 /* mark trace code */
482 /* keep 16-byte stack alignment */
484 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
485 ALIGN_2(stackframesize);
487 M_LSUB_IMM(stackframesize * 8, REG_SP);
489 /* save argument registers */
491 for (i = 0; i < md->paramcount; i++) {
492 if (!md->params[i].inmemory) {
493 s = md->params[i].regoff;
495 switch (md->paramtypes[i].type) {
499 M_LST(s, REG_SP, i * 8);
503 M_DST(s, REG_SP, i * 8);
509 /* save all argument and temporary registers for leaf methods */
511 if (code_is_leafmethod(code)) {
512 for (i = 0; i < INT_ARG_CNT; i++)
513 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
515 for (i = 0; i < FLT_ARG_CNT; i++)
516 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
518 for (i = 0; i < INT_TMP_CNT; i++)
519 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
521 for (i = 0; i < FLT_TMP_CNT; i++)
522 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
525 M_MOV_IMM(m, REG_A0);
526 M_MOV(REG_SP, REG_A1);
527 M_MOV(REG_SP, REG_A2);
528 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
529 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
532 /* restore argument registers */
534 for (i = 0; i < md->paramcount; i++) {
535 if (!md->params[i].inmemory) {
536 s = md->params[i].regoff;
538 switch (md->paramtypes[i].type) {
542 M_LLD(s, REG_SP, i * 8);
546 M_DLD(s, REG_SP, i * 8);
553 /* restore all argument and temporary registers for leaf methods */
555 if (code_is_leafmethod(code)) {
556 for (i = 0; i < INT_ARG_CNT; i++)
557 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
559 for (i = 0; i < FLT_ARG_CNT; i++)
560 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
562 for (i = 0; i < INT_TMP_CNT; i++)
563 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
565 for (i = 0; i < FLT_TMP_CNT; i++)
566 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
569 M_LADD_IMM(stackframesize * 8, REG_SP);
571 /* mark trace code */
575 #endif /* !defined(NDEBUG) */
578 /* emit_verbosecall_exit *******************************************************
580 Generates the code for the call trace.
582 *******************************************************************************/
585 void emit_verbosecall_exit(jitdata *jd)
592 /* get required compiler data */
600 /* mark trace code */
604 /* keep 16-byte stack alignment */
606 M_ASUB_IMM(2 * 8, REG_SP);
608 /* save return value */
610 switch (md->returntype.type) {
614 M_LST(REG_RESULT, REG_SP, 0 * 8);
618 M_DST(REG_FRESULT, REG_SP, 0 * 8);
622 M_MOV_IMM(m, REG_A0);
623 M_MOV(REG_SP, REG_A1);
625 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
628 /* restore return value */
630 switch (md->returntype.type) {
634 M_LLD(REG_RESULT, REG_SP, 0 * 8);
638 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
642 M_AADD_IMM(2 * 8, REG_SP);
644 /* mark trace code */
648 #endif /* !defined(NDEBUG) */
651 /* code generation functions **************************************************/
653 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
655 if ((basereg == REG_SP) || (basereg == R12)) {
657 emit_address_byte(0, dreg, REG_SP);
658 emit_address_byte(0, REG_SP, REG_SP);
660 } else if (IS_IMM8(disp)) {
661 emit_address_byte(1, dreg, REG_SP);
662 emit_address_byte(0, REG_SP, REG_SP);
666 emit_address_byte(2, dreg, REG_SP);
667 emit_address_byte(0, REG_SP, REG_SP);
671 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
672 emit_address_byte(0,(dreg),(basereg));
674 } else if ((basereg) == RIP) {
675 emit_address_byte(0, dreg, RBP);
680 emit_address_byte(1, dreg, basereg);
684 emit_address_byte(2, dreg, basereg);
691 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
693 if ((basereg == REG_SP) || (basereg == R12)) {
694 emit_address_byte(2, dreg, REG_SP);
695 emit_address_byte(0, REG_SP, REG_SP);
699 emit_address_byte(2, dreg, basereg);
705 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
708 emit_address_byte(0, reg, 4);
709 emit_address_byte(scale, indexreg, 5);
712 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
713 emit_address_byte(0, reg, 4);
714 emit_address_byte(scale, indexreg, basereg);
716 else if (IS_IMM8(disp)) {
717 emit_address_byte(1, reg, 4);
718 emit_address_byte(scale, indexreg, basereg);
722 emit_address_byte(2, reg, 4);
723 emit_address_byte(scale, indexreg, basereg);
729 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
732 varinfo *v_s1,*v_s2,*v_dst;
735 /* get required compiler data */
739 v_s1 = VAROP(iptr->s1);
740 v_s2 = VAROP(iptr->sx.s23.s2);
741 v_dst = VAROP(iptr->dst);
743 s1 = v_s1->vv.regoff;
744 s2 = v_s2->vv.regoff;
745 d = v_dst->vv.regoff;
747 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
749 if (IS_INMEMORY(v_dst->flags)) {
750 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
752 M_ILD(RCX, REG_SP, s2);
753 emit_shiftl_membase(cd, shift_op, REG_SP, d);
756 M_ILD(RCX, REG_SP, s2);
757 M_ILD(REG_ITMP2, REG_SP, s1);
758 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
759 M_IST(REG_ITMP2, REG_SP, d);
762 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
763 /* s1 may be equal to RCX */
766 M_ILD(REG_ITMP1, REG_SP, s2);
767 M_IST(s1, REG_SP, d);
768 M_INTMOVE(REG_ITMP1, RCX);
771 M_IST(s1, REG_SP, d);
772 M_ILD(RCX, REG_SP, s2);
776 M_ILD(RCX, REG_SP, s2);
777 M_IST(s1, REG_SP, d);
780 emit_shiftl_membase(cd, shift_op, REG_SP, d);
782 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
785 emit_shiftl_membase(cd, shift_op, REG_SP, d);
789 M_ILD(REG_ITMP2, REG_SP, s1);
790 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
791 M_IST(REG_ITMP2, REG_SP, d);
795 /* s1 may be equal to RCX */
796 M_IST(s1, REG_SP, d);
798 emit_shiftl_membase(cd, shift_op, REG_SP, d);
801 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
809 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
810 M_ILD(RCX, REG_SP, s2);
811 M_ILD(d, REG_SP, s1);
812 emit_shiftl_reg(cd, shift_op, d);
814 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
815 /* s1 may be equal to RCX */
817 M_ILD(RCX, REG_SP, s2);
818 emit_shiftl_reg(cd, shift_op, d);
820 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
822 M_ILD(d, REG_SP, s1);
823 emit_shiftl_reg(cd, shift_op, d);
826 /* s1 may be equal to RCX */
829 /* d cannot be used to backup s1 since this would
831 M_INTMOVE(s1, REG_ITMP3);
833 M_INTMOVE(REG_ITMP3, d);
841 /* d may be equal to s2 */
845 emit_shiftl_reg(cd, shift_op, d);
849 M_INTMOVE(REG_ITMP3, RCX);
851 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
856 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
859 varinfo *v_s1,*v_s2,*v_dst;
862 /* get required compiler data */
866 v_s1 = VAROP(iptr->s1);
867 v_s2 = VAROP(iptr->sx.s23.s2);
868 v_dst = VAROP(iptr->dst);
870 s1 = v_s1->vv.regoff;
871 s2 = v_s2->vv.regoff;
872 d = v_dst->vv.regoff;
874 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
876 if (IS_INMEMORY(v_dst->flags)) {
877 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
879 M_ILD(RCX, REG_SP, s2);
880 emit_shift_membase(cd, shift_op, REG_SP, d);
883 M_ILD(RCX, REG_SP, s2);
884 M_LLD(REG_ITMP2, REG_SP, s1);
885 emit_shift_reg(cd, shift_op, REG_ITMP2);
886 M_LST(REG_ITMP2, REG_SP, d);
889 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
890 /* s1 may be equal to RCX */
893 M_ILD(REG_ITMP1, REG_SP, s2);
894 M_LST(s1, REG_SP, d);
895 M_INTMOVE(REG_ITMP1, RCX);
898 M_LST(s1, REG_SP, d);
899 M_ILD(RCX, REG_SP, s2);
903 M_ILD(RCX, REG_SP, s2);
904 M_LST(s1, REG_SP, d);
907 emit_shift_membase(cd, shift_op, REG_SP, d);
909 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
912 emit_shift_membase(cd, shift_op, REG_SP, d);
916 M_LLD(REG_ITMP2, REG_SP, s1);
917 emit_shift_reg(cd, shift_op, REG_ITMP2);
918 M_LST(REG_ITMP2, REG_SP, d);
922 /* s1 may be equal to RCX */
923 M_LST(s1, REG_SP, d);
925 emit_shift_membase(cd, shift_op, REG_SP, d);
928 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
936 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
937 M_ILD(RCX, REG_SP, s2);
938 M_LLD(d, REG_SP, s1);
939 emit_shift_reg(cd, shift_op, d);
941 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
942 /* s1 may be equal to RCX */
944 M_ILD(RCX, REG_SP, s2);
945 emit_shift_reg(cd, shift_op, d);
947 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
949 M_LLD(d, REG_SP, s1);
950 emit_shift_reg(cd, shift_op, d);
953 /* s1 may be equal to RCX */
956 /* d cannot be used to backup s1 since this would
958 M_INTMOVE(s1, REG_ITMP3);
960 M_INTMOVE(REG_ITMP3, d);
968 /* d may be equal to s2 */
972 emit_shift_reg(cd, shift_op, d);
976 M_INTMOVE(REG_ITMP3, RCX);
978 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
983 /* low-level code emitter functions *******************************************/
985 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
987 emit_rex(1,(reg),0,(dreg));
988 *(cd->mcodeptr++) = 0x89;
989 emit_reg((reg),(dreg));
993 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
995 emit_rex(1,0,0,(reg));
996 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1001 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1003 emit_rex(0,(reg),0,(dreg));
1004 *(cd->mcodeptr++) = 0x89;
1005 emit_reg((reg),(dreg));
1009 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1010 emit_rex(0,0,0,(reg));
1011 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1016 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1017 emit_rex(1,(reg),0,(basereg));
1018 *(cd->mcodeptr++) = 0x8b;
1019 emit_membase(cd, (basereg),(disp),(reg));
1024 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1025 * constant membase immediate length of 32bit
1027 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1028 emit_rex(1,(reg),0,(basereg));
1029 *(cd->mcodeptr++) = 0x8b;
1030 emit_membase32(cd, (basereg),(disp),(reg));
1034 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1036 emit_rex(0,(reg),0,(basereg));
1037 *(cd->mcodeptr++) = 0x8b;
1038 emit_membase(cd, (basereg),(disp),(reg));
1042 /* ATTENTION: Always emit a REX byte, because the instruction size can
1043 be smaller when all register indexes are smaller than 7. */
1044 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1046 emit_byte_rex((reg),0,(basereg));
1047 *(cd->mcodeptr++) = 0x8b;
1048 emit_membase32(cd, (basereg),(disp),(reg));
1052 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1053 emit_rex(1,(reg),0,(basereg));
1054 *(cd->mcodeptr++) = 0x89;
1055 emit_membase(cd, (basereg),(disp),(reg));
1059 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1060 emit_rex(1,(reg),0,(basereg));
1061 *(cd->mcodeptr++) = 0x89;
1062 emit_membase32(cd, (basereg),(disp),(reg));
1066 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1067 emit_rex(0,(reg),0,(basereg));
1068 *(cd->mcodeptr++) = 0x89;
1069 emit_membase(cd, (basereg),(disp),(reg));
1073 /* Always emit a REX byte, because the instruction size can be smaller when */
1074 /* all register indexes are smaller than 7. */
1075 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1076 emit_byte_rex((reg),0,(basereg));
1077 *(cd->mcodeptr++) = 0x89;
1078 emit_membase32(cd, (basereg),(disp),(reg));
1082 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1083 emit_rex(1,(reg),(indexreg),(basereg));
1084 *(cd->mcodeptr++) = 0x8b;
1085 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1089 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1090 emit_rex(0,(reg),(indexreg),(basereg));
1091 *(cd->mcodeptr++) = 0x8b;
1092 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1096 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1097 emit_rex(1,(reg),(indexreg),(basereg));
1098 *(cd->mcodeptr++) = 0x89;
1099 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1103 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1104 emit_rex(0,(reg),(indexreg),(basereg));
1105 *(cd->mcodeptr++) = 0x89;
1106 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1110 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1111 *(cd->mcodeptr++) = 0x66;
1112 emit_rex(0,(reg),(indexreg),(basereg));
1113 *(cd->mcodeptr++) = 0x89;
1114 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1118 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1119 emit_byte_rex((reg),(indexreg),(basereg));
1120 *(cd->mcodeptr++) = 0x88;
1121 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1125 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1126 emit_rex(1,0,0,(basereg));
1127 *(cd->mcodeptr++) = 0xc7;
1128 emit_membase(cd, (basereg),(disp),0);
1133 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1134 emit_rex(1,0,0,(basereg));
1135 *(cd->mcodeptr++) = 0xc7;
1136 emit_membase32(cd, (basereg),(disp),0);
1141 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1142 emit_rex(0,0,0,(basereg));
1143 *(cd->mcodeptr++) = 0xc7;
1144 emit_membase(cd, (basereg),(disp),0);
1149 /* Always emit a REX byte, because the instruction size can be smaller when */
1150 /* all register indexes are smaller than 7. */
1151 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1152 emit_byte_rex(0,0,(basereg));
1153 *(cd->mcodeptr++) = 0xc7;
1154 emit_membase32(cd, (basereg),(disp),0);
1159 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1161 emit_rex(1,(dreg),0,(reg));
1162 *(cd->mcodeptr++) = 0x0f;
1163 *(cd->mcodeptr++) = 0xbe;
1164 /* XXX: why do reg and dreg have to be exchanged */
1165 emit_reg((dreg),(reg));
1169 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1171 emit_rex(1,(dreg),0,(reg));
1172 *(cd->mcodeptr++) = 0x0f;
1173 *(cd->mcodeptr++) = 0xbf;
1174 /* XXX: why do reg and dreg have to be exchanged */
1175 emit_reg((dreg),(reg));
1179 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1181 emit_rex(1,(dreg),0,(reg));
1182 *(cd->mcodeptr++) = 0x63;
1183 /* XXX: why do reg and dreg have to be exchanged */
1184 emit_reg((dreg),(reg));
1188 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1190 emit_rex(1,(dreg),0,(reg));
1191 *(cd->mcodeptr++) = 0x0f;
1192 *(cd->mcodeptr++) = 0xb7;
1193 /* XXX: why do reg and dreg have to be exchanged */
1194 emit_reg((dreg),(reg));
1198 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1199 emit_rex(1,(reg),(indexreg),(basereg));
1200 *(cd->mcodeptr++) = 0x0f;
1201 *(cd->mcodeptr++) = 0xbf;
1202 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1206 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1207 emit_rex(1,(reg),(indexreg),(basereg));
1208 *(cd->mcodeptr++) = 0x0f;
1209 *(cd->mcodeptr++) = 0xbe;
1210 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1214 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1215 emit_rex(1,(reg),(indexreg),(basereg));
1216 *(cd->mcodeptr++) = 0x0f;
1217 *(cd->mcodeptr++) = 0xb7;
1218 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1222 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1224 emit_rex(1,0,(indexreg),(basereg));
1225 *(cd->mcodeptr++) = 0xc7;
1226 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1231 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1233 emit_rex(0,0,(indexreg),(basereg));
1234 *(cd->mcodeptr++) = 0xc7;
1235 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1240 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1242 *(cd->mcodeptr++) = 0x66;
1243 emit_rex(0,0,(indexreg),(basereg));
1244 *(cd->mcodeptr++) = 0xc7;
1245 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1250 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1252 emit_rex(0,0,(indexreg),(basereg));
1253 *(cd->mcodeptr++) = 0xc6;
1254 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1259 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1261 emit_rex(1, dreg, 0, 0);
1262 *(cd->mcodeptr++) = 0x8b;
1263 emit_address_byte(0, dreg, 4);
1271 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1273 emit_rex(1,(reg),0,(dreg));
1274 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1275 emit_reg((reg),(dreg));
1279 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1281 emit_rex(0,(reg),0,(dreg));
1282 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1283 emit_reg((reg),(dreg));
1287 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1289 emit_rex(1,(reg),0,(basereg));
1290 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1291 emit_membase(cd, (basereg),(disp),(reg));
1295 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1297 emit_rex(0,(reg),0,(basereg));
1298 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1299 emit_membase(cd, (basereg),(disp),(reg));
1303 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1305 emit_rex(1,(reg),0,(basereg));
1306 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1307 emit_membase(cd, (basereg),(disp),(reg));
1311 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1313 emit_rex(0,(reg),0,(basereg));
1314 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1315 emit_membase(cd, (basereg),(disp),(reg));
1319 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1321 emit_rex(1,0,0,(dreg));
1322 *(cd->mcodeptr++) = 0x83;
1323 emit_reg((opc),(dreg));
1326 emit_rex(1,0,0,(dreg));
1327 *(cd->mcodeptr++) = 0x81;
1328 emit_reg((opc),(dreg));
1334 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1336 emit_rex(1,0,0,(dreg));
1337 *(cd->mcodeptr++) = 0x81;
1338 emit_reg((opc),(dreg));
1343 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1345 emit_rex(0,0,0,(dreg));
1346 *(cd->mcodeptr++) = 0x81;
1347 emit_reg((opc),(dreg));
1352 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1354 emit_rex(0,0,0,(dreg));
1355 *(cd->mcodeptr++) = 0x83;
1356 emit_reg((opc),(dreg));
1359 emit_rex(0,0,0,(dreg));
1360 *(cd->mcodeptr++) = 0x81;
1361 emit_reg((opc),(dreg));
1367 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1369 emit_rex(1,0,0,(basereg));
1370 *(cd->mcodeptr++) = 0x83;
1371 emit_membase(cd, (basereg),(disp),(opc));
1374 emit_rex(1,0,0,(basereg));
1375 *(cd->mcodeptr++) = 0x81;
1376 emit_membase(cd, (basereg),(disp),(opc));
1382 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1384 emit_rex(0,0,0,(basereg));
1385 *(cd->mcodeptr++) = 0x83;
1386 emit_membase(cd, (basereg),(disp),(opc));
1389 emit_rex(0,0,0,(basereg));
1390 *(cd->mcodeptr++) = 0x81;
1391 emit_membase(cd, (basereg),(disp),(opc));
1397 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1398 emit_rex(1,(reg),0,(dreg));
1399 *(cd->mcodeptr++) = 0x85;
1400 emit_reg((reg),(dreg));
1404 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1405 emit_rex(0,(reg),0,(dreg));
1406 *(cd->mcodeptr++) = 0x85;
1407 emit_reg((reg),(dreg));
1411 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1412 *(cd->mcodeptr++) = 0xf7;
1418 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1419 *(cd->mcodeptr++) = 0x66;
1420 *(cd->mcodeptr++) = 0xf7;
1426 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1427 *(cd->mcodeptr++) = 0xf6;
1433 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1434 emit_rex(1,(reg),0,(basereg));
1435 *(cd->mcodeptr++) = 0x8d;
1436 emit_membase(cd, (basereg),(disp),(reg));
1440 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1441 emit_rex(0,(reg),0,(basereg));
1442 *(cd->mcodeptr++) = 0x8d;
1443 emit_membase(cd, (basereg),(disp),(reg));
1447 void emit_incl_reg(codegendata *cd, s8 reg)
1449 *(cd->mcodeptr++) = 0xff;
1453 void emit_incq_reg(codegendata *cd, s8 reg)
1455 emit_rex(1,0,0,(reg));
1456 *(cd->mcodeptr++) = 0xff;
1460 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1462 emit_rex(0,0,0,(basereg));
1463 *(cd->mcodeptr++) = 0xff;
1464 emit_membase(cd, (basereg),(disp),0);
1467 void emit_incq_membase(codegendata *cd, s8 basereg, s8 disp)
1469 emit_rex(1,0,0,(basereg));
1470 *(cd->mcodeptr++) = 0xff;
1471 emit_membase(cd, (basereg),(disp),0);
1476 void emit_cltd(codegendata *cd) {
1477 *(cd->mcodeptr++) = 0x99;
1481 void emit_cqto(codegendata *cd) {
1483 *(cd->mcodeptr++) = 0x99;
1488 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1489 emit_rex(1,(dreg),0,(reg));
1490 *(cd->mcodeptr++) = 0x0f;
1491 *(cd->mcodeptr++) = 0xaf;
1492 emit_reg((dreg),(reg));
1496 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1497 emit_rex(0,(dreg),0,(reg));
1498 *(cd->mcodeptr++) = 0x0f;
1499 *(cd->mcodeptr++) = 0xaf;
1500 emit_reg((dreg),(reg));
1504 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1505 emit_rex(1,(dreg),0,(basereg));
1506 *(cd->mcodeptr++) = 0x0f;
1507 *(cd->mcodeptr++) = 0xaf;
1508 emit_membase(cd, (basereg),(disp),(dreg));
1512 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1513 emit_rex(0,(dreg),0,(basereg));
1514 *(cd->mcodeptr++) = 0x0f;
1515 *(cd->mcodeptr++) = 0xaf;
1516 emit_membase(cd, (basereg),(disp),(dreg));
1520 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1521 if (IS_IMM8((imm))) {
1522 emit_rex(1,0,0,(dreg));
1523 *(cd->mcodeptr++) = 0x6b;
1527 emit_rex(1,0,0,(dreg));
1528 *(cd->mcodeptr++) = 0x69;
1535 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1536 if (IS_IMM8((imm))) {
1537 emit_rex(1,(dreg),0,(reg));
1538 *(cd->mcodeptr++) = 0x6b;
1539 emit_reg((dreg),(reg));
1542 emit_rex(1,(dreg),0,(reg));
1543 *(cd->mcodeptr++) = 0x69;
1544 emit_reg((dreg),(reg));
1550 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1551 if (IS_IMM8((imm))) {
1552 emit_rex(0,(dreg),0,(reg));
1553 *(cd->mcodeptr++) = 0x6b;
1554 emit_reg((dreg),(reg));
1557 emit_rex(0,(dreg),0,(reg));
1558 *(cd->mcodeptr++) = 0x69;
1559 emit_reg((dreg),(reg));
1565 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1566 if (IS_IMM8((imm))) {
1567 emit_rex(1,(dreg),0,(basereg));
1568 *(cd->mcodeptr++) = 0x6b;
1569 emit_membase(cd, (basereg),(disp),(dreg));
1572 emit_rex(1,(dreg),0,(basereg));
1573 *(cd->mcodeptr++) = 0x69;
1574 emit_membase(cd, (basereg),(disp),(dreg));
1580 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1581 if (IS_IMM8((imm))) {
1582 emit_rex(0,(dreg),0,(basereg));
1583 *(cd->mcodeptr++) = 0x6b;
1584 emit_membase(cd, (basereg),(disp),(dreg));
1587 emit_rex(0,(dreg),0,(basereg));
1588 *(cd->mcodeptr++) = 0x69;
1589 emit_membase(cd, (basereg),(disp),(dreg));
1595 void emit_idiv_reg(codegendata *cd, s8 reg) {
1596 emit_rex(1,0,0,(reg));
1597 *(cd->mcodeptr++) = 0xf7;
1602 void emit_idivl_reg(codegendata *cd, s8 reg) {
1603 emit_rex(0,0,0,(reg));
1604 *(cd->mcodeptr++) = 0xf7;
1613 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1614 emit_rex(1,0,0,(reg));
1615 *(cd->mcodeptr++) = 0xd3;
1616 emit_reg((opc),(reg));
1620 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1621 emit_rex(0,0,0,(reg));
1622 *(cd->mcodeptr++) = 0xd3;
1623 emit_reg((opc),(reg));
1627 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1628 emit_rex(1,0,0,(basereg));
1629 *(cd->mcodeptr++) = 0xd3;
1630 emit_membase(cd, (basereg),(disp),(opc));
1634 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1635 emit_rex(0,0,0,(basereg));
1636 *(cd->mcodeptr++) = 0xd3;
1637 emit_membase(cd, (basereg),(disp),(opc));
1641 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1643 emit_rex(1,0,0,(dreg));
1644 *(cd->mcodeptr++) = 0xd1;
1645 emit_reg((opc),(dreg));
1647 emit_rex(1,0,0,(dreg));
1648 *(cd->mcodeptr++) = 0xc1;
1649 emit_reg((opc),(dreg));
1655 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1657 emit_rex(0,0,0,(dreg));
1658 *(cd->mcodeptr++) = 0xd1;
1659 emit_reg((opc),(dreg));
1661 emit_rex(0,0,0,(dreg));
1662 *(cd->mcodeptr++) = 0xc1;
1663 emit_reg((opc),(dreg));
1669 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1671 emit_rex(1,0,0,(basereg));
1672 *(cd->mcodeptr++) = 0xd1;
1673 emit_membase(cd, (basereg),(disp),(opc));
1675 emit_rex(1,0,0,(basereg));
1676 *(cd->mcodeptr++) = 0xc1;
1677 emit_membase(cd, (basereg),(disp),(opc));
1683 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1685 emit_rex(0,0,0,(basereg));
1686 *(cd->mcodeptr++) = 0xd1;
1687 emit_membase(cd, (basereg),(disp),(opc));
1689 emit_rex(0,0,0,(basereg));
1690 *(cd->mcodeptr++) = 0xc1;
1691 emit_membase(cd, (basereg),(disp),(opc));
1701 void emit_jmp_imm(codegendata *cd, s8 imm) {
1702 *(cd->mcodeptr++) = 0xe9;
1706 /* like emit_jmp_imm but allows 8 bit optimization */
1707 void emit_jmp_imm2(codegendata *cd, s8 imm) {
1709 *(cd->mcodeptr++) = 0xeb;
1713 *(cd->mcodeptr++) = 0xe9;
1719 void emit_jmp_reg(codegendata *cd, s8 reg) {
1720 emit_rex(0,0,0,(reg));
1721 *(cd->mcodeptr++) = 0xff;
1726 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1727 *(cd->mcodeptr++) = 0x0f;
1728 *(cd->mcodeptr++) = (0x80 + (opc));
1735 * conditional set and move operations
1738 /* we need the rex byte to get all low bytes */
1739 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1741 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1742 *(cd->mcodeptr++) = 0x0f;
1743 *(cd->mcodeptr++) = (0x90 + (opc));
1748 /* we need the rex byte to get all low bytes */
1749 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1751 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1752 *(cd->mcodeptr++) = 0x0f;
1753 *(cd->mcodeptr++) = (0x90 + (opc));
1754 emit_membase(cd, (basereg),(disp),0);
1758 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1760 emit_rex(1,(dreg),0,(reg));
1761 *(cd->mcodeptr++) = 0x0f;
1762 *(cd->mcodeptr++) = (0x40 + (opc));
1763 emit_reg((dreg),(reg));
1767 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1769 emit_rex(0,(dreg),0,(reg));
1770 *(cd->mcodeptr++) = 0x0f;
1771 *(cd->mcodeptr++) = (0x40 + (opc));
1772 emit_reg((dreg),(reg));
1776 void emit_neg_reg(codegendata *cd, s8 reg)
1778 emit_rex(1,0,0,(reg));
1779 *(cd->mcodeptr++) = 0xf7;
1784 void emit_negl_reg(codegendata *cd, s8 reg)
1786 emit_rex(0,0,0,(reg));
1787 *(cd->mcodeptr++) = 0xf7;
1792 void emit_push_reg(codegendata *cd, s8 reg) {
1793 emit_rex(0,0,0,(reg));
1794 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1798 void emit_push_imm(codegendata *cd, s8 imm) {
1799 *(cd->mcodeptr++) = 0x68;
1804 void emit_pop_reg(codegendata *cd, s8 reg) {
1805 emit_rex(0,0,0,(reg));
1806 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1810 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1811 emit_rex(1,(reg),0,(dreg));
1812 *(cd->mcodeptr++) = 0x87;
1813 emit_reg((reg),(dreg));
1821 void emit_call_reg(codegendata *cd, s8 reg)
1823 emit_rex(0,0,0,(reg));
1824 *(cd->mcodeptr++) = 0xff;
1829 void emit_call_imm(codegendata *cd, s8 imm)
1831 *(cd->mcodeptr++) = 0xe8;
1836 void emit_call_mem(codegendata *cd, ptrint mem)
1838 *(cd->mcodeptr++) = 0xff;
1845 * floating point instructions (SSE2)
1847 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1848 *(cd->mcodeptr++) = 0xf2;
1849 emit_rex(0,(dreg),0,(reg));
1850 *(cd->mcodeptr++) = 0x0f;
1851 *(cd->mcodeptr++) = 0x58;
1852 emit_reg((dreg),(reg));
1856 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1857 *(cd->mcodeptr++) = 0xf3;
1858 emit_rex(0,(dreg),0,(reg));
1859 *(cd->mcodeptr++) = 0x0f;
1860 *(cd->mcodeptr++) = 0x58;
1861 emit_reg((dreg),(reg));
1865 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1866 *(cd->mcodeptr++) = 0xf3;
1867 emit_rex(1,(dreg),0,(reg));
1868 *(cd->mcodeptr++) = 0x0f;
1869 *(cd->mcodeptr++) = 0x2a;
1870 emit_reg((dreg),(reg));
1874 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1875 *(cd->mcodeptr++) = 0xf3;
1876 emit_rex(0,(dreg),0,(reg));
1877 *(cd->mcodeptr++) = 0x0f;
1878 *(cd->mcodeptr++) = 0x2a;
1879 emit_reg((dreg),(reg));
1883 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1884 *(cd->mcodeptr++) = 0xf2;
1885 emit_rex(1,(dreg),0,(reg));
1886 *(cd->mcodeptr++) = 0x0f;
1887 *(cd->mcodeptr++) = 0x2a;
1888 emit_reg((dreg),(reg));
1892 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1893 *(cd->mcodeptr++) = 0xf2;
1894 emit_rex(0,(dreg),0,(reg));
1895 *(cd->mcodeptr++) = 0x0f;
1896 *(cd->mcodeptr++) = 0x2a;
1897 emit_reg((dreg),(reg));
1901 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1902 *(cd->mcodeptr++) = 0xf3;
1903 emit_rex(0,(dreg),0,(reg));
1904 *(cd->mcodeptr++) = 0x0f;
1905 *(cd->mcodeptr++) = 0x5a;
1906 emit_reg((dreg),(reg));
1910 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1911 *(cd->mcodeptr++) = 0xf2;
1912 emit_rex(0,(dreg),0,(reg));
1913 *(cd->mcodeptr++) = 0x0f;
1914 *(cd->mcodeptr++) = 0x5a;
1915 emit_reg((dreg),(reg));
1919 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1920 *(cd->mcodeptr++) = 0xf3;
1921 emit_rex(1,(dreg),0,(reg));
1922 *(cd->mcodeptr++) = 0x0f;
1923 *(cd->mcodeptr++) = 0x2c;
1924 emit_reg((dreg),(reg));
1928 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1929 *(cd->mcodeptr++) = 0xf3;
1930 emit_rex(0,(dreg),0,(reg));
1931 *(cd->mcodeptr++) = 0x0f;
1932 *(cd->mcodeptr++) = 0x2c;
1933 emit_reg((dreg),(reg));
1937 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1938 *(cd->mcodeptr++) = 0xf2;
1939 emit_rex(1,(dreg),0,(reg));
1940 *(cd->mcodeptr++) = 0x0f;
1941 *(cd->mcodeptr++) = 0x2c;
1942 emit_reg((dreg),(reg));
1946 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1947 *(cd->mcodeptr++) = 0xf2;
1948 emit_rex(0,(dreg),0,(reg));
1949 *(cd->mcodeptr++) = 0x0f;
1950 *(cd->mcodeptr++) = 0x2c;
1951 emit_reg((dreg),(reg));
1955 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1956 *(cd->mcodeptr++) = 0xf3;
1957 emit_rex(0,(dreg),0,(reg));
1958 *(cd->mcodeptr++) = 0x0f;
1959 *(cd->mcodeptr++) = 0x5e;
1960 emit_reg((dreg),(reg));
1964 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1965 *(cd->mcodeptr++) = 0xf2;
1966 emit_rex(0,(dreg),0,(reg));
1967 *(cd->mcodeptr++) = 0x0f;
1968 *(cd->mcodeptr++) = 0x5e;
1969 emit_reg((dreg),(reg));
1973 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1974 *(cd->mcodeptr++) = 0x66;
1975 emit_rex(1,(freg),0,(reg));
1976 *(cd->mcodeptr++) = 0x0f;
1977 *(cd->mcodeptr++) = 0x6e;
1978 emit_reg((freg),(reg));
1982 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1983 *(cd->mcodeptr++) = 0x66;
1984 emit_rex(1,(freg),0,(reg));
1985 *(cd->mcodeptr++) = 0x0f;
1986 *(cd->mcodeptr++) = 0x7e;
1987 emit_reg((freg),(reg));
1991 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1992 *(cd->mcodeptr++) = 0x66;
1993 emit_rex(0,(reg),0,(basereg));
1994 *(cd->mcodeptr++) = 0x0f;
1995 *(cd->mcodeptr++) = 0x7e;
1996 emit_membase(cd, (basereg),(disp),(reg));
2000 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2001 *(cd->mcodeptr++) = 0x66;
2002 emit_rex(0,(reg),(indexreg),(basereg));
2003 *(cd->mcodeptr++) = 0x0f;
2004 *(cd->mcodeptr++) = 0x7e;
2005 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2009 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2010 *(cd->mcodeptr++) = 0x66;
2011 emit_rex(1,(dreg),0,(basereg));
2012 *(cd->mcodeptr++) = 0x0f;
2013 *(cd->mcodeptr++) = 0x6e;
2014 emit_membase(cd, (basereg),(disp),(dreg));
2018 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2019 *(cd->mcodeptr++) = 0x66;
2020 emit_rex(0,(dreg),0,(basereg));
2021 *(cd->mcodeptr++) = 0x0f;
2022 *(cd->mcodeptr++) = 0x6e;
2023 emit_membase(cd, (basereg),(disp),(dreg));
2027 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2028 *(cd->mcodeptr++) = 0x66;
2029 emit_rex(0,(dreg),(indexreg),(basereg));
2030 *(cd->mcodeptr++) = 0x0f;
2031 *(cd->mcodeptr++) = 0x6e;
2032 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2036 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2037 *(cd->mcodeptr++) = 0xf3;
2038 emit_rex(0,(dreg),0,(reg));
2039 *(cd->mcodeptr++) = 0x0f;
2040 *(cd->mcodeptr++) = 0x7e;
2041 emit_reg((dreg),(reg));
2045 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2046 *(cd->mcodeptr++) = 0x66;
2047 emit_rex(0,(reg),0,(basereg));
2048 *(cd->mcodeptr++) = 0x0f;
2049 *(cd->mcodeptr++) = 0xd6;
2050 emit_membase(cd, (basereg),(disp),(reg));
2054 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2055 *(cd->mcodeptr++) = 0xf3;
2056 emit_rex(0,(dreg),0,(basereg));
2057 *(cd->mcodeptr++) = 0x0f;
2058 *(cd->mcodeptr++) = 0x7e;
2059 emit_membase(cd, (basereg),(disp),(dreg));
2063 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2064 *(cd->mcodeptr++) = 0xf3;
2065 emit_rex(0,(reg),0,(dreg));
2066 *(cd->mcodeptr++) = 0x0f;
2067 *(cd->mcodeptr++) = 0x10;
2068 emit_reg((reg),(dreg));
2072 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2073 *(cd->mcodeptr++) = 0xf2;
2074 emit_rex(0,(reg),0,(dreg));
2075 *(cd->mcodeptr++) = 0x0f;
2076 *(cd->mcodeptr++) = 0x10;
2077 emit_reg((reg),(dreg));
2081 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2082 *(cd->mcodeptr++) = 0xf3;
2083 emit_rex(0,(reg),0,(basereg));
2084 *(cd->mcodeptr++) = 0x0f;
2085 *(cd->mcodeptr++) = 0x11;
2086 emit_membase(cd, (basereg),(disp),(reg));
2090 /* Always emit a REX byte, because the instruction size can be smaller when */
2091 /* all register indexes are smaller than 7. */
2092 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2093 *(cd->mcodeptr++) = 0xf3;
2094 emit_byte_rex((reg),0,(basereg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = 0x11;
2097 emit_membase32(cd, (basereg),(disp),(reg));
2101 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2102 *(cd->mcodeptr++) = 0xf2;
2103 emit_rex(0,(reg),0,(basereg));
2104 *(cd->mcodeptr++) = 0x0f;
2105 *(cd->mcodeptr++) = 0x11;
2106 emit_membase(cd, (basereg),(disp),(reg));
2110 /* Always emit a REX byte, because the instruction size can be smaller when */
2111 /* all register indexes are smaller than 7. */
2112 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2113 *(cd->mcodeptr++) = 0xf2;
2114 emit_byte_rex((reg),0,(basereg));
2115 *(cd->mcodeptr++) = 0x0f;
2116 *(cd->mcodeptr++) = 0x11;
2117 emit_membase32(cd, (basereg),(disp),(reg));
2121 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2122 *(cd->mcodeptr++) = 0xf3;
2123 emit_rex(0,(dreg),0,(basereg));
2124 *(cd->mcodeptr++) = 0x0f;
2125 *(cd->mcodeptr++) = 0x10;
2126 emit_membase(cd, (basereg),(disp),(dreg));
2130 /* Always emit a REX byte, because the instruction size can be smaller when */
2131 /* all register indexes are smaller than 7. */
2132 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2133 *(cd->mcodeptr++) = 0xf3;
2134 emit_byte_rex((dreg),0,(basereg));
2135 *(cd->mcodeptr++) = 0x0f;
2136 *(cd->mcodeptr++) = 0x10;
2137 emit_membase32(cd, (basereg),(disp),(dreg));
2141 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2143 emit_rex(0,(dreg),0,(basereg));
2144 *(cd->mcodeptr++) = 0x0f;
2145 *(cd->mcodeptr++) = 0x12;
2146 emit_membase(cd, (basereg),(disp),(dreg));
2150 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2152 emit_rex(0,(reg),0,(basereg));
2153 *(cd->mcodeptr++) = 0x0f;
2154 *(cd->mcodeptr++) = 0x13;
2155 emit_membase(cd, (basereg),(disp),(reg));
2159 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2160 *(cd->mcodeptr++) = 0xf2;
2161 emit_rex(0,(dreg),0,(basereg));
2162 *(cd->mcodeptr++) = 0x0f;
2163 *(cd->mcodeptr++) = 0x10;
2164 emit_membase(cd, (basereg),(disp),(dreg));
2168 /* Always emit a REX byte, because the instruction size can be smaller when */
2169 /* all register indexes are smaller than 7. */
2170 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2171 *(cd->mcodeptr++) = 0xf2;
2172 emit_byte_rex((dreg),0,(basereg));
2173 *(cd->mcodeptr++) = 0x0f;
2174 *(cd->mcodeptr++) = 0x10;
2175 emit_membase32(cd, (basereg),(disp),(dreg));
2179 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2181 *(cd->mcodeptr++) = 0x66;
2182 emit_rex(0,(dreg),0,(basereg));
2183 *(cd->mcodeptr++) = 0x0f;
2184 *(cd->mcodeptr++) = 0x12;
2185 emit_membase(cd, (basereg),(disp),(dreg));
2189 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2191 *(cd->mcodeptr++) = 0x66;
2192 emit_rex(0,(reg),0,(basereg));
2193 *(cd->mcodeptr++) = 0x0f;
2194 *(cd->mcodeptr++) = 0x13;
2195 emit_membase(cd, (basereg),(disp),(reg));
2199 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2200 *(cd->mcodeptr++) = 0xf3;
2201 emit_rex(0,(reg),(indexreg),(basereg));
2202 *(cd->mcodeptr++) = 0x0f;
2203 *(cd->mcodeptr++) = 0x11;
2204 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2208 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2209 *(cd->mcodeptr++) = 0xf2;
2210 emit_rex(0,(reg),(indexreg),(basereg));
2211 *(cd->mcodeptr++) = 0x0f;
2212 *(cd->mcodeptr++) = 0x11;
2213 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2217 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2218 *(cd->mcodeptr++) = 0xf3;
2219 emit_rex(0,(dreg),(indexreg),(basereg));
2220 *(cd->mcodeptr++) = 0x0f;
2221 *(cd->mcodeptr++) = 0x10;
2222 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2226 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2227 *(cd->mcodeptr++) = 0xf2;
2228 emit_rex(0,(dreg),(indexreg),(basereg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x10;
2231 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2235 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2236 *(cd->mcodeptr++) = 0xf3;
2237 emit_rex(0,(dreg),0,(reg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x59;
2240 emit_reg((dreg),(reg));
2244 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2245 *(cd->mcodeptr++) = 0xf2;
2246 emit_rex(0,(dreg),0,(reg));
2247 *(cd->mcodeptr++) = 0x0f;
2248 *(cd->mcodeptr++) = 0x59;
2249 emit_reg((dreg),(reg));
2253 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2254 *(cd->mcodeptr++) = 0xf3;
2255 emit_rex(0,(dreg),0,(reg));
2256 *(cd->mcodeptr++) = 0x0f;
2257 *(cd->mcodeptr++) = 0x5c;
2258 emit_reg((dreg),(reg));
2262 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2263 *(cd->mcodeptr++) = 0xf2;
2264 emit_rex(0,(dreg),0,(reg));
2265 *(cd->mcodeptr++) = 0x0f;
2266 *(cd->mcodeptr++) = 0x5c;
2267 emit_reg((dreg),(reg));
2271 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2272 emit_rex(0,(dreg),0,(reg));
2273 *(cd->mcodeptr++) = 0x0f;
2274 *(cd->mcodeptr++) = 0x2e;
2275 emit_reg((dreg),(reg));
2279 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2280 *(cd->mcodeptr++) = 0x66;
2281 emit_rex(0,(dreg),0,(reg));
2282 *(cd->mcodeptr++) = 0x0f;
2283 *(cd->mcodeptr++) = 0x2e;
2284 emit_reg((dreg),(reg));
2288 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2289 emit_rex(0,(dreg),0,(reg));
2290 *(cd->mcodeptr++) = 0x0f;
2291 *(cd->mcodeptr++) = 0x57;
2292 emit_reg((dreg),(reg));
2296 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2297 emit_rex(0,(dreg),0,(basereg));
2298 *(cd->mcodeptr++) = 0x0f;
2299 *(cd->mcodeptr++) = 0x57;
2300 emit_membase(cd, (basereg),(disp),(dreg));
2304 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2305 *(cd->mcodeptr++) = 0x66;
2306 emit_rex(0,(dreg),0,(reg));
2307 *(cd->mcodeptr++) = 0x0f;
2308 *(cd->mcodeptr++) = 0x57;
2309 emit_reg((dreg),(reg));
2313 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2314 *(cd->mcodeptr++) = 0x66;
2315 emit_rex(0,(dreg),0,(basereg));
2316 *(cd->mcodeptr++) = 0x0f;
2317 *(cd->mcodeptr++) = 0x57;
2318 emit_membase(cd, (basereg),(disp),(dreg));
2322 /* system instructions ********************************************************/
2324 void emit_rdtsc(codegendata *cd)
2326 *(cd->mcodeptr++) = 0x0f;
2327 *(cd->mcodeptr++) = 0x31;
2332 * These are local overrides for various environment variables in Emacs.
2333 * Please do not remove this and leave it at the end of the file, where
2334 * Emacs will automagically detect them.
2335 * ---------------------------------------------------------------------
2338 * indent-tabs-mode: t