1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7766 2007-04-19 13:24:48Z michi $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
47 #include "vm/exceptions.h"
49 #include "vm/jit/abi.h"
50 #include "vm/jit/abi-asm.h"
51 #include "vm/jit/asmpart.h"
52 #include "vm/jit/codegen-common.h"
53 #include "vm/jit/emit-common.h"
54 #include "vm/jit/jit.h"
55 #include "vm/jit/replace.h"
57 #include "vmcore/options.h"
60 /* emit_load *******************************************************************
62 Emits a possible load of an operand.
64 *******************************************************************************/
66 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
72 /* get required compiler data */
76 if (IS_INMEMORY(src->flags)) {
79 disp = src->vv.regoff * 8;
83 M_ILD(tempreg, REG_SP, disp);
87 M_LLD(tempreg, REG_SP, disp);
90 M_FLD(tempreg, REG_SP, disp);
93 M_DLD(tempreg, REG_SP, disp);
96 vm_abort("emit_load: unknown type %d", src->type);
102 reg = src->vv.regoff;
108 /* emit_store ******************************************************************
110 This function generates the code to store the result of an
111 operation back into a spilled pseudo-variable. If the
112 pseudo-variable has not been spilled in the first place, this
113 function will generate nothing.
115 *******************************************************************************/
117 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
126 /* get required compiler data */
131 /* do we have to generate a conditional move? */
133 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
134 /* the passed register d is actually the source register */
138 /* Only pass the opcode to codegen_reg_of_var to get the real
139 destination register. */
141 opcode = iptr->opc & ICMD_OPCODE_MASK;
143 /* get the real destination register */
145 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
147 /* and emit the conditional move */
149 emit_cmovxx(cd, iptr, s, d);
153 if (IS_INMEMORY(dst->flags)) {
156 disp = dst->vv.regoff * 8;
162 M_LST(d, REG_SP, disp);
165 M_FST(d, REG_SP, disp);
168 M_DST(d, REG_SP, disp);
171 vm_abort("emit_store: unknown type %d", dst->type);
177 /* emit_copy *******************************************************************
179 Generates a register/memory to register/memory copy.
181 *******************************************************************************/
183 void emit_copy(jitdata *jd, instruction *iptr)
190 /* get required compiler data */
194 /* get source and destination variables */
196 src = VAROP(iptr->s1);
197 dst = VAROP(iptr->dst);
199 if ((src->vv.regoff != dst->vv.regoff) ||
200 ((src->flags ^ dst->flags) & INMEMORY)) {
202 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
203 /* emit nothing, as the value won't be used anyway */
207 /* If one of the variables resides in memory, we can eliminate
208 the register move from/to the temporary register with the
209 order of getting the destination register and the load. */
211 if (IS_INMEMORY(src->flags)) {
212 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
213 s1 = emit_load(jd, iptr, src, d);
216 s1 = emit_load(jd, iptr, src, REG_IFTMP);
217 d = codegen_reg_of_var(iptr->opc, dst, s1);
232 vm_abort("emit_copy: unknown type %d", src->type);
236 emit_store(jd, iptr, dst, d);
241 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
244 switch (iptr->flags.fields.condition) {
268 /* emit_branch *****************************************************************
270 Emits the code for conditional and unconditional branchs.
272 *******************************************************************************/
274 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
278 /* NOTE: A displacement overflow cannot happen. */
280 /* check which branch to generate */
282 if (condition == BRANCH_UNCONDITIONAL) {
284 /* calculate the different displacements */
286 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
288 M_JMP_IMM(branchdisp);
291 /* calculate the different displacements */
293 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
327 vm_abort("emit_branch: unknown condition %d", condition);
333 /* emit_arithmetic_check *******************************************************
335 Emit an ArithmeticException check.
337 *******************************************************************************/
339 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
341 if (INSTRUCTION_MUST_CHECK(iptr)) {
344 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
349 /* emit_arrayindexoutofbounds_check ********************************************
351 Emit a ArrayIndexOutOfBoundsException check.
353 *******************************************************************************/
355 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
357 if (INSTRUCTION_MUST_CHECK(iptr)) {
358 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
359 M_ICMP(REG_ITMP3, s2);
361 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
366 /* emit_classcast_check ********************************************************
368 Emit a ClassCastException check.
370 *******************************************************************************/
372 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
374 if (INSTRUCTION_MUST_CHECK(iptr)) {
386 vm_abort("emit_classcast_check: unknown condition %d", condition);
388 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
393 /* emit_nullpointer_check ******************************************************
395 Emit a NullPointerException check.
397 *******************************************************************************/
399 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
401 if (INSTRUCTION_MUST_CHECK(iptr)) {
404 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
409 /* emit_exception_check ********************************************************
411 Emit an Exception check.
413 *******************************************************************************/
415 void emit_exception_check(codegendata *cd, instruction *iptr)
417 if (INSTRUCTION_MUST_CHECK(iptr)) {
420 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
425 /* emit_patcher_stubs **********************************************************
427 Generates the code for the patcher stubs.
429 *******************************************************************************/
431 void emit_patcher_stubs(jitdata *jd)
441 /* get required compiler data */
445 /* generate code patching stub call code */
449 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
450 /* check size of code segment */
454 /* Get machine code which is patched back in later. A
455 `call rel32' is 5 bytes long (but read 8 bytes). */
457 savedmcodeptr = cd->mcodebase + pref->branchpos;
458 mcode = *((u8 *) savedmcodeptr);
460 /* patch in `call rel32' to call the following code */
462 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
463 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
465 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
467 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
469 /* move pointer to java_objectheader onto stack */
471 #if defined(ENABLE_THREADS)
472 /* create a virtual java_objectheader */
474 (void) dseg_add_unique_address(cd, NULL); /* flcword */
475 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
476 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
478 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
484 /* move machine code bytes and classinfo pointer into registers */
486 M_MOV_IMM(mcode, REG_ITMP3);
489 M_MOV_IMM(pref->ref, REG_ITMP3);
492 M_MOV_IMM(pref->disp, REG_ITMP3);
495 M_MOV_IMM(pref->patcher, REG_ITMP3);
498 if (targetdisp == 0) {
499 targetdisp = cd->mcodeptr - cd->mcodebase;
501 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
505 M_JMP_IMM((cd->mcodebase + targetdisp) -
506 (cd->mcodeptr + PATCHER_CALL_SIZE));
512 /* emit_replacement_stubs ******************************************************
514 Generates the code for the replacement stubs.
516 *******************************************************************************/
518 #if defined(ENABLE_REPLACEMENT)
519 void emit_replacement_stubs(jitdata *jd)
529 /* get required compiler data */
534 rplp = code->rplpoints;
536 /* store beginning of replacement stubs */
538 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
540 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
541 /* do not generate stubs for non-trappable points */
543 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
546 /* check code segment size */
550 /* note start of stub code */
553 savedmcodeptr = cd->mcodeptr;
556 /* push address of `rplpoint` struct */
558 M_MOV_IMM(rplp, REG_ITMP3);
561 /* jump to replacement function */
563 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
567 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
570 #endif /* defined(ENABLE_REPLACEMENT) */
573 /* emit_verbosecall_enter ******************************************************
575 Generates the code for the call trace.
577 *******************************************************************************/
580 void emit_verbosecall_enter(jitdata *jd)
588 /* get required compiler data */
596 /* mark trace code */
600 /* additional +1 is for 16-byte stack alignment */
602 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
604 /* save argument registers */
606 for (i = 0; i < INT_ARG_CNT; i++)
607 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
609 for (i = 0; i < FLT_ARG_CNT; i++)
610 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
612 /* save temporary registers for leaf methods */
614 if (jd->isleafmethod) {
615 for (i = 0; i < INT_TMP_CNT; i++)
616 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
618 for (i = 0; i < FLT_TMP_CNT; i++)
619 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
622 /* show integer hex code for float arguments */
624 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
625 /* If the paramtype is a float, we have to right shift all
626 following integer registers. */
628 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
629 for (k = INT_ARG_CNT - 2; k >= i; k--)
630 M_MOV(abi_registers_integer_argument[k],
631 abi_registers_integer_argument[k + 1]);
633 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
634 abi_registers_integer_argument[i]);
639 M_MOV_IMM(m, REG_ITMP2);
640 M_AST(REG_ITMP2, REG_SP, 0 * 8);
641 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
644 /* restore argument registers */
646 for (i = 0; i < INT_ARG_CNT; i++)
647 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
649 for (i = 0; i < FLT_ARG_CNT; i++)
650 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
652 /* restore temporary registers for leaf methods */
654 if (jd->isleafmethod) {
655 for (i = 0; i < INT_TMP_CNT; i++)
656 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
658 for (i = 0; i < FLT_TMP_CNT; i++)
659 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
662 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
664 /* mark trace code */
668 #endif /* !defined(NDEBUG) */
671 /* emit_verbosecall_exit *******************************************************
673 Generates the code for the call trace.
675 *******************************************************************************/
678 void emit_verbosecall_exit(jitdata *jd)
684 /* get required compiler data */
690 /* mark trace code */
694 M_ASUB_IMM(2 * 8, REG_SP);
696 M_LST(REG_RESULT, REG_SP, 0 * 8);
697 M_DST(REG_FRESULT, REG_SP, 1 * 8);
699 M_INTMOVE(REG_RESULT, REG_A0);
700 M_FLTMOVE(REG_FRESULT, REG_FA0);
701 M_FLTMOVE(REG_FRESULT, REG_FA1);
702 M_MOV_IMM(m, REG_A1);
704 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
707 M_LLD(REG_RESULT, REG_SP, 0 * 8);
708 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
710 M_AADD_IMM(2 * 8, REG_SP);
712 /* mark trace code */
716 #endif /* !defined(NDEBUG) */
719 /* code generation functions **************************************************/
721 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
723 if ((basereg == REG_SP) || (basereg == R12)) {
725 emit_address_byte(0, dreg, REG_SP);
726 emit_address_byte(0, REG_SP, REG_SP);
728 } else if (IS_IMM8(disp)) {
729 emit_address_byte(1, dreg, REG_SP);
730 emit_address_byte(0, REG_SP, REG_SP);
734 emit_address_byte(2, dreg, REG_SP);
735 emit_address_byte(0, REG_SP, REG_SP);
739 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
740 emit_address_byte(0,(dreg),(basereg));
742 } else if ((basereg) == RIP) {
743 emit_address_byte(0, dreg, RBP);
748 emit_address_byte(1, dreg, basereg);
752 emit_address_byte(2, dreg, basereg);
759 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
761 if ((basereg == REG_SP) || (basereg == R12)) {
762 emit_address_byte(2, dreg, REG_SP);
763 emit_address_byte(0, REG_SP, REG_SP);
767 emit_address_byte(2, dreg, basereg);
773 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
776 emit_address_byte(0, reg, 4);
777 emit_address_byte(scale, indexreg, 5);
780 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
781 emit_address_byte(0, reg, 4);
782 emit_address_byte(scale, indexreg, basereg);
784 else if (IS_IMM8(disp)) {
785 emit_address_byte(1, reg, 4);
786 emit_address_byte(scale, indexreg, basereg);
790 emit_address_byte(2, reg, 4);
791 emit_address_byte(scale, indexreg, basereg);
797 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
800 varinfo *v_s1,*v_s2,*v_dst;
803 /* get required compiler data */
807 v_s1 = VAROP(iptr->s1);
808 v_s2 = VAROP(iptr->sx.s23.s2);
809 v_dst = VAROP(iptr->dst);
811 s1 = v_s1->vv.regoff;
812 s2 = v_s2->vv.regoff;
813 d = v_dst->vv.regoff;
815 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
817 if (IS_INMEMORY(v_dst->flags)) {
818 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
820 M_ILD(RCX, REG_SP, s2 * 8);
821 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
824 M_ILD(RCX, REG_SP, s2 * 8);
825 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
826 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
827 M_IST(REG_ITMP2, REG_SP, d * 8);
830 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
831 /* s1 may be equal to RCX */
834 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
835 M_IST(s1, REG_SP, d * 8);
836 M_INTMOVE(REG_ITMP1, RCX);
839 M_IST(s1, REG_SP, d * 8);
840 M_ILD(RCX, REG_SP, s2 * 8);
844 M_ILD(RCX, REG_SP, s2 * 8);
845 M_IST(s1, REG_SP, d * 8);
848 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
850 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
853 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
857 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
858 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
859 M_IST(REG_ITMP2, REG_SP, d * 8);
863 /* s1 may be equal to RCX */
864 M_IST(s1, REG_SP, d * 8);
866 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
869 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
877 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
878 M_ILD(RCX, REG_SP, s2 * 8);
879 M_ILD(d, REG_SP, s1 * 8);
880 emit_shiftl_reg(cd, shift_op, d);
882 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
883 /* s1 may be equal to RCX */
885 M_ILD(RCX, REG_SP, s2 * 8);
886 emit_shiftl_reg(cd, shift_op, d);
888 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
890 M_ILD(d, REG_SP, s1 * 8);
891 emit_shiftl_reg(cd, shift_op, d);
894 /* s1 may be equal to RCX */
897 /* d cannot be used to backup s1 since this would
899 M_INTMOVE(s1, REG_ITMP3);
901 M_INTMOVE(REG_ITMP3, d);
909 /* d may be equal to s2 */
913 emit_shiftl_reg(cd, shift_op, d);
917 M_INTMOVE(REG_ITMP3, RCX);
919 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
924 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
927 varinfo *v_s1,*v_s2,*v_dst;
930 /* get required compiler data */
934 v_s1 = VAROP(iptr->s1);
935 v_s2 = VAROP(iptr->sx.s23.s2);
936 v_dst = VAROP(iptr->dst);
938 s1 = v_s1->vv.regoff;
939 s2 = v_s2->vv.regoff;
940 d = v_dst->vv.regoff;
942 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
944 if (IS_INMEMORY(v_dst->flags)) {
945 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
947 M_ILD(RCX, REG_SP, s2 * 8);
948 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
951 M_ILD(RCX, REG_SP, s2 * 8);
952 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
953 emit_shift_reg(cd, shift_op, REG_ITMP2);
954 M_LST(REG_ITMP2, REG_SP, d * 8);
957 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
958 /* s1 may be equal to RCX */
961 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
962 M_LST(s1, REG_SP, d * 8);
963 M_INTMOVE(REG_ITMP1, RCX);
966 M_LST(s1, REG_SP, d * 8);
967 M_ILD(RCX, REG_SP, s2 * 8);
971 M_ILD(RCX, REG_SP, s2 * 8);
972 M_LST(s1, REG_SP, d * 8);
975 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
977 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
980 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
984 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
985 emit_shift_reg(cd, shift_op, REG_ITMP2);
986 M_LST(REG_ITMP2, REG_SP, d * 8);
990 /* s1 may be equal to RCX */
991 M_LST(s1, REG_SP, d * 8);
993 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
996 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1004 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1005 M_ILD(RCX, REG_SP, s2 * 8);
1006 M_LLD(d, REG_SP, s1 * 8);
1007 emit_shift_reg(cd, shift_op, d);
1009 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1010 /* s1 may be equal to RCX */
1012 M_ILD(RCX, REG_SP, s2 * 8);
1013 emit_shift_reg(cd, shift_op, d);
1015 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1017 M_LLD(d, REG_SP, s1 * 8);
1018 emit_shift_reg(cd, shift_op, d);
1021 /* s1 may be equal to RCX */
1024 /* d cannot be used to backup s1 since this would
1026 M_INTMOVE(s1, REG_ITMP3);
1028 M_INTMOVE(REG_ITMP3, d);
1036 /* d may be equal to s2 */
1040 emit_shift_reg(cd, shift_op, d);
1044 M_INTMOVE(REG_ITMP3, RCX);
1046 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1051 /* low-level code emitter functions *******************************************/
1053 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1055 emit_rex(1,(reg),0,(dreg));
1056 *(cd->mcodeptr++) = 0x89;
1057 emit_reg((reg),(dreg));
1061 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1063 emit_rex(1,0,0,(reg));
1064 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1069 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1071 emit_rex(0,(reg),0,(dreg));
1072 *(cd->mcodeptr++) = 0x89;
1073 emit_reg((reg),(dreg));
1077 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1078 emit_rex(0,0,0,(reg));
1079 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1084 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1085 emit_rex(1,(reg),0,(basereg));
1086 *(cd->mcodeptr++) = 0x8b;
1087 emit_membase(cd, (basereg),(disp),(reg));
1092 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1093 * constant membase immediate length of 32bit
1095 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1096 emit_rex(1,(reg),0,(basereg));
1097 *(cd->mcodeptr++) = 0x8b;
1098 emit_membase32(cd, (basereg),(disp),(reg));
1102 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1104 emit_rex(0,(reg),0,(basereg));
1105 *(cd->mcodeptr++) = 0x8b;
1106 emit_membase(cd, (basereg),(disp),(reg));
1110 /* ATTENTION: Always emit a REX byte, because the instruction size can
1111 be smaller when all register indexes are smaller than 7. */
1112 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1114 emit_byte_rex((reg),0,(basereg));
1115 *(cd->mcodeptr++) = 0x8b;
1116 emit_membase32(cd, (basereg),(disp),(reg));
1120 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1121 emit_rex(1,(reg),0,(basereg));
1122 *(cd->mcodeptr++) = 0x89;
1123 emit_membase(cd, (basereg),(disp),(reg));
1127 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1128 emit_rex(1,(reg),0,(basereg));
1129 *(cd->mcodeptr++) = 0x89;
1130 emit_membase32(cd, (basereg),(disp),(reg));
1134 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1135 emit_rex(0,(reg),0,(basereg));
1136 *(cd->mcodeptr++) = 0x89;
1137 emit_membase(cd, (basereg),(disp),(reg));
1141 /* Always emit a REX byte, because the instruction size can be smaller when */
1142 /* all register indexes are smaller than 7. */
1143 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1144 emit_byte_rex((reg),0,(basereg));
1145 *(cd->mcodeptr++) = 0x89;
1146 emit_membase32(cd, (basereg),(disp),(reg));
1150 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1151 emit_rex(1,(reg),(indexreg),(basereg));
1152 *(cd->mcodeptr++) = 0x8b;
1153 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1157 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1158 emit_rex(0,(reg),(indexreg),(basereg));
1159 *(cd->mcodeptr++) = 0x8b;
1160 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1164 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1165 emit_rex(1,(reg),(indexreg),(basereg));
1166 *(cd->mcodeptr++) = 0x89;
1167 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1171 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1172 emit_rex(0,(reg),(indexreg),(basereg));
1173 *(cd->mcodeptr++) = 0x89;
1174 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1178 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1179 *(cd->mcodeptr++) = 0x66;
1180 emit_rex(0,(reg),(indexreg),(basereg));
1181 *(cd->mcodeptr++) = 0x89;
1182 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1186 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1187 emit_byte_rex((reg),(indexreg),(basereg));
1188 *(cd->mcodeptr++) = 0x88;
1189 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1193 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1194 emit_rex(1,0,0,(basereg));
1195 *(cd->mcodeptr++) = 0xc7;
1196 emit_membase(cd, (basereg),(disp),0);
1201 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1202 emit_rex(1,0,0,(basereg));
1203 *(cd->mcodeptr++) = 0xc7;
1204 emit_membase32(cd, (basereg),(disp),0);
1209 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1210 emit_rex(0,0,0,(basereg));
1211 *(cd->mcodeptr++) = 0xc7;
1212 emit_membase(cd, (basereg),(disp),0);
1217 /* Always emit a REX byte, because the instruction size can be smaller when */
1218 /* all register indexes are smaller than 7. */
1219 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1220 emit_byte_rex(0,0,(basereg));
1221 *(cd->mcodeptr++) = 0xc7;
1222 emit_membase32(cd, (basereg),(disp),0);
1227 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1229 emit_rex(1,(dreg),0,(reg));
1230 *(cd->mcodeptr++) = 0x0f;
1231 *(cd->mcodeptr++) = 0xbe;
1232 /* XXX: why do reg and dreg have to be exchanged */
1233 emit_reg((dreg),(reg));
1237 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1239 emit_rex(1,(dreg),0,(reg));
1240 *(cd->mcodeptr++) = 0x0f;
1241 *(cd->mcodeptr++) = 0xbf;
1242 /* XXX: why do reg and dreg have to be exchanged */
1243 emit_reg((dreg),(reg));
1247 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1249 emit_rex(1,(dreg),0,(reg));
1250 *(cd->mcodeptr++) = 0x63;
1251 /* XXX: why do reg and dreg have to be exchanged */
1252 emit_reg((dreg),(reg));
1256 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1258 emit_rex(1,(dreg),0,(reg));
1259 *(cd->mcodeptr++) = 0x0f;
1260 *(cd->mcodeptr++) = 0xb7;
1261 /* XXX: why do reg and dreg have to be exchanged */
1262 emit_reg((dreg),(reg));
1266 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1267 emit_rex(1,(reg),(indexreg),(basereg));
1268 *(cd->mcodeptr++) = 0x0f;
1269 *(cd->mcodeptr++) = 0xbf;
1270 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1274 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1275 emit_rex(1,(reg),(indexreg),(basereg));
1276 *(cd->mcodeptr++) = 0x0f;
1277 *(cd->mcodeptr++) = 0xbe;
1278 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1282 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1283 emit_rex(1,(reg),(indexreg),(basereg));
1284 *(cd->mcodeptr++) = 0x0f;
1285 *(cd->mcodeptr++) = 0xb7;
1286 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1290 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1292 emit_rex(1,0,(indexreg),(basereg));
1293 *(cd->mcodeptr++) = 0xc7;
1294 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1299 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1301 emit_rex(0,0,(indexreg),(basereg));
1302 *(cd->mcodeptr++) = 0xc7;
1303 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1308 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1310 *(cd->mcodeptr++) = 0x66;
1311 emit_rex(0,0,(indexreg),(basereg));
1312 *(cd->mcodeptr++) = 0xc7;
1313 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1318 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1320 emit_rex(0,0,(indexreg),(basereg));
1321 *(cd->mcodeptr++) = 0xc6;
1322 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1327 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1329 emit_rex(1, dreg, 0, 0);
1330 *(cd->mcodeptr++) = 0x8b;
1331 emit_address_byte(0, dreg, 4);
1339 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1341 emit_rex(1,(reg),0,(dreg));
1342 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1343 emit_reg((reg),(dreg));
1347 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1349 emit_rex(0,(reg),0,(dreg));
1350 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1351 emit_reg((reg),(dreg));
1355 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1357 emit_rex(1,(reg),0,(basereg));
1358 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1359 emit_membase(cd, (basereg),(disp),(reg));
1363 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1365 emit_rex(0,(reg),0,(basereg));
1366 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1367 emit_membase(cd, (basereg),(disp),(reg));
1371 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1373 emit_rex(1,(reg),0,(basereg));
1374 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1375 emit_membase(cd, (basereg),(disp),(reg));
1379 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1381 emit_rex(0,(reg),0,(basereg));
1382 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1383 emit_membase(cd, (basereg),(disp),(reg));
1387 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1389 emit_rex(1,0,0,(dreg));
1390 *(cd->mcodeptr++) = 0x83;
1391 emit_reg((opc),(dreg));
1394 emit_rex(1,0,0,(dreg));
1395 *(cd->mcodeptr++) = 0x81;
1396 emit_reg((opc),(dreg));
1402 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1404 emit_rex(1,0,0,(dreg));
1405 *(cd->mcodeptr++) = 0x81;
1406 emit_reg((opc),(dreg));
1411 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1413 emit_rex(0,0,0,(dreg));
1414 *(cd->mcodeptr++) = 0x81;
1415 emit_reg((opc),(dreg));
1420 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1422 emit_rex(0,0,0,(dreg));
1423 *(cd->mcodeptr++) = 0x83;
1424 emit_reg((opc),(dreg));
1427 emit_rex(0,0,0,(dreg));
1428 *(cd->mcodeptr++) = 0x81;
1429 emit_reg((opc),(dreg));
1435 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1437 emit_rex(1,(basereg),0,0);
1438 *(cd->mcodeptr++) = 0x83;
1439 emit_membase(cd, (basereg),(disp),(opc));
1442 emit_rex(1,(basereg),0,0);
1443 *(cd->mcodeptr++) = 0x81;
1444 emit_membase(cd, (basereg),(disp),(opc));
1450 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1452 emit_rex(0,(basereg),0,0);
1453 *(cd->mcodeptr++) = 0x83;
1454 emit_membase(cd, (basereg),(disp),(opc));
1457 emit_rex(0,(basereg),0,0);
1458 *(cd->mcodeptr++) = 0x81;
1459 emit_membase(cd, (basereg),(disp),(opc));
1465 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1466 emit_rex(1,(reg),0,(dreg));
1467 *(cd->mcodeptr++) = 0x85;
1468 emit_reg((reg),(dreg));
1472 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1473 emit_rex(0,(reg),0,(dreg));
1474 *(cd->mcodeptr++) = 0x85;
1475 emit_reg((reg),(dreg));
1479 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1480 *(cd->mcodeptr++) = 0xf7;
1486 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1487 *(cd->mcodeptr++) = 0x66;
1488 *(cd->mcodeptr++) = 0xf7;
1494 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1495 *(cd->mcodeptr++) = 0xf6;
1501 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1502 emit_rex(1,(reg),0,(basereg));
1503 *(cd->mcodeptr++) = 0x8d;
1504 emit_membase(cd, (basereg),(disp),(reg));
1508 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1509 emit_rex(0,(reg),0,(basereg));
1510 *(cd->mcodeptr++) = 0x8d;
1511 emit_membase(cd, (basereg),(disp),(reg));
1516 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1518 emit_rex(0,0,0,(basereg));
1519 *(cd->mcodeptr++) = 0xff;
1520 emit_membase(cd, (basereg),(disp),0);
1525 void emit_cltd(codegendata *cd) {
1526 *(cd->mcodeptr++) = 0x99;
1530 void emit_cqto(codegendata *cd) {
1532 *(cd->mcodeptr++) = 0x99;
1537 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1538 emit_rex(1,(dreg),0,(reg));
1539 *(cd->mcodeptr++) = 0x0f;
1540 *(cd->mcodeptr++) = 0xaf;
1541 emit_reg((dreg),(reg));
1545 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1546 emit_rex(0,(dreg),0,(reg));
1547 *(cd->mcodeptr++) = 0x0f;
1548 *(cd->mcodeptr++) = 0xaf;
1549 emit_reg((dreg),(reg));
1553 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1554 emit_rex(1,(dreg),0,(basereg));
1555 *(cd->mcodeptr++) = 0x0f;
1556 *(cd->mcodeptr++) = 0xaf;
1557 emit_membase(cd, (basereg),(disp),(dreg));
1561 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1562 emit_rex(0,(dreg),0,(basereg));
1563 *(cd->mcodeptr++) = 0x0f;
1564 *(cd->mcodeptr++) = 0xaf;
1565 emit_membase(cd, (basereg),(disp),(dreg));
1569 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1570 if (IS_IMM8((imm))) {
1571 emit_rex(1,0,0,(dreg));
1572 *(cd->mcodeptr++) = 0x6b;
1576 emit_rex(1,0,0,(dreg));
1577 *(cd->mcodeptr++) = 0x69;
1584 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1585 if (IS_IMM8((imm))) {
1586 emit_rex(1,(dreg),0,(reg));
1587 *(cd->mcodeptr++) = 0x6b;
1588 emit_reg((dreg),(reg));
1591 emit_rex(1,(dreg),0,(reg));
1592 *(cd->mcodeptr++) = 0x69;
1593 emit_reg((dreg),(reg));
1599 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1600 if (IS_IMM8((imm))) {
1601 emit_rex(0,(dreg),0,(reg));
1602 *(cd->mcodeptr++) = 0x6b;
1603 emit_reg((dreg),(reg));
1606 emit_rex(0,(dreg),0,(reg));
1607 *(cd->mcodeptr++) = 0x69;
1608 emit_reg((dreg),(reg));
1614 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1615 if (IS_IMM8((imm))) {
1616 emit_rex(1,(dreg),0,(basereg));
1617 *(cd->mcodeptr++) = 0x6b;
1618 emit_membase(cd, (basereg),(disp),(dreg));
1621 emit_rex(1,(dreg),0,(basereg));
1622 *(cd->mcodeptr++) = 0x69;
1623 emit_membase(cd, (basereg),(disp),(dreg));
1629 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1630 if (IS_IMM8((imm))) {
1631 emit_rex(0,(dreg),0,(basereg));
1632 *(cd->mcodeptr++) = 0x6b;
1633 emit_membase(cd, (basereg),(disp),(dreg));
1636 emit_rex(0,(dreg),0,(basereg));
1637 *(cd->mcodeptr++) = 0x69;
1638 emit_membase(cd, (basereg),(disp),(dreg));
1644 void emit_idiv_reg(codegendata *cd, s8 reg) {
1645 emit_rex(1,0,0,(reg));
1646 *(cd->mcodeptr++) = 0xf7;
1651 void emit_idivl_reg(codegendata *cd, s8 reg) {
1652 emit_rex(0,0,0,(reg));
1653 *(cd->mcodeptr++) = 0xf7;
1659 void emit_ret(codegendata *cd) {
1660 *(cd->mcodeptr++) = 0xc3;
1668 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1669 emit_rex(1,0,0,(reg));
1670 *(cd->mcodeptr++) = 0xd3;
1671 emit_reg((opc),(reg));
1675 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1676 emit_rex(0,0,0,(reg));
1677 *(cd->mcodeptr++) = 0xd3;
1678 emit_reg((opc),(reg));
1682 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1683 emit_rex(1,0,0,(basereg));
1684 *(cd->mcodeptr++) = 0xd3;
1685 emit_membase(cd, (basereg),(disp),(opc));
1689 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1690 emit_rex(0,0,0,(basereg));
1691 *(cd->mcodeptr++) = 0xd3;
1692 emit_membase(cd, (basereg),(disp),(opc));
1696 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1698 emit_rex(1,0,0,(dreg));
1699 *(cd->mcodeptr++) = 0xd1;
1700 emit_reg((opc),(dreg));
1702 emit_rex(1,0,0,(dreg));
1703 *(cd->mcodeptr++) = 0xc1;
1704 emit_reg((opc),(dreg));
1710 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1712 emit_rex(0,0,0,(dreg));
1713 *(cd->mcodeptr++) = 0xd1;
1714 emit_reg((opc),(dreg));
1716 emit_rex(0,0,0,(dreg));
1717 *(cd->mcodeptr++) = 0xc1;
1718 emit_reg((opc),(dreg));
1724 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1726 emit_rex(1,0,0,(basereg));
1727 *(cd->mcodeptr++) = 0xd1;
1728 emit_membase(cd, (basereg),(disp),(opc));
1730 emit_rex(1,0,0,(basereg));
1731 *(cd->mcodeptr++) = 0xc1;
1732 emit_membase(cd, (basereg),(disp),(opc));
1738 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1740 emit_rex(0,0,0,(basereg));
1741 *(cd->mcodeptr++) = 0xd1;
1742 emit_membase(cd, (basereg),(disp),(opc));
1744 emit_rex(0,0,0,(basereg));
1745 *(cd->mcodeptr++) = 0xc1;
1746 emit_membase(cd, (basereg),(disp),(opc));
1756 void emit_jmp_imm(codegendata *cd, s8 imm) {
1757 *(cd->mcodeptr++) = 0xe9;
1762 void emit_jmp_reg(codegendata *cd, s8 reg) {
1763 emit_rex(0,0,0,(reg));
1764 *(cd->mcodeptr++) = 0xff;
1769 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1770 *(cd->mcodeptr++) = 0x0f;
1771 *(cd->mcodeptr++) = (0x80 + (opc));
1778 * conditional set and move operations
1781 /* we need the rex byte to get all low bytes */
1782 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1784 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1785 *(cd->mcodeptr++) = 0x0f;
1786 *(cd->mcodeptr++) = (0x90 + (opc));
1791 /* we need the rex byte to get all low bytes */
1792 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1794 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1795 *(cd->mcodeptr++) = 0x0f;
1796 *(cd->mcodeptr++) = (0x90 + (opc));
1797 emit_membase(cd, (basereg),(disp),0);
1801 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1803 emit_rex(1,(dreg),0,(reg));
1804 *(cd->mcodeptr++) = 0x0f;
1805 *(cd->mcodeptr++) = (0x40 + (opc));
1806 emit_reg((dreg),(reg));
1810 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1812 emit_rex(0,(dreg),0,(reg));
1813 *(cd->mcodeptr++) = 0x0f;
1814 *(cd->mcodeptr++) = (0x40 + (opc));
1815 emit_reg((dreg),(reg));
1819 void emit_neg_reg(codegendata *cd, s8 reg)
1821 emit_rex(1,0,0,(reg));
1822 *(cd->mcodeptr++) = 0xf7;
1827 void emit_negl_reg(codegendata *cd, s8 reg)
1829 emit_rex(0,0,0,(reg));
1830 *(cd->mcodeptr++) = 0xf7;
1835 void emit_push_reg(codegendata *cd, s8 reg) {
1836 emit_rex(0,0,0,(reg));
1837 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1841 void emit_push_imm(codegendata *cd, s8 imm) {
1842 *(cd->mcodeptr++) = 0x68;
1847 void emit_pop_reg(codegendata *cd, s8 reg) {
1848 emit_rex(0,0,0,(reg));
1849 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1853 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1854 emit_rex(1,(reg),0,(dreg));
1855 *(cd->mcodeptr++) = 0x87;
1856 emit_reg((reg),(dreg));
1860 void emit_nop(codegendata *cd) {
1861 *(cd->mcodeptr++) = 0x90;
1869 void emit_call_reg(codegendata *cd, s8 reg)
1871 emit_rex(0,0,0,(reg));
1872 *(cd->mcodeptr++) = 0xff;
1877 void emit_call_imm(codegendata *cd, s8 imm)
1879 *(cd->mcodeptr++) = 0xe8;
1884 void emit_call_mem(codegendata *cd, ptrint mem)
1886 *(cd->mcodeptr++) = 0xff;
1893 * floating point instructions (SSE2)
1895 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1896 *(cd->mcodeptr++) = 0xf2;
1897 emit_rex(0,(dreg),0,(reg));
1898 *(cd->mcodeptr++) = 0x0f;
1899 *(cd->mcodeptr++) = 0x58;
1900 emit_reg((dreg),(reg));
1904 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1905 *(cd->mcodeptr++) = 0xf3;
1906 emit_rex(0,(dreg),0,(reg));
1907 *(cd->mcodeptr++) = 0x0f;
1908 *(cd->mcodeptr++) = 0x58;
1909 emit_reg((dreg),(reg));
1913 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1914 *(cd->mcodeptr++) = 0xf3;
1915 emit_rex(1,(dreg),0,(reg));
1916 *(cd->mcodeptr++) = 0x0f;
1917 *(cd->mcodeptr++) = 0x2a;
1918 emit_reg((dreg),(reg));
1922 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1923 *(cd->mcodeptr++) = 0xf3;
1924 emit_rex(0,(dreg),0,(reg));
1925 *(cd->mcodeptr++) = 0x0f;
1926 *(cd->mcodeptr++) = 0x2a;
1927 emit_reg((dreg),(reg));
1931 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1932 *(cd->mcodeptr++) = 0xf2;
1933 emit_rex(1,(dreg),0,(reg));
1934 *(cd->mcodeptr++) = 0x0f;
1935 *(cd->mcodeptr++) = 0x2a;
1936 emit_reg((dreg),(reg));
1940 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1941 *(cd->mcodeptr++) = 0xf2;
1942 emit_rex(0,(dreg),0,(reg));
1943 *(cd->mcodeptr++) = 0x0f;
1944 *(cd->mcodeptr++) = 0x2a;
1945 emit_reg((dreg),(reg));
1949 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1950 *(cd->mcodeptr++) = 0xf3;
1951 emit_rex(0,(dreg),0,(reg));
1952 *(cd->mcodeptr++) = 0x0f;
1953 *(cd->mcodeptr++) = 0x5a;
1954 emit_reg((dreg),(reg));
1958 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1959 *(cd->mcodeptr++) = 0xf2;
1960 emit_rex(0,(dreg),0,(reg));
1961 *(cd->mcodeptr++) = 0x0f;
1962 *(cd->mcodeptr++) = 0x5a;
1963 emit_reg((dreg),(reg));
1967 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1968 *(cd->mcodeptr++) = 0xf3;
1969 emit_rex(1,(dreg),0,(reg));
1970 *(cd->mcodeptr++) = 0x0f;
1971 *(cd->mcodeptr++) = 0x2c;
1972 emit_reg((dreg),(reg));
1976 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1977 *(cd->mcodeptr++) = 0xf3;
1978 emit_rex(0,(dreg),0,(reg));
1979 *(cd->mcodeptr++) = 0x0f;
1980 *(cd->mcodeptr++) = 0x2c;
1981 emit_reg((dreg),(reg));
1985 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1986 *(cd->mcodeptr++) = 0xf2;
1987 emit_rex(1,(dreg),0,(reg));
1988 *(cd->mcodeptr++) = 0x0f;
1989 *(cd->mcodeptr++) = 0x2c;
1990 emit_reg((dreg),(reg));
1994 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1995 *(cd->mcodeptr++) = 0xf2;
1996 emit_rex(0,(dreg),0,(reg));
1997 *(cd->mcodeptr++) = 0x0f;
1998 *(cd->mcodeptr++) = 0x2c;
1999 emit_reg((dreg),(reg));
2003 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2004 *(cd->mcodeptr++) = 0xf3;
2005 emit_rex(0,(dreg),0,(reg));
2006 *(cd->mcodeptr++) = 0x0f;
2007 *(cd->mcodeptr++) = 0x5e;
2008 emit_reg((dreg),(reg));
2012 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2013 *(cd->mcodeptr++) = 0xf2;
2014 emit_rex(0,(dreg),0,(reg));
2015 *(cd->mcodeptr++) = 0x0f;
2016 *(cd->mcodeptr++) = 0x5e;
2017 emit_reg((dreg),(reg));
2021 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2022 *(cd->mcodeptr++) = 0x66;
2023 emit_rex(1,(freg),0,(reg));
2024 *(cd->mcodeptr++) = 0x0f;
2025 *(cd->mcodeptr++) = 0x6e;
2026 emit_reg((freg),(reg));
2030 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2031 *(cd->mcodeptr++) = 0x66;
2032 emit_rex(1,(freg),0,(reg));
2033 *(cd->mcodeptr++) = 0x0f;
2034 *(cd->mcodeptr++) = 0x7e;
2035 emit_reg((freg),(reg));
2039 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2040 *(cd->mcodeptr++) = 0x66;
2041 emit_rex(0,(reg),0,(basereg));
2042 *(cd->mcodeptr++) = 0x0f;
2043 *(cd->mcodeptr++) = 0x7e;
2044 emit_membase(cd, (basereg),(disp),(reg));
2048 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2049 *(cd->mcodeptr++) = 0x66;
2050 emit_rex(0,(reg),(indexreg),(basereg));
2051 *(cd->mcodeptr++) = 0x0f;
2052 *(cd->mcodeptr++) = 0x7e;
2053 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2057 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2058 *(cd->mcodeptr++) = 0x66;
2059 emit_rex(1,(dreg),0,(basereg));
2060 *(cd->mcodeptr++) = 0x0f;
2061 *(cd->mcodeptr++) = 0x6e;
2062 emit_membase(cd, (basereg),(disp),(dreg));
2066 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2067 *(cd->mcodeptr++) = 0x66;
2068 emit_rex(0,(dreg),0,(basereg));
2069 *(cd->mcodeptr++) = 0x0f;
2070 *(cd->mcodeptr++) = 0x6e;
2071 emit_membase(cd, (basereg),(disp),(dreg));
2075 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2076 *(cd->mcodeptr++) = 0x66;
2077 emit_rex(0,(dreg),(indexreg),(basereg));
2078 *(cd->mcodeptr++) = 0x0f;
2079 *(cd->mcodeptr++) = 0x6e;
2080 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2084 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2085 *(cd->mcodeptr++) = 0xf3;
2086 emit_rex(0,(dreg),0,(reg));
2087 *(cd->mcodeptr++) = 0x0f;
2088 *(cd->mcodeptr++) = 0x7e;
2089 emit_reg((dreg),(reg));
2093 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2094 *(cd->mcodeptr++) = 0x66;
2095 emit_rex(0,(reg),0,(basereg));
2096 *(cd->mcodeptr++) = 0x0f;
2097 *(cd->mcodeptr++) = 0xd6;
2098 emit_membase(cd, (basereg),(disp),(reg));
2102 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2103 *(cd->mcodeptr++) = 0xf3;
2104 emit_rex(0,(dreg),0,(basereg));
2105 *(cd->mcodeptr++) = 0x0f;
2106 *(cd->mcodeptr++) = 0x7e;
2107 emit_membase(cd, (basereg),(disp),(dreg));
2111 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2112 *(cd->mcodeptr++) = 0xf3;
2113 emit_rex(0,(reg),0,(dreg));
2114 *(cd->mcodeptr++) = 0x0f;
2115 *(cd->mcodeptr++) = 0x10;
2116 emit_reg((reg),(dreg));
2120 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2121 *(cd->mcodeptr++) = 0xf2;
2122 emit_rex(0,(reg),0,(dreg));
2123 *(cd->mcodeptr++) = 0x0f;
2124 *(cd->mcodeptr++) = 0x10;
2125 emit_reg((reg),(dreg));
2129 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2130 *(cd->mcodeptr++) = 0xf3;
2131 emit_rex(0,(reg),0,(basereg));
2132 *(cd->mcodeptr++) = 0x0f;
2133 *(cd->mcodeptr++) = 0x11;
2134 emit_membase(cd, (basereg),(disp),(reg));
2138 /* Always emit a REX byte, because the instruction size can be smaller when */
2139 /* all register indexes are smaller than 7. */
2140 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2141 *(cd->mcodeptr++) = 0xf3;
2142 emit_byte_rex((reg),0,(basereg));
2143 *(cd->mcodeptr++) = 0x0f;
2144 *(cd->mcodeptr++) = 0x11;
2145 emit_membase32(cd, (basereg),(disp),(reg));
2149 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2150 *(cd->mcodeptr++) = 0xf2;
2151 emit_rex(0,(reg),0,(basereg));
2152 *(cd->mcodeptr++) = 0x0f;
2153 *(cd->mcodeptr++) = 0x11;
2154 emit_membase(cd, (basereg),(disp),(reg));
2158 /* Always emit a REX byte, because the instruction size can be smaller when */
2159 /* all register indexes are smaller than 7. */
2160 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2161 *(cd->mcodeptr++) = 0xf2;
2162 emit_byte_rex((reg),0,(basereg));
2163 *(cd->mcodeptr++) = 0x0f;
2164 *(cd->mcodeptr++) = 0x11;
2165 emit_membase32(cd, (basereg),(disp),(reg));
2169 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2170 *(cd->mcodeptr++) = 0xf3;
2171 emit_rex(0,(dreg),0,(basereg));
2172 *(cd->mcodeptr++) = 0x0f;
2173 *(cd->mcodeptr++) = 0x10;
2174 emit_membase(cd, (basereg),(disp),(dreg));
2178 /* Always emit a REX byte, because the instruction size can be smaller when */
2179 /* all register indexes are smaller than 7. */
2180 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2181 *(cd->mcodeptr++) = 0xf3;
2182 emit_byte_rex((dreg),0,(basereg));
2183 *(cd->mcodeptr++) = 0x0f;
2184 *(cd->mcodeptr++) = 0x10;
2185 emit_membase32(cd, (basereg),(disp),(dreg));
2189 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2191 emit_rex(0,(dreg),0,(basereg));
2192 *(cd->mcodeptr++) = 0x0f;
2193 *(cd->mcodeptr++) = 0x12;
2194 emit_membase(cd, (basereg),(disp),(dreg));
2198 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2200 emit_rex(0,(reg),0,(basereg));
2201 *(cd->mcodeptr++) = 0x0f;
2202 *(cd->mcodeptr++) = 0x13;
2203 emit_membase(cd, (basereg),(disp),(reg));
2207 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2208 *(cd->mcodeptr++) = 0xf2;
2209 emit_rex(0,(dreg),0,(basereg));
2210 *(cd->mcodeptr++) = 0x0f;
2211 *(cd->mcodeptr++) = 0x10;
2212 emit_membase(cd, (basereg),(disp),(dreg));
2216 /* Always emit a REX byte, because the instruction size can be smaller when */
2217 /* all register indexes are smaller than 7. */
2218 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2219 *(cd->mcodeptr++) = 0xf2;
2220 emit_byte_rex((dreg),0,(basereg));
2221 *(cd->mcodeptr++) = 0x0f;
2222 *(cd->mcodeptr++) = 0x10;
2223 emit_membase32(cd, (basereg),(disp),(dreg));
2227 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2229 *(cd->mcodeptr++) = 0x66;
2230 emit_rex(0,(dreg),0,(basereg));
2231 *(cd->mcodeptr++) = 0x0f;
2232 *(cd->mcodeptr++) = 0x12;
2233 emit_membase(cd, (basereg),(disp),(dreg));
2237 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2239 *(cd->mcodeptr++) = 0x66;
2240 emit_rex(0,(reg),0,(basereg));
2241 *(cd->mcodeptr++) = 0x0f;
2242 *(cd->mcodeptr++) = 0x13;
2243 emit_membase(cd, (basereg),(disp),(reg));
2247 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2248 *(cd->mcodeptr++) = 0xf3;
2249 emit_rex(0,(reg),(indexreg),(basereg));
2250 *(cd->mcodeptr++) = 0x0f;
2251 *(cd->mcodeptr++) = 0x11;
2252 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2256 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2257 *(cd->mcodeptr++) = 0xf2;
2258 emit_rex(0,(reg),(indexreg),(basereg));
2259 *(cd->mcodeptr++) = 0x0f;
2260 *(cd->mcodeptr++) = 0x11;
2261 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2265 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2266 *(cd->mcodeptr++) = 0xf3;
2267 emit_rex(0,(dreg),(indexreg),(basereg));
2268 *(cd->mcodeptr++) = 0x0f;
2269 *(cd->mcodeptr++) = 0x10;
2270 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2274 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2275 *(cd->mcodeptr++) = 0xf2;
2276 emit_rex(0,(dreg),(indexreg),(basereg));
2277 *(cd->mcodeptr++) = 0x0f;
2278 *(cd->mcodeptr++) = 0x10;
2279 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2283 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2284 *(cd->mcodeptr++) = 0xf3;
2285 emit_rex(0,(dreg),0,(reg));
2286 *(cd->mcodeptr++) = 0x0f;
2287 *(cd->mcodeptr++) = 0x59;
2288 emit_reg((dreg),(reg));
2292 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2293 *(cd->mcodeptr++) = 0xf2;
2294 emit_rex(0,(dreg),0,(reg));
2295 *(cd->mcodeptr++) = 0x0f;
2296 *(cd->mcodeptr++) = 0x59;
2297 emit_reg((dreg),(reg));
2301 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2302 *(cd->mcodeptr++) = 0xf3;
2303 emit_rex(0,(dreg),0,(reg));
2304 *(cd->mcodeptr++) = 0x0f;
2305 *(cd->mcodeptr++) = 0x5c;
2306 emit_reg((dreg),(reg));
2310 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2311 *(cd->mcodeptr++) = 0xf2;
2312 emit_rex(0,(dreg),0,(reg));
2313 *(cd->mcodeptr++) = 0x0f;
2314 *(cd->mcodeptr++) = 0x5c;
2315 emit_reg((dreg),(reg));
2319 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2320 emit_rex(0,(dreg),0,(reg));
2321 *(cd->mcodeptr++) = 0x0f;
2322 *(cd->mcodeptr++) = 0x2e;
2323 emit_reg((dreg),(reg));
2327 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2328 *(cd->mcodeptr++) = 0x66;
2329 emit_rex(0,(dreg),0,(reg));
2330 *(cd->mcodeptr++) = 0x0f;
2331 *(cd->mcodeptr++) = 0x2e;
2332 emit_reg((dreg),(reg));
2336 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2337 emit_rex(0,(dreg),0,(reg));
2338 *(cd->mcodeptr++) = 0x0f;
2339 *(cd->mcodeptr++) = 0x57;
2340 emit_reg((dreg),(reg));
2344 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2345 emit_rex(0,(dreg),0,(basereg));
2346 *(cd->mcodeptr++) = 0x0f;
2347 *(cd->mcodeptr++) = 0x57;
2348 emit_membase(cd, (basereg),(disp),(dreg));
2352 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2353 *(cd->mcodeptr++) = 0x66;
2354 emit_rex(0,(dreg),0,(reg));
2355 *(cd->mcodeptr++) = 0x0f;
2356 *(cd->mcodeptr++) = 0x57;
2357 emit_reg((dreg),(reg));
2361 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2362 *(cd->mcodeptr++) = 0x66;
2363 emit_rex(0,(dreg),0,(basereg));
2364 *(cd->mcodeptr++) = 0x0f;
2365 *(cd->mcodeptr++) = 0x57;
2366 emit_membase(cd, (basereg),(disp),(dreg));
2370 /* system instructions ********************************************************/
2372 void emit_rdtsc(codegendata *cd)
2374 *(cd->mcodeptr++) = 0x0f;
2375 *(cd->mcodeptr++) = 0x31;
2380 * These are local overrides for various environment variables in Emacs.
2381 * Please do not remove this and leave it at the end of the file, where
2382 * Emacs will automagically detect them.
2383 * ---------------------------------------------------------------------
2386 * indent-tabs-mode: t