1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7713 2007-04-15 21:49:48Z twisti $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
47 #include "vm/exceptions.h"
49 #include "vm/jit/abi.h"
50 #include "vm/jit/abi-asm.h"
51 #include "vm/jit/asmpart.h"
52 #include "vm/jit/codegen-common.h"
53 #include "vm/jit/emit-common.h"
54 #include "vm/jit/jit.h"
55 #include "vm/jit/replace.h"
57 #include "vmcore/options.h"
60 /* emit_load *******************************************************************
62 Emits a possible load of an operand.
64 *******************************************************************************/
66 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
72 /* get required compiler data */
76 if (IS_INMEMORY(src->flags)) {
79 disp = src->vv.regoff * 8;
83 M_ILD(tempreg, REG_SP, disp);
87 M_LLD(tempreg, REG_SP, disp);
90 M_FLD(tempreg, REG_SP, disp);
93 M_DLD(tempreg, REG_SP, disp);
96 vm_abort("emit_load: unknown type %d", src->type);
102 reg = src->vv.regoff;
108 /* emit_store ******************************************************************
110 This function generates the code to store the result of an
111 operation back into a spilled pseudo-variable. If the
112 pseudo-variable has not been spilled in the first place, this
113 function will generate nothing.
115 *******************************************************************************/
117 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
126 /* get required compiler data */
131 /* do we have to generate a conditional move? */
133 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
134 /* the passed register d is actually the source register */
138 /* Only pass the opcode to codegen_reg_of_var to get the real
139 destination register. */
141 opcode = iptr->opc & ICMD_OPCODE_MASK;
143 /* get the real destination register */
145 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
147 /* and emit the conditional move */
149 emit_cmovxx(cd, iptr, s, d);
153 if (IS_INMEMORY(dst->flags)) {
156 disp = dst->vv.regoff * 8;
162 M_LST(d, REG_SP, disp);
165 M_FST(d, REG_SP, disp);
168 M_DST(d, REG_SP, disp);
171 vm_abort("emit_store: unknown type %d", dst->type);
177 /* emit_copy *******************************************************************
179 Generates a register/memory to register/memory copy.
181 *******************************************************************************/
183 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
188 /* get required compiler data */
192 if ((src->vv.regoff != dst->vv.regoff) ||
193 ((src->flags ^ dst->flags) & INMEMORY)) {
195 /* If one of the variables resides in memory, we can eliminate
196 the register move from/to the temporary register with the
197 order of getting the destination register and the load. */
199 if (IS_INMEMORY(src->flags)) {
200 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
201 s1 = emit_load(jd, iptr, src, d);
204 s1 = emit_load(jd, iptr, src, REG_IFTMP);
205 d = codegen_reg_of_var(iptr->opc, dst, s1);
220 vm_abort("emit_copy: unknown type %d", src->type);
224 emit_store(jd, iptr, dst, d);
229 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
232 switch (iptr->flags.fields.condition) {
256 /* emit_branch *****************************************************************
258 Emits the code for conditional and unconditional branchs.
260 *******************************************************************************/
262 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
266 /* NOTE: A displacement overflow cannot happen. */
268 /* check which branch to generate */
270 if (condition == BRANCH_UNCONDITIONAL) {
272 /* calculate the different displacements */
274 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
276 M_JMP_IMM(branchdisp);
279 /* calculate the different displacements */
281 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
315 vm_abort("emit_branch: unknown condition %d", condition);
321 /* emit_arithmetic_check *******************************************************
323 Emit an ArithmeticException check.
325 *******************************************************************************/
327 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
329 if (INSTRUCTION_MUST_CHECK(iptr)) {
332 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
337 /* emit_arrayindexoutofbounds_check ********************************************
339 Emit a ArrayIndexOutOfBoundsException check.
341 *******************************************************************************/
343 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
345 if (INSTRUCTION_MUST_CHECK(iptr)) {
346 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
347 M_ICMP(REG_ITMP3, s2);
349 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
354 /* emit_classcast_check ********************************************************
356 Emit a ClassCastException check.
358 *******************************************************************************/
360 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
362 if (INSTRUCTION_MUST_CHECK(iptr)) {
374 vm_abort("emit_classcast_check: unknown condition %d", condition);
376 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
381 /* emit_nullpointer_check ******************************************************
383 Emit a NullPointerException check.
385 *******************************************************************************/
387 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
389 if (INSTRUCTION_MUST_CHECK(iptr)) {
392 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
397 /* emit_exception_check ********************************************************
399 Emit an Exception check.
401 *******************************************************************************/
403 void emit_exception_check(codegendata *cd, instruction *iptr)
405 if (INSTRUCTION_MUST_CHECK(iptr)) {
408 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
413 /* emit_patcher_stubs **********************************************************
415 Generates the code for the patcher stubs.
417 *******************************************************************************/
419 void emit_patcher_stubs(jitdata *jd)
429 /* get required compiler data */
433 /* generate code patching stub call code */
437 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
438 /* check size of code segment */
442 /* Get machine code which is patched back in later. A
443 `call rel32' is 5 bytes long (but read 8 bytes). */
445 savedmcodeptr = cd->mcodebase + pref->branchpos;
446 mcode = *((u8 *) savedmcodeptr);
448 /* patch in `call rel32' to call the following code */
450 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
451 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
453 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
455 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
457 /* move pointer to java_objectheader onto stack */
459 #if defined(ENABLE_THREADS)
460 /* create a virtual java_objectheader */
462 (void) dseg_add_unique_address(cd, NULL); /* flcword */
463 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
464 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
466 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
472 /* move machine code bytes and classinfo pointer into registers */
474 M_MOV_IMM(mcode, REG_ITMP3);
477 M_MOV_IMM(pref->ref, REG_ITMP3);
480 M_MOV_IMM(pref->disp, REG_ITMP3);
483 M_MOV_IMM(pref->patcher, REG_ITMP3);
486 if (targetdisp == 0) {
487 targetdisp = cd->mcodeptr - cd->mcodebase;
489 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
493 M_JMP_IMM((cd->mcodebase + targetdisp) -
494 (cd->mcodeptr + PATCHER_CALL_SIZE));
500 /* emit_replacement_stubs ******************************************************
502 Generates the code for the replacement stubs.
504 *******************************************************************************/
506 #if defined(ENABLE_REPLACEMENT)
507 void emit_replacement_stubs(jitdata *jd)
517 /* get required compiler data */
522 rplp = code->rplpoints;
524 /* store beginning of replacement stubs */
526 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
528 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
529 /* do not generate stubs for non-trappable points */
531 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
534 /* check code segment size */
538 /* note start of stub code */
541 savedmcodeptr = cd->mcodeptr;
544 /* push address of `rplpoint` struct */
546 M_MOV_IMM(rplp, REG_ITMP3);
549 /* jump to replacement function */
551 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
555 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
558 #endif /* defined(ENABLE_REPLACEMENT) */
561 /* emit_verbosecall_enter ******************************************************
563 Generates the code for the call trace.
565 *******************************************************************************/
568 void emit_verbosecall_enter(jitdata *jd)
576 /* get required compiler data */
584 /* mark trace code */
588 /* additional +1 is for 16-byte stack alignment */
590 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
592 /* save argument registers */
594 for (i = 0; i < INT_ARG_CNT; i++)
595 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
597 for (i = 0; i < FLT_ARG_CNT; i++)
598 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
600 /* save temporary registers for leaf methods */
602 if (jd->isleafmethod) {
603 for (i = 0; i < INT_TMP_CNT; i++)
604 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
606 for (i = 0; i < FLT_TMP_CNT; i++)
607 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
610 /* show integer hex code for float arguments */
612 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
613 /* If the paramtype is a float, we have to right shift all
614 following integer registers. */
616 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
617 for (k = INT_ARG_CNT - 2; k >= i; k--)
618 M_MOV(abi_registers_integer_argument[k],
619 abi_registers_integer_argument[k + 1]);
621 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
622 abi_registers_integer_argument[i]);
627 M_MOV_IMM(m, REG_ITMP2);
628 M_AST(REG_ITMP2, REG_SP, 0 * 8);
629 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
632 /* restore argument registers */
634 for (i = 0; i < INT_ARG_CNT; i++)
635 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
637 for (i = 0; i < FLT_ARG_CNT; i++)
638 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
640 /* restore temporary registers for leaf methods */
642 if (jd->isleafmethod) {
643 for (i = 0; i < INT_TMP_CNT; i++)
644 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
646 for (i = 0; i < FLT_TMP_CNT; i++)
647 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
650 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
652 /* mark trace code */
656 #endif /* !defined(NDEBUG) */
659 /* emit_verbosecall_exit *******************************************************
661 Generates the code for the call trace.
663 *******************************************************************************/
666 void emit_verbosecall_exit(jitdata *jd)
672 /* get required compiler data */
678 /* mark trace code */
682 M_ASUB_IMM(2 * 8, REG_SP);
684 M_LST(REG_RESULT, REG_SP, 0 * 8);
685 M_DST(REG_FRESULT, REG_SP, 1 * 8);
687 M_INTMOVE(REG_RESULT, REG_A0);
688 M_FLTMOVE(REG_FRESULT, REG_FA0);
689 M_FLTMOVE(REG_FRESULT, REG_FA1);
690 M_MOV_IMM(m, REG_A1);
692 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
695 M_LLD(REG_RESULT, REG_SP, 0 * 8);
696 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
698 M_AADD_IMM(2 * 8, REG_SP);
700 /* mark trace code */
704 #endif /* !defined(NDEBUG) */
707 /* code generation functions **************************************************/
709 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
711 if ((basereg == REG_SP) || (basereg == R12)) {
713 emit_address_byte(0, dreg, REG_SP);
714 emit_address_byte(0, REG_SP, REG_SP);
716 } else if (IS_IMM8(disp)) {
717 emit_address_byte(1, dreg, REG_SP);
718 emit_address_byte(0, REG_SP, REG_SP);
722 emit_address_byte(2, dreg, REG_SP);
723 emit_address_byte(0, REG_SP, REG_SP);
727 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
728 emit_address_byte(0,(dreg),(basereg));
730 } else if ((basereg) == RIP) {
731 emit_address_byte(0, dreg, RBP);
736 emit_address_byte(1, dreg, basereg);
740 emit_address_byte(2, dreg, basereg);
747 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
749 if ((basereg == REG_SP) || (basereg == R12)) {
750 emit_address_byte(2, dreg, REG_SP);
751 emit_address_byte(0, REG_SP, REG_SP);
755 emit_address_byte(2, dreg, basereg);
761 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
764 emit_address_byte(0, reg, 4);
765 emit_address_byte(scale, indexreg, 5);
768 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
769 emit_address_byte(0, reg, 4);
770 emit_address_byte(scale, indexreg, basereg);
772 else if (IS_IMM8(disp)) {
773 emit_address_byte(1, reg, 4);
774 emit_address_byte(scale, indexreg, basereg);
778 emit_address_byte(2, reg, 4);
779 emit_address_byte(scale, indexreg, basereg);
785 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
788 varinfo *v_s1,*v_s2,*v_dst;
791 /* get required compiler data */
795 v_s1 = VAROP(iptr->s1);
796 v_s2 = VAROP(iptr->sx.s23.s2);
797 v_dst = VAROP(iptr->dst);
799 s1 = v_s1->vv.regoff;
800 s2 = v_s2->vv.regoff;
801 d = v_dst->vv.regoff;
803 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
805 if (IS_INMEMORY(v_dst->flags)) {
806 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
808 M_ILD(RCX, REG_SP, s2 * 8);
809 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
812 M_ILD(RCX, REG_SP, s2 * 8);
813 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
814 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
815 M_IST(REG_ITMP2, REG_SP, d * 8);
818 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
819 /* s1 may be equal to RCX */
822 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
823 M_IST(s1, REG_SP, d * 8);
824 M_INTMOVE(REG_ITMP1, RCX);
827 M_IST(s1, REG_SP, d * 8);
828 M_ILD(RCX, REG_SP, s2 * 8);
832 M_ILD(RCX, REG_SP, s2 * 8);
833 M_IST(s1, REG_SP, d * 8);
836 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
838 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
841 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
845 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
846 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
847 M_IST(REG_ITMP2, REG_SP, d * 8);
851 /* s1 may be equal to RCX */
852 M_IST(s1, REG_SP, d * 8);
854 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
857 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
865 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
866 M_ILD(RCX, REG_SP, s2 * 8);
867 M_ILD(d, REG_SP, s1 * 8);
868 emit_shiftl_reg(cd, shift_op, d);
870 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
871 /* s1 may be equal to RCX */
873 M_ILD(RCX, REG_SP, s2 * 8);
874 emit_shiftl_reg(cd, shift_op, d);
876 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
878 M_ILD(d, REG_SP, s1 * 8);
879 emit_shiftl_reg(cd, shift_op, d);
882 /* s1 may be equal to RCX */
885 /* d cannot be used to backup s1 since this would
887 M_INTMOVE(s1, REG_ITMP3);
889 M_INTMOVE(REG_ITMP3, d);
897 /* d may be equal to s2 */
901 emit_shiftl_reg(cd, shift_op, d);
905 M_INTMOVE(REG_ITMP3, RCX);
907 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
912 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
915 varinfo *v_s1,*v_s2,*v_dst;
918 /* get required compiler data */
922 v_s1 = VAROP(iptr->s1);
923 v_s2 = VAROP(iptr->sx.s23.s2);
924 v_dst = VAROP(iptr->dst);
926 s1 = v_s1->vv.regoff;
927 s2 = v_s2->vv.regoff;
928 d = v_dst->vv.regoff;
930 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
932 if (IS_INMEMORY(v_dst->flags)) {
933 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
935 M_ILD(RCX, REG_SP, s2 * 8);
936 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
939 M_ILD(RCX, REG_SP, s2 * 8);
940 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
941 emit_shift_reg(cd, shift_op, REG_ITMP2);
942 M_LST(REG_ITMP2, REG_SP, d * 8);
945 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
946 /* s1 may be equal to RCX */
949 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
950 M_LST(s1, REG_SP, d * 8);
951 M_INTMOVE(REG_ITMP1, RCX);
954 M_LST(s1, REG_SP, d * 8);
955 M_ILD(RCX, REG_SP, s2 * 8);
959 M_ILD(RCX, REG_SP, s2 * 8);
960 M_LST(s1, REG_SP, d * 8);
963 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
965 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
968 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
972 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
973 emit_shift_reg(cd, shift_op, REG_ITMP2);
974 M_LST(REG_ITMP2, REG_SP, d * 8);
978 /* s1 may be equal to RCX */
979 M_LST(s1, REG_SP, d * 8);
981 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
984 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
992 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
993 M_ILD(RCX, REG_SP, s2 * 8);
994 M_LLD(d, REG_SP, s1 * 8);
995 emit_shift_reg(cd, shift_op, d);
997 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
998 /* s1 may be equal to RCX */
1000 M_ILD(RCX, REG_SP, s2 * 8);
1001 emit_shift_reg(cd, shift_op, d);
1003 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1005 M_LLD(d, REG_SP, s1 * 8);
1006 emit_shift_reg(cd, shift_op, d);
1009 /* s1 may be equal to RCX */
1012 /* d cannot be used to backup s1 since this would
1014 M_INTMOVE(s1, REG_ITMP3);
1016 M_INTMOVE(REG_ITMP3, d);
1024 /* d may be equal to s2 */
1028 emit_shift_reg(cd, shift_op, d);
1032 M_INTMOVE(REG_ITMP3, RCX);
1034 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1039 /* low-level code emitter functions *******************************************/
1041 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1043 emit_rex(1,(reg),0,(dreg));
1044 *(cd->mcodeptr++) = 0x89;
1045 emit_reg((reg),(dreg));
1049 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1051 emit_rex(1,0,0,(reg));
1052 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1057 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1059 emit_rex(0,(reg),0,(dreg));
1060 *(cd->mcodeptr++) = 0x89;
1061 emit_reg((reg),(dreg));
1065 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1066 emit_rex(0,0,0,(reg));
1067 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1072 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1073 emit_rex(1,(reg),0,(basereg));
1074 *(cd->mcodeptr++) = 0x8b;
1075 emit_membase(cd, (basereg),(disp),(reg));
1080 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1081 * constant membase immediate length of 32bit
1083 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1084 emit_rex(1,(reg),0,(basereg));
1085 *(cd->mcodeptr++) = 0x8b;
1086 emit_membase32(cd, (basereg),(disp),(reg));
1090 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1092 emit_rex(0,(reg),0,(basereg));
1093 *(cd->mcodeptr++) = 0x8b;
1094 emit_membase(cd, (basereg),(disp),(reg));
1098 /* ATTENTION: Always emit a REX byte, because the instruction size can
1099 be smaller when all register indexes are smaller than 7. */
1100 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1102 emit_byte_rex((reg),0,(basereg));
1103 *(cd->mcodeptr++) = 0x8b;
1104 emit_membase32(cd, (basereg),(disp),(reg));
1108 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1109 emit_rex(1,(reg),0,(basereg));
1110 *(cd->mcodeptr++) = 0x89;
1111 emit_membase(cd, (basereg),(disp),(reg));
1115 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1116 emit_rex(1,(reg),0,(basereg));
1117 *(cd->mcodeptr++) = 0x89;
1118 emit_membase32(cd, (basereg),(disp),(reg));
1122 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1123 emit_rex(0,(reg),0,(basereg));
1124 *(cd->mcodeptr++) = 0x89;
1125 emit_membase(cd, (basereg),(disp),(reg));
1129 /* Always emit a REX byte, because the instruction size can be smaller when */
1130 /* all register indexes are smaller than 7. */
1131 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1132 emit_byte_rex((reg),0,(basereg));
1133 *(cd->mcodeptr++) = 0x89;
1134 emit_membase32(cd, (basereg),(disp),(reg));
1138 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1139 emit_rex(1,(reg),(indexreg),(basereg));
1140 *(cd->mcodeptr++) = 0x8b;
1141 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1145 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1146 emit_rex(0,(reg),(indexreg),(basereg));
1147 *(cd->mcodeptr++) = 0x8b;
1148 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1152 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1153 emit_rex(1,(reg),(indexreg),(basereg));
1154 *(cd->mcodeptr++) = 0x89;
1155 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1159 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1160 emit_rex(0,(reg),(indexreg),(basereg));
1161 *(cd->mcodeptr++) = 0x89;
1162 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1166 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1167 *(cd->mcodeptr++) = 0x66;
1168 emit_rex(0,(reg),(indexreg),(basereg));
1169 *(cd->mcodeptr++) = 0x89;
1170 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1174 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1175 emit_byte_rex((reg),(indexreg),(basereg));
1176 *(cd->mcodeptr++) = 0x88;
1177 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1181 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1182 emit_rex(1,0,0,(basereg));
1183 *(cd->mcodeptr++) = 0xc7;
1184 emit_membase(cd, (basereg),(disp),0);
1189 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1190 emit_rex(1,0,0,(basereg));
1191 *(cd->mcodeptr++) = 0xc7;
1192 emit_membase32(cd, (basereg),(disp),0);
1197 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1198 emit_rex(0,0,0,(basereg));
1199 *(cd->mcodeptr++) = 0xc7;
1200 emit_membase(cd, (basereg),(disp),0);
1205 /* Always emit a REX byte, because the instruction size can be smaller when */
1206 /* all register indexes are smaller than 7. */
1207 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1208 emit_byte_rex(0,0,(basereg));
1209 *(cd->mcodeptr++) = 0xc7;
1210 emit_membase32(cd, (basereg),(disp),0);
1215 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1217 emit_rex(1,(dreg),0,(reg));
1218 *(cd->mcodeptr++) = 0x0f;
1219 *(cd->mcodeptr++) = 0xbe;
1220 /* XXX: why do reg and dreg have to be exchanged */
1221 emit_reg((dreg),(reg));
1225 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1227 emit_rex(1,(dreg),0,(reg));
1228 *(cd->mcodeptr++) = 0x0f;
1229 *(cd->mcodeptr++) = 0xbf;
1230 /* XXX: why do reg and dreg have to be exchanged */
1231 emit_reg((dreg),(reg));
1235 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1237 emit_rex(1,(dreg),0,(reg));
1238 *(cd->mcodeptr++) = 0x63;
1239 /* XXX: why do reg and dreg have to be exchanged */
1240 emit_reg((dreg),(reg));
1244 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1246 emit_rex(1,(dreg),0,(reg));
1247 *(cd->mcodeptr++) = 0x0f;
1248 *(cd->mcodeptr++) = 0xb7;
1249 /* XXX: why do reg and dreg have to be exchanged */
1250 emit_reg((dreg),(reg));
1254 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1255 emit_rex(1,(reg),(indexreg),(basereg));
1256 *(cd->mcodeptr++) = 0x0f;
1257 *(cd->mcodeptr++) = 0xbf;
1258 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1262 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1263 emit_rex(1,(reg),(indexreg),(basereg));
1264 *(cd->mcodeptr++) = 0x0f;
1265 *(cd->mcodeptr++) = 0xbe;
1266 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1270 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1271 emit_rex(1,(reg),(indexreg),(basereg));
1272 *(cd->mcodeptr++) = 0x0f;
1273 *(cd->mcodeptr++) = 0xb7;
1274 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1278 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1280 emit_rex(1,0,(indexreg),(basereg));
1281 *(cd->mcodeptr++) = 0xc7;
1282 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1287 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1289 emit_rex(0,0,(indexreg),(basereg));
1290 *(cd->mcodeptr++) = 0xc7;
1291 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1296 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1298 *(cd->mcodeptr++) = 0x66;
1299 emit_rex(0,0,(indexreg),(basereg));
1300 *(cd->mcodeptr++) = 0xc7;
1301 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1306 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1308 emit_rex(0,0,(indexreg),(basereg));
1309 *(cd->mcodeptr++) = 0xc6;
1310 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1315 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1317 emit_rex(1, dreg, 0, 0);
1318 *(cd->mcodeptr++) = 0x8b;
1319 emit_address_byte(0, dreg, 4);
1327 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1329 emit_rex(1,(reg),0,(dreg));
1330 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1331 emit_reg((reg),(dreg));
1335 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1337 emit_rex(0,(reg),0,(dreg));
1338 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1339 emit_reg((reg),(dreg));
1343 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1345 emit_rex(1,(reg),0,(basereg));
1346 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1347 emit_membase(cd, (basereg),(disp),(reg));
1351 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1353 emit_rex(0,(reg),0,(basereg));
1354 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1355 emit_membase(cd, (basereg),(disp),(reg));
1359 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1361 emit_rex(1,(reg),0,(basereg));
1362 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1363 emit_membase(cd, (basereg),(disp),(reg));
1367 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1369 emit_rex(0,(reg),0,(basereg));
1370 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1371 emit_membase(cd, (basereg),(disp),(reg));
1375 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1377 emit_rex(1,0,0,(dreg));
1378 *(cd->mcodeptr++) = 0x83;
1379 emit_reg((opc),(dreg));
1382 emit_rex(1,0,0,(dreg));
1383 *(cd->mcodeptr++) = 0x81;
1384 emit_reg((opc),(dreg));
1390 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1392 emit_rex(1,0,0,(dreg));
1393 *(cd->mcodeptr++) = 0x81;
1394 emit_reg((opc),(dreg));
1399 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1401 emit_rex(0,0,0,(dreg));
1402 *(cd->mcodeptr++) = 0x81;
1403 emit_reg((opc),(dreg));
1408 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1410 emit_rex(0,0,0,(dreg));
1411 *(cd->mcodeptr++) = 0x83;
1412 emit_reg((opc),(dreg));
1415 emit_rex(0,0,0,(dreg));
1416 *(cd->mcodeptr++) = 0x81;
1417 emit_reg((opc),(dreg));
1423 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1425 emit_rex(1,(basereg),0,0);
1426 *(cd->mcodeptr++) = 0x83;
1427 emit_membase(cd, (basereg),(disp),(opc));
1430 emit_rex(1,(basereg),0,0);
1431 *(cd->mcodeptr++) = 0x81;
1432 emit_membase(cd, (basereg),(disp),(opc));
1438 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1440 emit_rex(0,(basereg),0,0);
1441 *(cd->mcodeptr++) = 0x83;
1442 emit_membase(cd, (basereg),(disp),(opc));
1445 emit_rex(0,(basereg),0,0);
1446 *(cd->mcodeptr++) = 0x81;
1447 emit_membase(cd, (basereg),(disp),(opc));
1453 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1454 emit_rex(1,(reg),0,(dreg));
1455 *(cd->mcodeptr++) = 0x85;
1456 emit_reg((reg),(dreg));
1460 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1461 emit_rex(0,(reg),0,(dreg));
1462 *(cd->mcodeptr++) = 0x85;
1463 emit_reg((reg),(dreg));
1467 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1468 *(cd->mcodeptr++) = 0xf7;
1474 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1475 *(cd->mcodeptr++) = 0x66;
1476 *(cd->mcodeptr++) = 0xf7;
1482 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1483 *(cd->mcodeptr++) = 0xf6;
1489 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1490 emit_rex(1,(reg),0,(basereg));
1491 *(cd->mcodeptr++) = 0x8d;
1492 emit_membase(cd, (basereg),(disp),(reg));
1496 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1497 emit_rex(0,(reg),0,(basereg));
1498 *(cd->mcodeptr++) = 0x8d;
1499 emit_membase(cd, (basereg),(disp),(reg));
1504 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1506 emit_rex(0,0,0,(basereg));
1507 *(cd->mcodeptr++) = 0xff;
1508 emit_membase(cd, (basereg),(disp),0);
1513 void emit_cltd(codegendata *cd) {
1514 *(cd->mcodeptr++) = 0x99;
1518 void emit_cqto(codegendata *cd) {
1520 *(cd->mcodeptr++) = 0x99;
1525 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1526 emit_rex(1,(dreg),0,(reg));
1527 *(cd->mcodeptr++) = 0x0f;
1528 *(cd->mcodeptr++) = 0xaf;
1529 emit_reg((dreg),(reg));
1533 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1534 emit_rex(0,(dreg),0,(reg));
1535 *(cd->mcodeptr++) = 0x0f;
1536 *(cd->mcodeptr++) = 0xaf;
1537 emit_reg((dreg),(reg));
1541 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1542 emit_rex(1,(dreg),0,(basereg));
1543 *(cd->mcodeptr++) = 0x0f;
1544 *(cd->mcodeptr++) = 0xaf;
1545 emit_membase(cd, (basereg),(disp),(dreg));
1549 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1550 emit_rex(0,(dreg),0,(basereg));
1551 *(cd->mcodeptr++) = 0x0f;
1552 *(cd->mcodeptr++) = 0xaf;
1553 emit_membase(cd, (basereg),(disp),(dreg));
1557 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1558 if (IS_IMM8((imm))) {
1559 emit_rex(1,0,0,(dreg));
1560 *(cd->mcodeptr++) = 0x6b;
1564 emit_rex(1,0,0,(dreg));
1565 *(cd->mcodeptr++) = 0x69;
1572 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1573 if (IS_IMM8((imm))) {
1574 emit_rex(1,(dreg),0,(reg));
1575 *(cd->mcodeptr++) = 0x6b;
1576 emit_reg((dreg),(reg));
1579 emit_rex(1,(dreg),0,(reg));
1580 *(cd->mcodeptr++) = 0x69;
1581 emit_reg((dreg),(reg));
1587 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1588 if (IS_IMM8((imm))) {
1589 emit_rex(0,(dreg),0,(reg));
1590 *(cd->mcodeptr++) = 0x6b;
1591 emit_reg((dreg),(reg));
1594 emit_rex(0,(dreg),0,(reg));
1595 *(cd->mcodeptr++) = 0x69;
1596 emit_reg((dreg),(reg));
1602 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1603 if (IS_IMM8((imm))) {
1604 emit_rex(1,(dreg),0,(basereg));
1605 *(cd->mcodeptr++) = 0x6b;
1606 emit_membase(cd, (basereg),(disp),(dreg));
1609 emit_rex(1,(dreg),0,(basereg));
1610 *(cd->mcodeptr++) = 0x69;
1611 emit_membase(cd, (basereg),(disp),(dreg));
1617 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1618 if (IS_IMM8((imm))) {
1619 emit_rex(0,(dreg),0,(basereg));
1620 *(cd->mcodeptr++) = 0x6b;
1621 emit_membase(cd, (basereg),(disp),(dreg));
1624 emit_rex(0,(dreg),0,(basereg));
1625 *(cd->mcodeptr++) = 0x69;
1626 emit_membase(cd, (basereg),(disp),(dreg));
1632 void emit_idiv_reg(codegendata *cd, s8 reg) {
1633 emit_rex(1,0,0,(reg));
1634 *(cd->mcodeptr++) = 0xf7;
1639 void emit_idivl_reg(codegendata *cd, s8 reg) {
1640 emit_rex(0,0,0,(reg));
1641 *(cd->mcodeptr++) = 0xf7;
1647 void emit_ret(codegendata *cd) {
1648 *(cd->mcodeptr++) = 0xc3;
1656 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1657 emit_rex(1,0,0,(reg));
1658 *(cd->mcodeptr++) = 0xd3;
1659 emit_reg((opc),(reg));
1663 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1664 emit_rex(0,0,0,(reg));
1665 *(cd->mcodeptr++) = 0xd3;
1666 emit_reg((opc),(reg));
1670 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1671 emit_rex(1,0,0,(basereg));
1672 *(cd->mcodeptr++) = 0xd3;
1673 emit_membase(cd, (basereg),(disp),(opc));
1677 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1678 emit_rex(0,0,0,(basereg));
1679 *(cd->mcodeptr++) = 0xd3;
1680 emit_membase(cd, (basereg),(disp),(opc));
1684 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1686 emit_rex(1,0,0,(dreg));
1687 *(cd->mcodeptr++) = 0xd1;
1688 emit_reg((opc),(dreg));
1690 emit_rex(1,0,0,(dreg));
1691 *(cd->mcodeptr++) = 0xc1;
1692 emit_reg((opc),(dreg));
1698 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1700 emit_rex(0,0,0,(dreg));
1701 *(cd->mcodeptr++) = 0xd1;
1702 emit_reg((opc),(dreg));
1704 emit_rex(0,0,0,(dreg));
1705 *(cd->mcodeptr++) = 0xc1;
1706 emit_reg((opc),(dreg));
1712 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1714 emit_rex(1,0,0,(basereg));
1715 *(cd->mcodeptr++) = 0xd1;
1716 emit_membase(cd, (basereg),(disp),(opc));
1718 emit_rex(1,0,0,(basereg));
1719 *(cd->mcodeptr++) = 0xc1;
1720 emit_membase(cd, (basereg),(disp),(opc));
1726 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1728 emit_rex(0,0,0,(basereg));
1729 *(cd->mcodeptr++) = 0xd1;
1730 emit_membase(cd, (basereg),(disp),(opc));
1732 emit_rex(0,0,0,(basereg));
1733 *(cd->mcodeptr++) = 0xc1;
1734 emit_membase(cd, (basereg),(disp),(opc));
1744 void emit_jmp_imm(codegendata *cd, s8 imm) {
1745 *(cd->mcodeptr++) = 0xe9;
1750 void emit_jmp_reg(codegendata *cd, s8 reg) {
1751 emit_rex(0,0,0,(reg));
1752 *(cd->mcodeptr++) = 0xff;
1757 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1758 *(cd->mcodeptr++) = 0x0f;
1759 *(cd->mcodeptr++) = (0x80 + (opc));
1766 * conditional set and move operations
1769 /* we need the rex byte to get all low bytes */
1770 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1772 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1773 *(cd->mcodeptr++) = 0x0f;
1774 *(cd->mcodeptr++) = (0x90 + (opc));
1779 /* we need the rex byte to get all low bytes */
1780 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1782 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1783 *(cd->mcodeptr++) = 0x0f;
1784 *(cd->mcodeptr++) = (0x90 + (opc));
1785 emit_membase(cd, (basereg),(disp),0);
1789 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1791 emit_rex(1,(dreg),0,(reg));
1792 *(cd->mcodeptr++) = 0x0f;
1793 *(cd->mcodeptr++) = (0x40 + (opc));
1794 emit_reg((dreg),(reg));
1798 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1800 emit_rex(0,(dreg),0,(reg));
1801 *(cd->mcodeptr++) = 0x0f;
1802 *(cd->mcodeptr++) = (0x40 + (opc));
1803 emit_reg((dreg),(reg));
1807 void emit_neg_reg(codegendata *cd, s8 reg)
1809 emit_rex(1,0,0,(reg));
1810 *(cd->mcodeptr++) = 0xf7;
1815 void emit_negl_reg(codegendata *cd, s8 reg)
1817 emit_rex(0,0,0,(reg));
1818 *(cd->mcodeptr++) = 0xf7;
1823 void emit_push_reg(codegendata *cd, s8 reg) {
1824 emit_rex(0,0,0,(reg));
1825 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1829 void emit_push_imm(codegendata *cd, s8 imm) {
1830 *(cd->mcodeptr++) = 0x68;
1835 void emit_pop_reg(codegendata *cd, s8 reg) {
1836 emit_rex(0,0,0,(reg));
1837 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1841 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1842 emit_rex(1,(reg),0,(dreg));
1843 *(cd->mcodeptr++) = 0x87;
1844 emit_reg((reg),(dreg));
1848 void emit_nop(codegendata *cd) {
1849 *(cd->mcodeptr++) = 0x90;
1857 void emit_call_reg(codegendata *cd, s8 reg)
1859 emit_rex(0,0,0,(reg));
1860 *(cd->mcodeptr++) = 0xff;
1865 void emit_call_imm(codegendata *cd, s8 imm)
1867 *(cd->mcodeptr++) = 0xe8;
1872 void emit_call_mem(codegendata *cd, ptrint mem)
1874 *(cd->mcodeptr++) = 0xff;
1881 * floating point instructions (SSE2)
1883 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1884 *(cd->mcodeptr++) = 0xf2;
1885 emit_rex(0,(dreg),0,(reg));
1886 *(cd->mcodeptr++) = 0x0f;
1887 *(cd->mcodeptr++) = 0x58;
1888 emit_reg((dreg),(reg));
1892 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1893 *(cd->mcodeptr++) = 0xf3;
1894 emit_rex(0,(dreg),0,(reg));
1895 *(cd->mcodeptr++) = 0x0f;
1896 *(cd->mcodeptr++) = 0x58;
1897 emit_reg((dreg),(reg));
1901 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1902 *(cd->mcodeptr++) = 0xf3;
1903 emit_rex(1,(dreg),0,(reg));
1904 *(cd->mcodeptr++) = 0x0f;
1905 *(cd->mcodeptr++) = 0x2a;
1906 emit_reg((dreg),(reg));
1910 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1911 *(cd->mcodeptr++) = 0xf3;
1912 emit_rex(0,(dreg),0,(reg));
1913 *(cd->mcodeptr++) = 0x0f;
1914 *(cd->mcodeptr++) = 0x2a;
1915 emit_reg((dreg),(reg));
1919 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1920 *(cd->mcodeptr++) = 0xf2;
1921 emit_rex(1,(dreg),0,(reg));
1922 *(cd->mcodeptr++) = 0x0f;
1923 *(cd->mcodeptr++) = 0x2a;
1924 emit_reg((dreg),(reg));
1928 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1929 *(cd->mcodeptr++) = 0xf2;
1930 emit_rex(0,(dreg),0,(reg));
1931 *(cd->mcodeptr++) = 0x0f;
1932 *(cd->mcodeptr++) = 0x2a;
1933 emit_reg((dreg),(reg));
1937 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1938 *(cd->mcodeptr++) = 0xf3;
1939 emit_rex(0,(dreg),0,(reg));
1940 *(cd->mcodeptr++) = 0x0f;
1941 *(cd->mcodeptr++) = 0x5a;
1942 emit_reg((dreg),(reg));
1946 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1947 *(cd->mcodeptr++) = 0xf2;
1948 emit_rex(0,(dreg),0,(reg));
1949 *(cd->mcodeptr++) = 0x0f;
1950 *(cd->mcodeptr++) = 0x5a;
1951 emit_reg((dreg),(reg));
1955 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1956 *(cd->mcodeptr++) = 0xf3;
1957 emit_rex(1,(dreg),0,(reg));
1958 *(cd->mcodeptr++) = 0x0f;
1959 *(cd->mcodeptr++) = 0x2c;
1960 emit_reg((dreg),(reg));
1964 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1965 *(cd->mcodeptr++) = 0xf3;
1966 emit_rex(0,(dreg),0,(reg));
1967 *(cd->mcodeptr++) = 0x0f;
1968 *(cd->mcodeptr++) = 0x2c;
1969 emit_reg((dreg),(reg));
1973 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1974 *(cd->mcodeptr++) = 0xf2;
1975 emit_rex(1,(dreg),0,(reg));
1976 *(cd->mcodeptr++) = 0x0f;
1977 *(cd->mcodeptr++) = 0x2c;
1978 emit_reg((dreg),(reg));
1982 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1983 *(cd->mcodeptr++) = 0xf2;
1984 emit_rex(0,(dreg),0,(reg));
1985 *(cd->mcodeptr++) = 0x0f;
1986 *(cd->mcodeptr++) = 0x2c;
1987 emit_reg((dreg),(reg));
1991 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1992 *(cd->mcodeptr++) = 0xf3;
1993 emit_rex(0,(dreg),0,(reg));
1994 *(cd->mcodeptr++) = 0x0f;
1995 *(cd->mcodeptr++) = 0x5e;
1996 emit_reg((dreg),(reg));
2000 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2001 *(cd->mcodeptr++) = 0xf2;
2002 emit_rex(0,(dreg),0,(reg));
2003 *(cd->mcodeptr++) = 0x0f;
2004 *(cd->mcodeptr++) = 0x5e;
2005 emit_reg((dreg),(reg));
2009 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2010 *(cd->mcodeptr++) = 0x66;
2011 emit_rex(1,(freg),0,(reg));
2012 *(cd->mcodeptr++) = 0x0f;
2013 *(cd->mcodeptr++) = 0x6e;
2014 emit_reg((freg),(reg));
2018 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2019 *(cd->mcodeptr++) = 0x66;
2020 emit_rex(1,(freg),0,(reg));
2021 *(cd->mcodeptr++) = 0x0f;
2022 *(cd->mcodeptr++) = 0x7e;
2023 emit_reg((freg),(reg));
2027 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2028 *(cd->mcodeptr++) = 0x66;
2029 emit_rex(0,(reg),0,(basereg));
2030 *(cd->mcodeptr++) = 0x0f;
2031 *(cd->mcodeptr++) = 0x7e;
2032 emit_membase(cd, (basereg),(disp),(reg));
2036 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2037 *(cd->mcodeptr++) = 0x66;
2038 emit_rex(0,(reg),(indexreg),(basereg));
2039 *(cd->mcodeptr++) = 0x0f;
2040 *(cd->mcodeptr++) = 0x7e;
2041 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2045 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2046 *(cd->mcodeptr++) = 0x66;
2047 emit_rex(1,(dreg),0,(basereg));
2048 *(cd->mcodeptr++) = 0x0f;
2049 *(cd->mcodeptr++) = 0x6e;
2050 emit_membase(cd, (basereg),(disp),(dreg));
2054 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2055 *(cd->mcodeptr++) = 0x66;
2056 emit_rex(0,(dreg),0,(basereg));
2057 *(cd->mcodeptr++) = 0x0f;
2058 *(cd->mcodeptr++) = 0x6e;
2059 emit_membase(cd, (basereg),(disp),(dreg));
2063 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2064 *(cd->mcodeptr++) = 0x66;
2065 emit_rex(0,(dreg),(indexreg),(basereg));
2066 *(cd->mcodeptr++) = 0x0f;
2067 *(cd->mcodeptr++) = 0x6e;
2068 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2072 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2073 *(cd->mcodeptr++) = 0xf3;
2074 emit_rex(0,(dreg),0,(reg));
2075 *(cd->mcodeptr++) = 0x0f;
2076 *(cd->mcodeptr++) = 0x7e;
2077 emit_reg((dreg),(reg));
2081 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2082 *(cd->mcodeptr++) = 0x66;
2083 emit_rex(0,(reg),0,(basereg));
2084 *(cd->mcodeptr++) = 0x0f;
2085 *(cd->mcodeptr++) = 0xd6;
2086 emit_membase(cd, (basereg),(disp),(reg));
2090 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2091 *(cd->mcodeptr++) = 0xf3;
2092 emit_rex(0,(dreg),0,(basereg));
2093 *(cd->mcodeptr++) = 0x0f;
2094 *(cd->mcodeptr++) = 0x7e;
2095 emit_membase(cd, (basereg),(disp),(dreg));
2099 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2100 *(cd->mcodeptr++) = 0xf3;
2101 emit_rex(0,(reg),0,(dreg));
2102 *(cd->mcodeptr++) = 0x0f;
2103 *(cd->mcodeptr++) = 0x10;
2104 emit_reg((reg),(dreg));
2108 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2109 *(cd->mcodeptr++) = 0xf2;
2110 emit_rex(0,(reg),0,(dreg));
2111 *(cd->mcodeptr++) = 0x0f;
2112 *(cd->mcodeptr++) = 0x10;
2113 emit_reg((reg),(dreg));
2117 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2118 *(cd->mcodeptr++) = 0xf3;
2119 emit_rex(0,(reg),0,(basereg));
2120 *(cd->mcodeptr++) = 0x0f;
2121 *(cd->mcodeptr++) = 0x11;
2122 emit_membase(cd, (basereg),(disp),(reg));
2126 /* Always emit a REX byte, because the instruction size can be smaller when */
2127 /* all register indexes are smaller than 7. */
2128 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2129 *(cd->mcodeptr++) = 0xf3;
2130 emit_byte_rex((reg),0,(basereg));
2131 *(cd->mcodeptr++) = 0x0f;
2132 *(cd->mcodeptr++) = 0x11;
2133 emit_membase32(cd, (basereg),(disp),(reg));
2137 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2138 *(cd->mcodeptr++) = 0xf2;
2139 emit_rex(0,(reg),0,(basereg));
2140 *(cd->mcodeptr++) = 0x0f;
2141 *(cd->mcodeptr++) = 0x11;
2142 emit_membase(cd, (basereg),(disp),(reg));
2146 /* Always emit a REX byte, because the instruction size can be smaller when */
2147 /* all register indexes are smaller than 7. */
2148 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2149 *(cd->mcodeptr++) = 0xf2;
2150 emit_byte_rex((reg),0,(basereg));
2151 *(cd->mcodeptr++) = 0x0f;
2152 *(cd->mcodeptr++) = 0x11;
2153 emit_membase32(cd, (basereg),(disp),(reg));
2157 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2158 *(cd->mcodeptr++) = 0xf3;
2159 emit_rex(0,(dreg),0,(basereg));
2160 *(cd->mcodeptr++) = 0x0f;
2161 *(cd->mcodeptr++) = 0x10;
2162 emit_membase(cd, (basereg),(disp),(dreg));
2166 /* Always emit a REX byte, because the instruction size can be smaller when */
2167 /* all register indexes are smaller than 7. */
2168 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2169 *(cd->mcodeptr++) = 0xf3;
2170 emit_byte_rex((dreg),0,(basereg));
2171 *(cd->mcodeptr++) = 0x0f;
2172 *(cd->mcodeptr++) = 0x10;
2173 emit_membase32(cd, (basereg),(disp),(dreg));
2177 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2179 emit_rex(0,(dreg),0,(basereg));
2180 *(cd->mcodeptr++) = 0x0f;
2181 *(cd->mcodeptr++) = 0x12;
2182 emit_membase(cd, (basereg),(disp),(dreg));
2186 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2188 emit_rex(0,(reg),0,(basereg));
2189 *(cd->mcodeptr++) = 0x0f;
2190 *(cd->mcodeptr++) = 0x13;
2191 emit_membase(cd, (basereg),(disp),(reg));
2195 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2196 *(cd->mcodeptr++) = 0xf2;
2197 emit_rex(0,(dreg),0,(basereg));
2198 *(cd->mcodeptr++) = 0x0f;
2199 *(cd->mcodeptr++) = 0x10;
2200 emit_membase(cd, (basereg),(disp),(dreg));
2204 /* Always emit a REX byte, because the instruction size can be smaller when */
2205 /* all register indexes are smaller than 7. */
2206 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2207 *(cd->mcodeptr++) = 0xf2;
2208 emit_byte_rex((dreg),0,(basereg));
2209 *(cd->mcodeptr++) = 0x0f;
2210 *(cd->mcodeptr++) = 0x10;
2211 emit_membase32(cd, (basereg),(disp),(dreg));
2215 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2217 *(cd->mcodeptr++) = 0x66;
2218 emit_rex(0,(dreg),0,(basereg));
2219 *(cd->mcodeptr++) = 0x0f;
2220 *(cd->mcodeptr++) = 0x12;
2221 emit_membase(cd, (basereg),(disp),(dreg));
2225 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2227 *(cd->mcodeptr++) = 0x66;
2228 emit_rex(0,(reg),0,(basereg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x13;
2231 emit_membase(cd, (basereg),(disp),(reg));
2235 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2236 *(cd->mcodeptr++) = 0xf3;
2237 emit_rex(0,(reg),(indexreg),(basereg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x11;
2240 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2244 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2245 *(cd->mcodeptr++) = 0xf2;
2246 emit_rex(0,(reg),(indexreg),(basereg));
2247 *(cd->mcodeptr++) = 0x0f;
2248 *(cd->mcodeptr++) = 0x11;
2249 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2253 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2254 *(cd->mcodeptr++) = 0xf3;
2255 emit_rex(0,(dreg),(indexreg),(basereg));
2256 *(cd->mcodeptr++) = 0x0f;
2257 *(cd->mcodeptr++) = 0x10;
2258 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2262 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2263 *(cd->mcodeptr++) = 0xf2;
2264 emit_rex(0,(dreg),(indexreg),(basereg));
2265 *(cd->mcodeptr++) = 0x0f;
2266 *(cd->mcodeptr++) = 0x10;
2267 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2271 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2272 *(cd->mcodeptr++) = 0xf3;
2273 emit_rex(0,(dreg),0,(reg));
2274 *(cd->mcodeptr++) = 0x0f;
2275 *(cd->mcodeptr++) = 0x59;
2276 emit_reg((dreg),(reg));
2280 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2281 *(cd->mcodeptr++) = 0xf2;
2282 emit_rex(0,(dreg),0,(reg));
2283 *(cd->mcodeptr++) = 0x0f;
2284 *(cd->mcodeptr++) = 0x59;
2285 emit_reg((dreg),(reg));
2289 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2290 *(cd->mcodeptr++) = 0xf3;
2291 emit_rex(0,(dreg),0,(reg));
2292 *(cd->mcodeptr++) = 0x0f;
2293 *(cd->mcodeptr++) = 0x5c;
2294 emit_reg((dreg),(reg));
2298 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2299 *(cd->mcodeptr++) = 0xf2;
2300 emit_rex(0,(dreg),0,(reg));
2301 *(cd->mcodeptr++) = 0x0f;
2302 *(cd->mcodeptr++) = 0x5c;
2303 emit_reg((dreg),(reg));
2307 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2308 emit_rex(0,(dreg),0,(reg));
2309 *(cd->mcodeptr++) = 0x0f;
2310 *(cd->mcodeptr++) = 0x2e;
2311 emit_reg((dreg),(reg));
2315 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2316 *(cd->mcodeptr++) = 0x66;
2317 emit_rex(0,(dreg),0,(reg));
2318 *(cd->mcodeptr++) = 0x0f;
2319 *(cd->mcodeptr++) = 0x2e;
2320 emit_reg((dreg),(reg));
2324 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2325 emit_rex(0,(dreg),0,(reg));
2326 *(cd->mcodeptr++) = 0x0f;
2327 *(cd->mcodeptr++) = 0x57;
2328 emit_reg((dreg),(reg));
2332 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2333 emit_rex(0,(dreg),0,(basereg));
2334 *(cd->mcodeptr++) = 0x0f;
2335 *(cd->mcodeptr++) = 0x57;
2336 emit_membase(cd, (basereg),(disp),(dreg));
2340 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2341 *(cd->mcodeptr++) = 0x66;
2342 emit_rex(0,(dreg),0,(reg));
2343 *(cd->mcodeptr++) = 0x0f;
2344 *(cd->mcodeptr++) = 0x57;
2345 emit_reg((dreg),(reg));
2349 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2350 *(cd->mcodeptr++) = 0x66;
2351 emit_rex(0,(dreg),0,(basereg));
2352 *(cd->mcodeptr++) = 0x0f;
2353 *(cd->mcodeptr++) = 0x57;
2354 emit_membase(cd, (basereg),(disp),(dreg));
2358 /* system instructions ********************************************************/
2360 void emit_rdtsc(codegendata *cd)
2362 *(cd->mcodeptr++) = 0x0f;
2363 *(cd->mcodeptr++) = 0x31;
2368 * These are local overrides for various environment variables in Emacs.
2369 * Please do not remove this and leave it at the end of the file, where
2370 * Emacs will automagically detect them.
2371 * ---------------------------------------------------------------------
2374 * indent-tabs-mode: t