1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/exceptions.h"
44 #include "vm/jit/abi.h"
45 #include "vm/jit/abi-asm.h"
46 #include "vm/jit/asmpart.h"
47 #include "vm/jit/codegen-common.h"
48 #include "vm/jit/emit-common.h"
49 #include "vm/jit/jit.h"
50 #include "vm/jit/patcher-common.h"
51 #include "vm/jit/replace.h"
52 #include "vm/jit/trace.h"
54 #include "vmcore/options.h"
57 /* emit_load *******************************************************************
59 Emits a possible load of an operand.
61 *******************************************************************************/
63 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
69 /* get required compiler data */
73 if (IS_INMEMORY(src->flags)) {
76 disp = src->vv.regoff;
80 M_ILD(tempreg, REG_SP, disp);
84 M_LLD(tempreg, REG_SP, disp);
87 M_FLD(tempreg, REG_SP, disp);
90 M_DLD(tempreg, REG_SP, disp);
93 vm_abort("emit_load: unknown type %d", src->type);
105 /* emit_store ******************************************************************
107 This function generates the code to store the result of an
108 operation back into a spilled pseudo-variable. If the
109 pseudo-variable has not been spilled in the first place, this
110 function will generate nothing.
112 *******************************************************************************/
114 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
123 /* get required compiler data */
128 /* do we have to generate a conditional move? */
130 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
131 /* the passed register d is actually the source register */
135 /* Only pass the opcode to codegen_reg_of_var to get the real
136 destination register. */
138 opcode = iptr->opc & ICMD_OPCODE_MASK;
140 /* get the real destination register */
142 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
144 /* and emit the conditional move */
146 emit_cmovxx(cd, iptr, s, d);
150 if (IS_INMEMORY(dst->flags)) {
153 disp = dst->vv.regoff;
159 M_LST(d, REG_SP, disp);
162 M_FST(d, REG_SP, disp);
165 M_DST(d, REG_SP, disp);
168 vm_abort("emit_store: unknown type %d", dst->type);
174 /* emit_copy *******************************************************************
176 Generates a register/memory to register/memory copy.
178 *******************************************************************************/
180 void emit_copy(jitdata *jd, instruction *iptr)
187 /* get required compiler data */
191 /* get source and destination variables */
193 src = VAROP(iptr->s1);
194 dst = VAROP(iptr->dst);
196 if ((src->vv.regoff != dst->vv.regoff) ||
197 ((src->flags ^ dst->flags) & INMEMORY)) {
199 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
200 /* emit nothing, as the value won't be used anyway */
204 /* If one of the variables resides in memory, we can eliminate
205 the register move from/to the temporary register with the
206 order of getting the destination register and the load. */
208 if (IS_INMEMORY(src->flags)) {
209 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
210 s1 = emit_load(jd, iptr, src, d);
213 s1 = emit_load(jd, iptr, src, REG_IFTMP);
214 d = codegen_reg_of_var(iptr->opc, dst, s1);
229 vm_abort("emit_copy: unknown type %d", src->type);
233 emit_store(jd, iptr, dst, d);
238 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
241 switch (iptr->flags.fields.condition) {
265 /* emit_branch *****************************************************************
267 Emits the code for conditional and unconditional branchs.
269 *******************************************************************************/
271 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
275 /* NOTE: A displacement overflow cannot happen. */
277 /* check which branch to generate */
279 if (condition == BRANCH_UNCONDITIONAL) {
281 /* calculate the different displacements */
283 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
285 M_JMP_IMM(branchdisp);
288 /* calculate the different displacements */
290 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
324 vm_abort("emit_branch: unknown condition %d", condition);
330 /* emit_arithmetic_check *******************************************************
332 Emit an ArithmeticException check.
334 *******************************************************************************/
336 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
338 if (INSTRUCTION_MUST_CHECK(iptr)) {
341 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
346 /* emit_arrayindexoutofbounds_check ********************************************
348 Emit a ArrayIndexOutOfBoundsException check.
350 *******************************************************************************/
352 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
354 if (INSTRUCTION_MUST_CHECK(iptr)) {
355 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
356 M_ICMP(REG_ITMP3, s2);
358 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
363 /* emit_arraystore_check *******************************************************
365 Emit an ArrayStoreException check.
367 *******************************************************************************/
369 void emit_arraystore_check(codegendata *cd, instruction *iptr)
371 if (INSTRUCTION_MUST_CHECK(iptr)) {
374 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_ARRAYSTORE);
379 /* emit_classcast_check ********************************************************
381 Emit a ClassCastException check.
383 *******************************************************************************/
385 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
387 if (INSTRUCTION_MUST_CHECK(iptr)) {
399 vm_abort("emit_classcast_check: unknown condition %d", condition);
401 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
406 /* emit_nullpointer_check ******************************************************
408 Emit a NullPointerException check.
410 *******************************************************************************/
412 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
414 if (INSTRUCTION_MUST_CHECK(iptr)) {
417 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
422 /* emit_exception_check ********************************************************
424 Emit an Exception check.
426 *******************************************************************************/
428 void emit_exception_check(codegendata *cd, instruction *iptr)
430 if (INSTRUCTION_MUST_CHECK(iptr)) {
433 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
438 /* emit_trap_compiler **********************************************************
440 Emit a trap instruction which calls the JIT compiler.
442 *******************************************************************************/
444 void emit_trap_compiler(codegendata *cd)
446 M_ALD_MEM(REG_METHODPTR, EXCEPTION_HARDWARE_COMPILER);
450 /* emit_trap *******************************************************************
452 Emit a trap instruction and return the original machine code.
454 *******************************************************************************/
456 uint32_t emit_trap(codegendata *cd)
460 /* Get machine code which is patched back in later. The trap is 2
463 mcode = *((uint16_t *) cd->mcodeptr);
465 /* XXX This needs to be change to INT3 when the debugging problems
466 with gdb are resolved. */
474 /* emit_verbosecall_enter ******************************************************
476 Generates the code for the call trace.
478 *******************************************************************************/
481 void emit_verbosecall_enter(jitdata *jd)
491 /* get required compiler data */
500 /* mark trace code */
504 /* keep 16-byte stack alignment */
506 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
507 ALIGN_2(stackframesize);
509 M_LSUB_IMM(stackframesize * 8, REG_SP);
511 /* save argument registers */
513 for (i = 0; i < md->paramcount; i++) {
514 if (!md->params[i].inmemory) {
515 s = md->params[i].regoff;
517 switch (md->paramtypes[i].type) {
521 M_LST(s, REG_SP, i * 8);
525 M_DST(s, REG_SP, i * 8);
531 /* save all argument and temporary registers for leaf methods */
533 if (code_is_leafmethod(code)) {
534 for (i = 0; i < INT_ARG_CNT; i++)
535 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
537 for (i = 0; i < FLT_ARG_CNT; i++)
538 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
540 for (i = 0; i < INT_TMP_CNT; i++)
541 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
543 for (i = 0; i < FLT_TMP_CNT; i++)
544 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
547 M_MOV_IMM(m, REG_A0);
548 M_MOV(REG_SP, REG_A1);
549 M_MOV(REG_SP, REG_A2);
550 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
551 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
554 /* restore argument registers */
556 for (i = 0; i < md->paramcount; i++) {
557 if (!md->params[i].inmemory) {
558 s = md->params[i].regoff;
560 switch (md->paramtypes[i].type) {
564 M_LLD(s, REG_SP, i * 8);
568 M_DLD(s, REG_SP, i * 8);
575 /* restore all argument and temporary registers for leaf methods */
577 if (code_is_leafmethod(code)) {
578 for (i = 0; i < INT_ARG_CNT; i++)
579 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
581 for (i = 0; i < FLT_ARG_CNT; i++)
582 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
584 for (i = 0; i < INT_TMP_CNT; i++)
585 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
587 for (i = 0; i < FLT_TMP_CNT; i++)
588 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
591 M_LADD_IMM(stackframesize * 8, REG_SP);
593 /* mark trace code */
597 #endif /* !defined(NDEBUG) */
600 /* emit_verbosecall_exit *******************************************************
602 Generates the code for the call trace.
604 *******************************************************************************/
607 void emit_verbosecall_exit(jitdata *jd)
614 /* get required compiler data */
622 /* mark trace code */
626 /* keep 16-byte stack alignment */
628 M_ASUB_IMM(2 * 8, REG_SP);
630 /* save return value */
632 switch (md->returntype.type) {
636 M_LST(REG_RESULT, REG_SP, 0 * 8);
640 M_DST(REG_FRESULT, REG_SP, 0 * 8);
644 M_MOV_IMM(m, REG_A0);
645 M_MOV(REG_SP, REG_A1);
647 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
650 /* restore return value */
652 switch (md->returntype.type) {
656 M_LLD(REG_RESULT, REG_SP, 0 * 8);
660 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
664 M_AADD_IMM(2 * 8, REG_SP);
666 /* mark trace code */
670 #endif /* !defined(NDEBUG) */
673 /* code generation functions **************************************************/
675 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
677 if ((basereg == REG_SP) || (basereg == R12)) {
679 emit_address_byte(0, dreg, REG_SP);
680 emit_address_byte(0, REG_SP, REG_SP);
682 } else if (IS_IMM8(disp)) {
683 emit_address_byte(1, dreg, REG_SP);
684 emit_address_byte(0, REG_SP, REG_SP);
688 emit_address_byte(2, dreg, REG_SP);
689 emit_address_byte(0, REG_SP, REG_SP);
693 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
694 emit_address_byte(0,(dreg),(basereg));
696 } else if ((basereg) == RIP) {
697 emit_address_byte(0, dreg, RBP);
702 emit_address_byte(1, dreg, basereg);
706 emit_address_byte(2, dreg, basereg);
713 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
715 if ((basereg == REG_SP) || (basereg == R12)) {
716 emit_address_byte(2, dreg, REG_SP);
717 emit_address_byte(0, REG_SP, REG_SP);
721 emit_address_byte(2, dreg, basereg);
727 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
730 emit_address_byte(0, reg, 4);
731 emit_address_byte(scale, indexreg, 5);
734 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
735 emit_address_byte(0, reg, 4);
736 emit_address_byte(scale, indexreg, basereg);
738 else if (IS_IMM8(disp)) {
739 emit_address_byte(1, reg, 4);
740 emit_address_byte(scale, indexreg, basereg);
744 emit_address_byte(2, reg, 4);
745 emit_address_byte(scale, indexreg, basereg);
751 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
754 varinfo *v_s1,*v_s2,*v_dst;
757 /* get required compiler data */
761 v_s1 = VAROP(iptr->s1);
762 v_s2 = VAROP(iptr->sx.s23.s2);
763 v_dst = VAROP(iptr->dst);
765 s1 = v_s1->vv.regoff;
766 s2 = v_s2->vv.regoff;
767 d = v_dst->vv.regoff;
769 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
771 if (IS_INMEMORY(v_dst->flags)) {
772 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
774 M_ILD(RCX, REG_SP, s2);
775 emit_shiftl_membase(cd, shift_op, REG_SP, d);
778 M_ILD(RCX, REG_SP, s2);
779 M_ILD(REG_ITMP2, REG_SP, s1);
780 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
781 M_IST(REG_ITMP2, REG_SP, d);
784 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
785 /* s1 may be equal to RCX */
788 M_ILD(REG_ITMP1, REG_SP, s2);
789 M_IST(s1, REG_SP, d);
790 M_INTMOVE(REG_ITMP1, RCX);
793 M_IST(s1, REG_SP, d);
794 M_ILD(RCX, REG_SP, s2);
798 M_ILD(RCX, REG_SP, s2);
799 M_IST(s1, REG_SP, d);
802 emit_shiftl_membase(cd, shift_op, REG_SP, d);
804 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
807 emit_shiftl_membase(cd, shift_op, REG_SP, d);
811 M_ILD(REG_ITMP2, REG_SP, s1);
812 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
813 M_IST(REG_ITMP2, REG_SP, d);
817 /* s1 may be equal to RCX */
818 M_IST(s1, REG_SP, d);
820 emit_shiftl_membase(cd, shift_op, REG_SP, d);
823 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
831 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
832 M_ILD(RCX, REG_SP, s2);
833 M_ILD(d, REG_SP, s1);
834 emit_shiftl_reg(cd, shift_op, d);
836 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
837 /* s1 may be equal to RCX */
839 M_ILD(RCX, REG_SP, s2);
840 emit_shiftl_reg(cd, shift_op, d);
842 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
844 M_ILD(d, REG_SP, s1);
845 emit_shiftl_reg(cd, shift_op, d);
848 /* s1 may be equal to RCX */
851 /* d cannot be used to backup s1 since this would
853 M_INTMOVE(s1, REG_ITMP3);
855 M_INTMOVE(REG_ITMP3, d);
863 /* d may be equal to s2 */
867 emit_shiftl_reg(cd, shift_op, d);
871 M_INTMOVE(REG_ITMP3, RCX);
873 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
878 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
881 varinfo *v_s1,*v_s2,*v_dst;
884 /* get required compiler data */
888 v_s1 = VAROP(iptr->s1);
889 v_s2 = VAROP(iptr->sx.s23.s2);
890 v_dst = VAROP(iptr->dst);
892 s1 = v_s1->vv.regoff;
893 s2 = v_s2->vv.regoff;
894 d = v_dst->vv.regoff;
896 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
898 if (IS_INMEMORY(v_dst->flags)) {
899 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
901 M_ILD(RCX, REG_SP, s2);
902 emit_shift_membase(cd, shift_op, REG_SP, d);
905 M_ILD(RCX, REG_SP, s2);
906 M_LLD(REG_ITMP2, REG_SP, s1);
907 emit_shift_reg(cd, shift_op, REG_ITMP2);
908 M_LST(REG_ITMP2, REG_SP, d);
911 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
912 /* s1 may be equal to RCX */
915 M_ILD(REG_ITMP1, REG_SP, s2);
916 M_LST(s1, REG_SP, d);
917 M_INTMOVE(REG_ITMP1, RCX);
920 M_LST(s1, REG_SP, d);
921 M_ILD(RCX, REG_SP, s2);
925 M_ILD(RCX, REG_SP, s2);
926 M_LST(s1, REG_SP, d);
929 emit_shift_membase(cd, shift_op, REG_SP, d);
931 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
934 emit_shift_membase(cd, shift_op, REG_SP, d);
938 M_LLD(REG_ITMP2, REG_SP, s1);
939 emit_shift_reg(cd, shift_op, REG_ITMP2);
940 M_LST(REG_ITMP2, REG_SP, d);
944 /* s1 may be equal to RCX */
945 M_LST(s1, REG_SP, d);
947 emit_shift_membase(cd, shift_op, REG_SP, d);
950 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
958 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
959 M_ILD(RCX, REG_SP, s2);
960 M_LLD(d, REG_SP, s1);
961 emit_shift_reg(cd, shift_op, d);
963 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
964 /* s1 may be equal to RCX */
966 M_ILD(RCX, REG_SP, s2);
967 emit_shift_reg(cd, shift_op, d);
969 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
971 M_LLD(d, REG_SP, s1);
972 emit_shift_reg(cd, shift_op, d);
975 /* s1 may be equal to RCX */
978 /* d cannot be used to backup s1 since this would
980 M_INTMOVE(s1, REG_ITMP3);
982 M_INTMOVE(REG_ITMP3, d);
990 /* d may be equal to s2 */
994 emit_shift_reg(cd, shift_op, d);
998 M_INTMOVE(REG_ITMP3, RCX);
1000 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1005 /* low-level code emitter functions *******************************************/
1007 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1009 emit_rex(1,(reg),0,(dreg));
1010 *(cd->mcodeptr++) = 0x89;
1011 emit_reg((reg),(dreg));
1015 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1017 emit_rex(1,0,0,(reg));
1018 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1023 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1025 emit_rex(0,(reg),0,(dreg));
1026 *(cd->mcodeptr++) = 0x89;
1027 emit_reg((reg),(dreg));
1031 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1032 emit_rex(0,0,0,(reg));
1033 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1038 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1039 emit_rex(1,(reg),0,(basereg));
1040 *(cd->mcodeptr++) = 0x8b;
1041 emit_membase(cd, (basereg),(disp),(reg));
1046 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1047 * constant membase immediate length of 32bit
1049 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1050 emit_rex(1,(reg),0,(basereg));
1051 *(cd->mcodeptr++) = 0x8b;
1052 emit_membase32(cd, (basereg),(disp),(reg));
1056 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1058 emit_rex(0,(reg),0,(basereg));
1059 *(cd->mcodeptr++) = 0x8b;
1060 emit_membase(cd, (basereg),(disp),(reg));
1064 /* ATTENTION: Always emit a REX byte, because the instruction size can
1065 be smaller when all register indexes are smaller than 7. */
1066 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1068 emit_byte_rex((reg),0,(basereg));
1069 *(cd->mcodeptr++) = 0x8b;
1070 emit_membase32(cd, (basereg),(disp),(reg));
1074 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1075 emit_rex(1,(reg),0,(basereg));
1076 *(cd->mcodeptr++) = 0x89;
1077 emit_membase(cd, (basereg),(disp),(reg));
1081 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1082 emit_rex(1,(reg),0,(basereg));
1083 *(cd->mcodeptr++) = 0x89;
1084 emit_membase32(cd, (basereg),(disp),(reg));
1088 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1089 emit_rex(0,(reg),0,(basereg));
1090 *(cd->mcodeptr++) = 0x89;
1091 emit_membase(cd, (basereg),(disp),(reg));
1095 /* Always emit a REX byte, because the instruction size can be smaller when */
1096 /* all register indexes are smaller than 7. */
1097 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1098 emit_byte_rex((reg),0,(basereg));
1099 *(cd->mcodeptr++) = 0x89;
1100 emit_membase32(cd, (basereg),(disp),(reg));
1104 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1105 emit_rex(1,(reg),(indexreg),(basereg));
1106 *(cd->mcodeptr++) = 0x8b;
1107 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1111 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1112 emit_rex(0,(reg),(indexreg),(basereg));
1113 *(cd->mcodeptr++) = 0x8b;
1114 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1118 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1119 emit_rex(1,(reg),(indexreg),(basereg));
1120 *(cd->mcodeptr++) = 0x89;
1121 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1125 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1126 emit_rex(0,(reg),(indexreg),(basereg));
1127 *(cd->mcodeptr++) = 0x89;
1128 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1132 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1133 *(cd->mcodeptr++) = 0x66;
1134 emit_rex(0,(reg),(indexreg),(basereg));
1135 *(cd->mcodeptr++) = 0x89;
1136 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1140 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1141 emit_byte_rex((reg),(indexreg),(basereg));
1142 *(cd->mcodeptr++) = 0x88;
1143 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1147 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1148 emit_rex(1,0,0,(basereg));
1149 *(cd->mcodeptr++) = 0xc7;
1150 emit_membase(cd, (basereg),(disp),0);
1155 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1156 emit_rex(1,0,0,(basereg));
1157 *(cd->mcodeptr++) = 0xc7;
1158 emit_membase32(cd, (basereg),(disp),0);
1163 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1164 emit_rex(0,0,0,(basereg));
1165 *(cd->mcodeptr++) = 0xc7;
1166 emit_membase(cd, (basereg),(disp),0);
1171 /* Always emit a REX byte, because the instruction size can be smaller when */
1172 /* all register indexes are smaller than 7. */
1173 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1174 emit_byte_rex(0,0,(basereg));
1175 *(cd->mcodeptr++) = 0xc7;
1176 emit_membase32(cd, (basereg),(disp),0);
1181 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1183 emit_rex(1,(dreg),0,(reg));
1184 *(cd->mcodeptr++) = 0x0f;
1185 *(cd->mcodeptr++) = 0xbe;
1186 /* XXX: why do reg and dreg have to be exchanged */
1187 emit_reg((dreg),(reg));
1191 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1193 emit_rex(1,(dreg),0,(reg));
1194 *(cd->mcodeptr++) = 0x0f;
1195 *(cd->mcodeptr++) = 0xbf;
1196 /* XXX: why do reg and dreg have to be exchanged */
1197 emit_reg((dreg),(reg));
1201 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1203 emit_rex(1,(dreg),0,(reg));
1204 *(cd->mcodeptr++) = 0x63;
1205 /* XXX: why do reg and dreg have to be exchanged */
1206 emit_reg((dreg),(reg));
1210 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1212 emit_rex(1,(dreg),0,(reg));
1213 *(cd->mcodeptr++) = 0x0f;
1214 *(cd->mcodeptr++) = 0xb7;
1215 /* XXX: why do reg and dreg have to be exchanged */
1216 emit_reg((dreg),(reg));
1220 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1221 emit_rex(1,(reg),(indexreg),(basereg));
1222 *(cd->mcodeptr++) = 0x0f;
1223 *(cd->mcodeptr++) = 0xbf;
1224 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1228 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1229 emit_rex(1,(reg),(indexreg),(basereg));
1230 *(cd->mcodeptr++) = 0x0f;
1231 *(cd->mcodeptr++) = 0xbe;
1232 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1236 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1237 emit_rex(1,(reg),(indexreg),(basereg));
1238 *(cd->mcodeptr++) = 0x0f;
1239 *(cd->mcodeptr++) = 0xb7;
1240 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1244 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1246 emit_rex(1,0,(indexreg),(basereg));
1247 *(cd->mcodeptr++) = 0xc7;
1248 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1253 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1255 emit_rex(0,0,(indexreg),(basereg));
1256 *(cd->mcodeptr++) = 0xc7;
1257 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1262 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1264 *(cd->mcodeptr++) = 0x66;
1265 emit_rex(0,0,(indexreg),(basereg));
1266 *(cd->mcodeptr++) = 0xc7;
1267 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1272 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1274 emit_rex(0,0,(indexreg),(basereg));
1275 *(cd->mcodeptr++) = 0xc6;
1276 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1281 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1283 emit_rex(1, dreg, 0, 0);
1284 *(cd->mcodeptr++) = 0x8b;
1285 emit_address_byte(0, dreg, 4);
1293 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1295 emit_rex(1,(reg),0,(dreg));
1296 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1297 emit_reg((reg),(dreg));
1301 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1303 emit_rex(0,(reg),0,(dreg));
1304 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1305 emit_reg((reg),(dreg));
1309 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1311 emit_rex(1,(reg),0,(basereg));
1312 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1313 emit_membase(cd, (basereg),(disp),(reg));
1317 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1319 emit_rex(0,(reg),0,(basereg));
1320 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1321 emit_membase(cd, (basereg),(disp),(reg));
1325 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1327 emit_rex(1,(reg),0,(basereg));
1328 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1329 emit_membase(cd, (basereg),(disp),(reg));
1333 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1335 emit_rex(0,(reg),0,(basereg));
1336 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1337 emit_membase(cd, (basereg),(disp),(reg));
1341 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1343 emit_rex(1,0,0,(dreg));
1344 *(cd->mcodeptr++) = 0x83;
1345 emit_reg((opc),(dreg));
1348 emit_rex(1,0,0,(dreg));
1349 *(cd->mcodeptr++) = 0x81;
1350 emit_reg((opc),(dreg));
1356 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1358 emit_rex(1,0,0,(dreg));
1359 *(cd->mcodeptr++) = 0x81;
1360 emit_reg((opc),(dreg));
1365 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1367 emit_rex(0,0,0,(dreg));
1368 *(cd->mcodeptr++) = 0x81;
1369 emit_reg((opc),(dreg));
1374 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1376 emit_rex(0,0,0,(dreg));
1377 *(cd->mcodeptr++) = 0x83;
1378 emit_reg((opc),(dreg));
1381 emit_rex(0,0,0,(dreg));
1382 *(cd->mcodeptr++) = 0x81;
1383 emit_reg((opc),(dreg));
1389 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1391 emit_rex(1,(basereg),0,0);
1392 *(cd->mcodeptr++) = 0x83;
1393 emit_membase(cd, (basereg),(disp),(opc));
1396 emit_rex(1,(basereg),0,0);
1397 *(cd->mcodeptr++) = 0x81;
1398 emit_membase(cd, (basereg),(disp),(opc));
1404 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1406 emit_rex(0,(basereg),0,0);
1407 *(cd->mcodeptr++) = 0x83;
1408 emit_membase(cd, (basereg),(disp),(opc));
1411 emit_rex(0,(basereg),0,0);
1412 *(cd->mcodeptr++) = 0x81;
1413 emit_membase(cd, (basereg),(disp),(opc));
1419 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1420 emit_rex(1,(reg),0,(dreg));
1421 *(cd->mcodeptr++) = 0x85;
1422 emit_reg((reg),(dreg));
1426 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1427 emit_rex(0,(reg),0,(dreg));
1428 *(cd->mcodeptr++) = 0x85;
1429 emit_reg((reg),(dreg));
1433 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1434 *(cd->mcodeptr++) = 0xf7;
1440 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1441 *(cd->mcodeptr++) = 0x66;
1442 *(cd->mcodeptr++) = 0xf7;
1448 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1449 *(cd->mcodeptr++) = 0xf6;
1455 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1456 emit_rex(1,(reg),0,(basereg));
1457 *(cd->mcodeptr++) = 0x8d;
1458 emit_membase(cd, (basereg),(disp),(reg));
1462 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1463 emit_rex(0,(reg),0,(basereg));
1464 *(cd->mcodeptr++) = 0x8d;
1465 emit_membase(cd, (basereg),(disp),(reg));
1470 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1472 emit_rex(0,0,0,(basereg));
1473 *(cd->mcodeptr++) = 0xff;
1474 emit_membase(cd, (basereg),(disp),0);
1479 void emit_cltd(codegendata *cd) {
1480 *(cd->mcodeptr++) = 0x99;
1484 void emit_cqto(codegendata *cd) {
1486 *(cd->mcodeptr++) = 0x99;
1491 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1492 emit_rex(1,(dreg),0,(reg));
1493 *(cd->mcodeptr++) = 0x0f;
1494 *(cd->mcodeptr++) = 0xaf;
1495 emit_reg((dreg),(reg));
1499 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1500 emit_rex(0,(dreg),0,(reg));
1501 *(cd->mcodeptr++) = 0x0f;
1502 *(cd->mcodeptr++) = 0xaf;
1503 emit_reg((dreg),(reg));
1507 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1508 emit_rex(1,(dreg),0,(basereg));
1509 *(cd->mcodeptr++) = 0x0f;
1510 *(cd->mcodeptr++) = 0xaf;
1511 emit_membase(cd, (basereg),(disp),(dreg));
1515 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1516 emit_rex(0,(dreg),0,(basereg));
1517 *(cd->mcodeptr++) = 0x0f;
1518 *(cd->mcodeptr++) = 0xaf;
1519 emit_membase(cd, (basereg),(disp),(dreg));
1523 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1524 if (IS_IMM8((imm))) {
1525 emit_rex(1,0,0,(dreg));
1526 *(cd->mcodeptr++) = 0x6b;
1530 emit_rex(1,0,0,(dreg));
1531 *(cd->mcodeptr++) = 0x69;
1538 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1539 if (IS_IMM8((imm))) {
1540 emit_rex(1,(dreg),0,(reg));
1541 *(cd->mcodeptr++) = 0x6b;
1542 emit_reg((dreg),(reg));
1545 emit_rex(1,(dreg),0,(reg));
1546 *(cd->mcodeptr++) = 0x69;
1547 emit_reg((dreg),(reg));
1553 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1554 if (IS_IMM8((imm))) {
1555 emit_rex(0,(dreg),0,(reg));
1556 *(cd->mcodeptr++) = 0x6b;
1557 emit_reg((dreg),(reg));
1560 emit_rex(0,(dreg),0,(reg));
1561 *(cd->mcodeptr++) = 0x69;
1562 emit_reg((dreg),(reg));
1568 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1569 if (IS_IMM8((imm))) {
1570 emit_rex(1,(dreg),0,(basereg));
1571 *(cd->mcodeptr++) = 0x6b;
1572 emit_membase(cd, (basereg),(disp),(dreg));
1575 emit_rex(1,(dreg),0,(basereg));
1576 *(cd->mcodeptr++) = 0x69;
1577 emit_membase(cd, (basereg),(disp),(dreg));
1583 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1584 if (IS_IMM8((imm))) {
1585 emit_rex(0,(dreg),0,(basereg));
1586 *(cd->mcodeptr++) = 0x6b;
1587 emit_membase(cd, (basereg),(disp),(dreg));
1590 emit_rex(0,(dreg),0,(basereg));
1591 *(cd->mcodeptr++) = 0x69;
1592 emit_membase(cd, (basereg),(disp),(dreg));
1598 void emit_idiv_reg(codegendata *cd, s8 reg) {
1599 emit_rex(1,0,0,(reg));
1600 *(cd->mcodeptr++) = 0xf7;
1605 void emit_idivl_reg(codegendata *cd, s8 reg) {
1606 emit_rex(0,0,0,(reg));
1607 *(cd->mcodeptr++) = 0xf7;
1616 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1617 emit_rex(1,0,0,(reg));
1618 *(cd->mcodeptr++) = 0xd3;
1619 emit_reg((opc),(reg));
1623 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1624 emit_rex(0,0,0,(reg));
1625 *(cd->mcodeptr++) = 0xd3;
1626 emit_reg((opc),(reg));
1630 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1631 emit_rex(1,0,0,(basereg));
1632 *(cd->mcodeptr++) = 0xd3;
1633 emit_membase(cd, (basereg),(disp),(opc));
1637 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1638 emit_rex(0,0,0,(basereg));
1639 *(cd->mcodeptr++) = 0xd3;
1640 emit_membase(cd, (basereg),(disp),(opc));
1644 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1646 emit_rex(1,0,0,(dreg));
1647 *(cd->mcodeptr++) = 0xd1;
1648 emit_reg((opc),(dreg));
1650 emit_rex(1,0,0,(dreg));
1651 *(cd->mcodeptr++) = 0xc1;
1652 emit_reg((opc),(dreg));
1658 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1660 emit_rex(0,0,0,(dreg));
1661 *(cd->mcodeptr++) = 0xd1;
1662 emit_reg((opc),(dreg));
1664 emit_rex(0,0,0,(dreg));
1665 *(cd->mcodeptr++) = 0xc1;
1666 emit_reg((opc),(dreg));
1672 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1674 emit_rex(1,0,0,(basereg));
1675 *(cd->mcodeptr++) = 0xd1;
1676 emit_membase(cd, (basereg),(disp),(opc));
1678 emit_rex(1,0,0,(basereg));
1679 *(cd->mcodeptr++) = 0xc1;
1680 emit_membase(cd, (basereg),(disp),(opc));
1686 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1688 emit_rex(0,0,0,(basereg));
1689 *(cd->mcodeptr++) = 0xd1;
1690 emit_membase(cd, (basereg),(disp),(opc));
1692 emit_rex(0,0,0,(basereg));
1693 *(cd->mcodeptr++) = 0xc1;
1694 emit_membase(cd, (basereg),(disp),(opc));
1704 void emit_jmp_imm(codegendata *cd, s8 imm) {
1705 *(cd->mcodeptr++) = 0xe9;
1710 void emit_jmp_reg(codegendata *cd, s8 reg) {
1711 emit_rex(0,0,0,(reg));
1712 *(cd->mcodeptr++) = 0xff;
1717 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1718 *(cd->mcodeptr++) = 0x0f;
1719 *(cd->mcodeptr++) = (0x80 + (opc));
1726 * conditional set and move operations
1729 /* we need the rex byte to get all low bytes */
1730 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1732 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1733 *(cd->mcodeptr++) = 0x0f;
1734 *(cd->mcodeptr++) = (0x90 + (opc));
1739 /* we need the rex byte to get all low bytes */
1740 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1742 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1743 *(cd->mcodeptr++) = 0x0f;
1744 *(cd->mcodeptr++) = (0x90 + (opc));
1745 emit_membase(cd, (basereg),(disp),0);
1749 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1751 emit_rex(1,(dreg),0,(reg));
1752 *(cd->mcodeptr++) = 0x0f;
1753 *(cd->mcodeptr++) = (0x40 + (opc));
1754 emit_reg((dreg),(reg));
1758 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1760 emit_rex(0,(dreg),0,(reg));
1761 *(cd->mcodeptr++) = 0x0f;
1762 *(cd->mcodeptr++) = (0x40 + (opc));
1763 emit_reg((dreg),(reg));
1767 void emit_neg_reg(codegendata *cd, s8 reg)
1769 emit_rex(1,0,0,(reg));
1770 *(cd->mcodeptr++) = 0xf7;
1775 void emit_negl_reg(codegendata *cd, s8 reg)
1777 emit_rex(0,0,0,(reg));
1778 *(cd->mcodeptr++) = 0xf7;
1783 void emit_push_reg(codegendata *cd, s8 reg) {
1784 emit_rex(0,0,0,(reg));
1785 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1789 void emit_push_imm(codegendata *cd, s8 imm) {
1790 *(cd->mcodeptr++) = 0x68;
1795 void emit_pop_reg(codegendata *cd, s8 reg) {
1796 emit_rex(0,0,0,(reg));
1797 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1801 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1802 emit_rex(1,(reg),0,(dreg));
1803 *(cd->mcodeptr++) = 0x87;
1804 emit_reg((reg),(dreg));
1812 void emit_call_reg(codegendata *cd, s8 reg)
1814 emit_rex(0,0,0,(reg));
1815 *(cd->mcodeptr++) = 0xff;
1820 void emit_call_imm(codegendata *cd, s8 imm)
1822 *(cd->mcodeptr++) = 0xe8;
1827 void emit_call_mem(codegendata *cd, ptrint mem)
1829 *(cd->mcodeptr++) = 0xff;
1836 * floating point instructions (SSE2)
1838 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1839 *(cd->mcodeptr++) = 0xf2;
1840 emit_rex(0,(dreg),0,(reg));
1841 *(cd->mcodeptr++) = 0x0f;
1842 *(cd->mcodeptr++) = 0x58;
1843 emit_reg((dreg),(reg));
1847 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1848 *(cd->mcodeptr++) = 0xf3;
1849 emit_rex(0,(dreg),0,(reg));
1850 *(cd->mcodeptr++) = 0x0f;
1851 *(cd->mcodeptr++) = 0x58;
1852 emit_reg((dreg),(reg));
1856 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1857 *(cd->mcodeptr++) = 0xf3;
1858 emit_rex(1,(dreg),0,(reg));
1859 *(cd->mcodeptr++) = 0x0f;
1860 *(cd->mcodeptr++) = 0x2a;
1861 emit_reg((dreg),(reg));
1865 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1866 *(cd->mcodeptr++) = 0xf3;
1867 emit_rex(0,(dreg),0,(reg));
1868 *(cd->mcodeptr++) = 0x0f;
1869 *(cd->mcodeptr++) = 0x2a;
1870 emit_reg((dreg),(reg));
1874 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1875 *(cd->mcodeptr++) = 0xf2;
1876 emit_rex(1,(dreg),0,(reg));
1877 *(cd->mcodeptr++) = 0x0f;
1878 *(cd->mcodeptr++) = 0x2a;
1879 emit_reg((dreg),(reg));
1883 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1884 *(cd->mcodeptr++) = 0xf2;
1885 emit_rex(0,(dreg),0,(reg));
1886 *(cd->mcodeptr++) = 0x0f;
1887 *(cd->mcodeptr++) = 0x2a;
1888 emit_reg((dreg),(reg));
1892 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1893 *(cd->mcodeptr++) = 0xf3;
1894 emit_rex(0,(dreg),0,(reg));
1895 *(cd->mcodeptr++) = 0x0f;
1896 *(cd->mcodeptr++) = 0x5a;
1897 emit_reg((dreg),(reg));
1901 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1902 *(cd->mcodeptr++) = 0xf2;
1903 emit_rex(0,(dreg),0,(reg));
1904 *(cd->mcodeptr++) = 0x0f;
1905 *(cd->mcodeptr++) = 0x5a;
1906 emit_reg((dreg),(reg));
1910 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1911 *(cd->mcodeptr++) = 0xf3;
1912 emit_rex(1,(dreg),0,(reg));
1913 *(cd->mcodeptr++) = 0x0f;
1914 *(cd->mcodeptr++) = 0x2c;
1915 emit_reg((dreg),(reg));
1919 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1920 *(cd->mcodeptr++) = 0xf3;
1921 emit_rex(0,(dreg),0,(reg));
1922 *(cd->mcodeptr++) = 0x0f;
1923 *(cd->mcodeptr++) = 0x2c;
1924 emit_reg((dreg),(reg));
1928 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1929 *(cd->mcodeptr++) = 0xf2;
1930 emit_rex(1,(dreg),0,(reg));
1931 *(cd->mcodeptr++) = 0x0f;
1932 *(cd->mcodeptr++) = 0x2c;
1933 emit_reg((dreg),(reg));
1937 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1938 *(cd->mcodeptr++) = 0xf2;
1939 emit_rex(0,(dreg),0,(reg));
1940 *(cd->mcodeptr++) = 0x0f;
1941 *(cd->mcodeptr++) = 0x2c;
1942 emit_reg((dreg),(reg));
1946 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1947 *(cd->mcodeptr++) = 0xf3;
1948 emit_rex(0,(dreg),0,(reg));
1949 *(cd->mcodeptr++) = 0x0f;
1950 *(cd->mcodeptr++) = 0x5e;
1951 emit_reg((dreg),(reg));
1955 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1956 *(cd->mcodeptr++) = 0xf2;
1957 emit_rex(0,(dreg),0,(reg));
1958 *(cd->mcodeptr++) = 0x0f;
1959 *(cd->mcodeptr++) = 0x5e;
1960 emit_reg((dreg),(reg));
1964 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1965 *(cd->mcodeptr++) = 0x66;
1966 emit_rex(1,(freg),0,(reg));
1967 *(cd->mcodeptr++) = 0x0f;
1968 *(cd->mcodeptr++) = 0x6e;
1969 emit_reg((freg),(reg));
1973 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1974 *(cd->mcodeptr++) = 0x66;
1975 emit_rex(1,(freg),0,(reg));
1976 *(cd->mcodeptr++) = 0x0f;
1977 *(cd->mcodeptr++) = 0x7e;
1978 emit_reg((freg),(reg));
1982 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1983 *(cd->mcodeptr++) = 0x66;
1984 emit_rex(0,(reg),0,(basereg));
1985 *(cd->mcodeptr++) = 0x0f;
1986 *(cd->mcodeptr++) = 0x7e;
1987 emit_membase(cd, (basereg),(disp),(reg));
1991 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1992 *(cd->mcodeptr++) = 0x66;
1993 emit_rex(0,(reg),(indexreg),(basereg));
1994 *(cd->mcodeptr++) = 0x0f;
1995 *(cd->mcodeptr++) = 0x7e;
1996 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2000 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2001 *(cd->mcodeptr++) = 0x66;
2002 emit_rex(1,(dreg),0,(basereg));
2003 *(cd->mcodeptr++) = 0x0f;
2004 *(cd->mcodeptr++) = 0x6e;
2005 emit_membase(cd, (basereg),(disp),(dreg));
2009 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2010 *(cd->mcodeptr++) = 0x66;
2011 emit_rex(0,(dreg),0,(basereg));
2012 *(cd->mcodeptr++) = 0x0f;
2013 *(cd->mcodeptr++) = 0x6e;
2014 emit_membase(cd, (basereg),(disp),(dreg));
2018 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2019 *(cd->mcodeptr++) = 0x66;
2020 emit_rex(0,(dreg),(indexreg),(basereg));
2021 *(cd->mcodeptr++) = 0x0f;
2022 *(cd->mcodeptr++) = 0x6e;
2023 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2027 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2028 *(cd->mcodeptr++) = 0xf3;
2029 emit_rex(0,(dreg),0,(reg));
2030 *(cd->mcodeptr++) = 0x0f;
2031 *(cd->mcodeptr++) = 0x7e;
2032 emit_reg((dreg),(reg));
2036 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2037 *(cd->mcodeptr++) = 0x66;
2038 emit_rex(0,(reg),0,(basereg));
2039 *(cd->mcodeptr++) = 0x0f;
2040 *(cd->mcodeptr++) = 0xd6;
2041 emit_membase(cd, (basereg),(disp),(reg));
2045 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2046 *(cd->mcodeptr++) = 0xf3;
2047 emit_rex(0,(dreg),0,(basereg));
2048 *(cd->mcodeptr++) = 0x0f;
2049 *(cd->mcodeptr++) = 0x7e;
2050 emit_membase(cd, (basereg),(disp),(dreg));
2054 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2055 *(cd->mcodeptr++) = 0xf3;
2056 emit_rex(0,(reg),0,(dreg));
2057 *(cd->mcodeptr++) = 0x0f;
2058 *(cd->mcodeptr++) = 0x10;
2059 emit_reg((reg),(dreg));
2063 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2064 *(cd->mcodeptr++) = 0xf2;
2065 emit_rex(0,(reg),0,(dreg));
2066 *(cd->mcodeptr++) = 0x0f;
2067 *(cd->mcodeptr++) = 0x10;
2068 emit_reg((reg),(dreg));
2072 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2073 *(cd->mcodeptr++) = 0xf3;
2074 emit_rex(0,(reg),0,(basereg));
2075 *(cd->mcodeptr++) = 0x0f;
2076 *(cd->mcodeptr++) = 0x11;
2077 emit_membase(cd, (basereg),(disp),(reg));
2081 /* Always emit a REX byte, because the instruction size can be smaller when */
2082 /* all register indexes are smaller than 7. */
2083 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2084 *(cd->mcodeptr++) = 0xf3;
2085 emit_byte_rex((reg),0,(basereg));
2086 *(cd->mcodeptr++) = 0x0f;
2087 *(cd->mcodeptr++) = 0x11;
2088 emit_membase32(cd, (basereg),(disp),(reg));
2092 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2093 *(cd->mcodeptr++) = 0xf2;
2094 emit_rex(0,(reg),0,(basereg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = 0x11;
2097 emit_membase(cd, (basereg),(disp),(reg));
2101 /* Always emit a REX byte, because the instruction size can be smaller when */
2102 /* all register indexes are smaller than 7. */
2103 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2104 *(cd->mcodeptr++) = 0xf2;
2105 emit_byte_rex((reg),0,(basereg));
2106 *(cd->mcodeptr++) = 0x0f;
2107 *(cd->mcodeptr++) = 0x11;
2108 emit_membase32(cd, (basereg),(disp),(reg));
2112 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2113 *(cd->mcodeptr++) = 0xf3;
2114 emit_rex(0,(dreg),0,(basereg));
2115 *(cd->mcodeptr++) = 0x0f;
2116 *(cd->mcodeptr++) = 0x10;
2117 emit_membase(cd, (basereg),(disp),(dreg));
2121 /* Always emit a REX byte, because the instruction size can be smaller when */
2122 /* all register indexes are smaller than 7. */
2123 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2124 *(cd->mcodeptr++) = 0xf3;
2125 emit_byte_rex((dreg),0,(basereg));
2126 *(cd->mcodeptr++) = 0x0f;
2127 *(cd->mcodeptr++) = 0x10;
2128 emit_membase32(cd, (basereg),(disp),(dreg));
2132 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2134 emit_rex(0,(dreg),0,(basereg));
2135 *(cd->mcodeptr++) = 0x0f;
2136 *(cd->mcodeptr++) = 0x12;
2137 emit_membase(cd, (basereg),(disp),(dreg));
2141 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2143 emit_rex(0,(reg),0,(basereg));
2144 *(cd->mcodeptr++) = 0x0f;
2145 *(cd->mcodeptr++) = 0x13;
2146 emit_membase(cd, (basereg),(disp),(reg));
2150 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2151 *(cd->mcodeptr++) = 0xf2;
2152 emit_rex(0,(dreg),0,(basereg));
2153 *(cd->mcodeptr++) = 0x0f;
2154 *(cd->mcodeptr++) = 0x10;
2155 emit_membase(cd, (basereg),(disp),(dreg));
2159 /* Always emit a REX byte, because the instruction size can be smaller when */
2160 /* all register indexes are smaller than 7. */
2161 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2162 *(cd->mcodeptr++) = 0xf2;
2163 emit_byte_rex((dreg),0,(basereg));
2164 *(cd->mcodeptr++) = 0x0f;
2165 *(cd->mcodeptr++) = 0x10;
2166 emit_membase32(cd, (basereg),(disp),(dreg));
2170 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2172 *(cd->mcodeptr++) = 0x66;
2173 emit_rex(0,(dreg),0,(basereg));
2174 *(cd->mcodeptr++) = 0x0f;
2175 *(cd->mcodeptr++) = 0x12;
2176 emit_membase(cd, (basereg),(disp),(dreg));
2180 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2182 *(cd->mcodeptr++) = 0x66;
2183 emit_rex(0,(reg),0,(basereg));
2184 *(cd->mcodeptr++) = 0x0f;
2185 *(cd->mcodeptr++) = 0x13;
2186 emit_membase(cd, (basereg),(disp),(reg));
2190 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2191 *(cd->mcodeptr++) = 0xf3;
2192 emit_rex(0,(reg),(indexreg),(basereg));
2193 *(cd->mcodeptr++) = 0x0f;
2194 *(cd->mcodeptr++) = 0x11;
2195 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2199 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2200 *(cd->mcodeptr++) = 0xf2;
2201 emit_rex(0,(reg),(indexreg),(basereg));
2202 *(cd->mcodeptr++) = 0x0f;
2203 *(cd->mcodeptr++) = 0x11;
2204 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2208 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2209 *(cd->mcodeptr++) = 0xf3;
2210 emit_rex(0,(dreg),(indexreg),(basereg));
2211 *(cd->mcodeptr++) = 0x0f;
2212 *(cd->mcodeptr++) = 0x10;
2213 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2217 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2218 *(cd->mcodeptr++) = 0xf2;
2219 emit_rex(0,(dreg),(indexreg),(basereg));
2220 *(cd->mcodeptr++) = 0x0f;
2221 *(cd->mcodeptr++) = 0x10;
2222 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2226 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2227 *(cd->mcodeptr++) = 0xf3;
2228 emit_rex(0,(dreg),0,(reg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x59;
2231 emit_reg((dreg),(reg));
2235 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2236 *(cd->mcodeptr++) = 0xf2;
2237 emit_rex(0,(dreg),0,(reg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x59;
2240 emit_reg((dreg),(reg));
2244 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2245 *(cd->mcodeptr++) = 0xf3;
2246 emit_rex(0,(dreg),0,(reg));
2247 *(cd->mcodeptr++) = 0x0f;
2248 *(cd->mcodeptr++) = 0x5c;
2249 emit_reg((dreg),(reg));
2253 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2254 *(cd->mcodeptr++) = 0xf2;
2255 emit_rex(0,(dreg),0,(reg));
2256 *(cd->mcodeptr++) = 0x0f;
2257 *(cd->mcodeptr++) = 0x5c;
2258 emit_reg((dreg),(reg));
2262 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2263 emit_rex(0,(dreg),0,(reg));
2264 *(cd->mcodeptr++) = 0x0f;
2265 *(cd->mcodeptr++) = 0x2e;
2266 emit_reg((dreg),(reg));
2270 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2271 *(cd->mcodeptr++) = 0x66;
2272 emit_rex(0,(dreg),0,(reg));
2273 *(cd->mcodeptr++) = 0x0f;
2274 *(cd->mcodeptr++) = 0x2e;
2275 emit_reg((dreg),(reg));
2279 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2280 emit_rex(0,(dreg),0,(reg));
2281 *(cd->mcodeptr++) = 0x0f;
2282 *(cd->mcodeptr++) = 0x57;
2283 emit_reg((dreg),(reg));
2287 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2288 emit_rex(0,(dreg),0,(basereg));
2289 *(cd->mcodeptr++) = 0x0f;
2290 *(cd->mcodeptr++) = 0x57;
2291 emit_membase(cd, (basereg),(disp),(dreg));
2295 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2296 *(cd->mcodeptr++) = 0x66;
2297 emit_rex(0,(dreg),0,(reg));
2298 *(cd->mcodeptr++) = 0x0f;
2299 *(cd->mcodeptr++) = 0x57;
2300 emit_reg((dreg),(reg));
2304 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2305 *(cd->mcodeptr++) = 0x66;
2306 emit_rex(0,(dreg),0,(basereg));
2307 *(cd->mcodeptr++) = 0x0f;
2308 *(cd->mcodeptr++) = 0x57;
2309 emit_membase(cd, (basereg),(disp),(dreg));
2313 /* system instructions ********************************************************/
2315 void emit_rdtsc(codegendata *cd)
2317 *(cd->mcodeptr++) = 0x0f;
2318 *(cd->mcodeptr++) = 0x31;
2323 * These are local overrides for various environment variables in Emacs.
2324 * Please do not remove this and leave it at the end of the file, where
2325 * Emacs will automagically detect them.
2326 * ---------------------------------------------------------------------
2329 * indent-tabs-mode: t