1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/builtin.h"
43 #include "vm/exceptions.h"
45 #include "vm/jit/abi.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/patcher-common.h"
52 #include "vm/jit/replace.h"
54 #include "vmcore/options.h"
57 /* emit_load *******************************************************************
59 Emits a possible load of an operand.
61 *******************************************************************************/
63 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
69 /* get required compiler data */
73 if (IS_INMEMORY(src->flags)) {
76 disp = src->vv.regoff;
80 M_ILD(tempreg, REG_SP, disp);
84 M_LLD(tempreg, REG_SP, disp);
87 M_FLD(tempreg, REG_SP, disp);
90 M_DLD(tempreg, REG_SP, disp);
93 vm_abort("emit_load: unknown type %d", src->type);
105 /* emit_store ******************************************************************
107 This function generates the code to store the result of an
108 operation back into a spilled pseudo-variable. If the
109 pseudo-variable has not been spilled in the first place, this
110 function will generate nothing.
112 *******************************************************************************/
114 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
123 /* get required compiler data */
128 /* do we have to generate a conditional move? */
130 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
131 /* the passed register d is actually the source register */
135 /* Only pass the opcode to codegen_reg_of_var to get the real
136 destination register. */
138 opcode = iptr->opc & ICMD_OPCODE_MASK;
140 /* get the real destination register */
142 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
144 /* and emit the conditional move */
146 emit_cmovxx(cd, iptr, s, d);
150 if (IS_INMEMORY(dst->flags)) {
153 disp = dst->vv.regoff;
159 M_LST(d, REG_SP, disp);
162 M_FST(d, REG_SP, disp);
165 M_DST(d, REG_SP, disp);
168 vm_abort("emit_store: unknown type %d", dst->type);
174 /* emit_copy *******************************************************************
176 Generates a register/memory to register/memory copy.
178 *******************************************************************************/
180 void emit_copy(jitdata *jd, instruction *iptr)
187 /* get required compiler data */
191 /* get source and destination variables */
193 src = VAROP(iptr->s1);
194 dst = VAROP(iptr->dst);
196 if ((src->vv.regoff != dst->vv.regoff) ||
197 ((src->flags ^ dst->flags) & INMEMORY)) {
199 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
200 /* emit nothing, as the value won't be used anyway */
204 /* If one of the variables resides in memory, we can eliminate
205 the register move from/to the temporary register with the
206 order of getting the destination register and the load. */
208 if (IS_INMEMORY(src->flags)) {
209 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
210 s1 = emit_load(jd, iptr, src, d);
213 s1 = emit_load(jd, iptr, src, REG_IFTMP);
214 d = codegen_reg_of_var(iptr->opc, dst, s1);
229 vm_abort("emit_copy: unknown type %d", src->type);
233 emit_store(jd, iptr, dst, d);
238 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
241 switch (iptr->flags.fields.condition) {
265 /* emit_branch *****************************************************************
267 Emits the code for conditional and unconditional branchs.
269 *******************************************************************************/
271 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
275 /* NOTE: A displacement overflow cannot happen. */
277 /* check which branch to generate */
279 if (condition == BRANCH_UNCONDITIONAL) {
281 /* calculate the different displacements */
283 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
285 M_JMP_IMM(branchdisp);
288 /* calculate the different displacements */
290 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
324 vm_abort("emit_branch: unknown condition %d", condition);
330 /* emit_arithmetic_check *******************************************************
332 Emit an ArithmeticException check.
334 *******************************************************************************/
336 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
338 if (INSTRUCTION_MUST_CHECK(iptr)) {
341 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
346 /* emit_arrayindexoutofbounds_check ********************************************
348 Emit a ArrayIndexOutOfBoundsException check.
350 *******************************************************************************/
352 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
354 if (INSTRUCTION_MUST_CHECK(iptr)) {
355 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
356 M_ICMP(REG_ITMP3, s2);
358 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
363 /* emit_arraystore_check *******************************************************
365 Emit an ArrayStoreException check.
367 *******************************************************************************/
369 void emit_arraystore_check(codegendata *cd, instruction *iptr)
371 if (INSTRUCTION_MUST_CHECK(iptr)) {
374 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_ARRAYSTORE);
379 /* emit_classcast_check ********************************************************
381 Emit a ClassCastException check.
383 *******************************************************************************/
385 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
387 if (INSTRUCTION_MUST_CHECK(iptr)) {
399 vm_abort("emit_classcast_check: unknown condition %d", condition);
401 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
406 /* emit_nullpointer_check ******************************************************
408 Emit a NullPointerException check.
410 *******************************************************************************/
412 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
414 if (INSTRUCTION_MUST_CHECK(iptr)) {
417 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
422 /* emit_exception_check ********************************************************
424 Emit an Exception check.
426 *******************************************************************************/
428 void emit_exception_check(codegendata *cd, instruction *iptr)
430 if (INSTRUCTION_MUST_CHECK(iptr)) {
433 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
438 /* emit_trap *******************************************************************
440 Emit a trap instruction and return the original machine code.
442 *******************************************************************************/
444 uint32_t emit_trap(codegendata *cd)
448 /* Get machine code which is patched back in later. The trap is 2
451 mcode = *((uint16_t *) cd->mcodeptr);
453 /* XXX This needs to be change to INT3 when the debugging problems
454 with gdb are resolved. */
462 /* emit_verbosecall_enter ******************************************************
464 Generates the code for the call trace.
466 *******************************************************************************/
469 void emit_verbosecall_enter(jitdata *jd)
477 /* get required compiler data */
485 /* mark trace code */
489 /* additional +1 is for 16-byte stack alignment */
491 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
493 /* save argument registers */
495 for (i = 0; i < INT_ARG_CNT; i++)
496 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
498 for (i = 0; i < FLT_ARG_CNT; i++)
499 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
501 /* save temporary registers for leaf methods */
503 if (jd->isleafmethod) {
504 for (i = 0; i < INT_TMP_CNT; i++)
505 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
507 for (i = 0; i < FLT_TMP_CNT; i++)
508 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
511 /* show integer hex code for float arguments */
513 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
514 /* If the paramtype is a float, we have to right shift all
515 following integer registers. */
517 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
518 for (k = INT_ARG_CNT - 2; k >= i; k--)
519 M_MOV(abi_registers_integer_argument[k],
520 abi_registers_integer_argument[k + 1]);
522 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
523 abi_registers_integer_argument[i]);
528 M_MOV_IMM(m, REG_ITMP2);
529 M_AST(REG_ITMP2, REG_SP, 0 * 8);
530 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
533 /* restore argument registers */
535 for (i = 0; i < INT_ARG_CNT; i++)
536 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
538 for (i = 0; i < FLT_ARG_CNT; i++)
539 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
541 /* restore temporary registers for leaf methods */
543 if (jd->isleafmethod) {
544 for (i = 0; i < INT_TMP_CNT; i++)
545 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
547 for (i = 0; i < FLT_TMP_CNT; i++)
548 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
551 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
553 /* mark trace code */
557 #endif /* !defined(NDEBUG) */
560 /* emit_verbosecall_exit *******************************************************
562 Generates the code for the call trace.
564 *******************************************************************************/
567 void emit_verbosecall_exit(jitdata *jd)
573 /* get required compiler data */
579 /* mark trace code */
583 M_ASUB_IMM(2 * 8, REG_SP);
585 M_LST(REG_RESULT, REG_SP, 0 * 8);
586 M_DST(REG_FRESULT, REG_SP, 1 * 8);
588 M_INTMOVE(REG_RESULT, REG_A0);
589 M_FLTMOVE(REG_FRESULT, REG_FA0);
590 M_FLTMOVE(REG_FRESULT, REG_FA1);
591 M_MOV_IMM(m, REG_A1);
593 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
596 M_LLD(REG_RESULT, REG_SP, 0 * 8);
597 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
599 M_AADD_IMM(2 * 8, REG_SP);
601 /* mark trace code */
605 #endif /* !defined(NDEBUG) */
608 /* code generation functions **************************************************/
610 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
612 if ((basereg == REG_SP) || (basereg == R12)) {
614 emit_address_byte(0, dreg, REG_SP);
615 emit_address_byte(0, REG_SP, REG_SP);
617 } else if (IS_IMM8(disp)) {
618 emit_address_byte(1, dreg, REG_SP);
619 emit_address_byte(0, REG_SP, REG_SP);
623 emit_address_byte(2, dreg, REG_SP);
624 emit_address_byte(0, REG_SP, REG_SP);
628 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
629 emit_address_byte(0,(dreg),(basereg));
631 } else if ((basereg) == RIP) {
632 emit_address_byte(0, dreg, RBP);
637 emit_address_byte(1, dreg, basereg);
641 emit_address_byte(2, dreg, basereg);
648 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
650 if ((basereg == REG_SP) || (basereg == R12)) {
651 emit_address_byte(2, dreg, REG_SP);
652 emit_address_byte(0, REG_SP, REG_SP);
656 emit_address_byte(2, dreg, basereg);
662 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
665 emit_address_byte(0, reg, 4);
666 emit_address_byte(scale, indexreg, 5);
669 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
670 emit_address_byte(0, reg, 4);
671 emit_address_byte(scale, indexreg, basereg);
673 else if (IS_IMM8(disp)) {
674 emit_address_byte(1, reg, 4);
675 emit_address_byte(scale, indexreg, basereg);
679 emit_address_byte(2, reg, 4);
680 emit_address_byte(scale, indexreg, basereg);
686 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
689 varinfo *v_s1,*v_s2,*v_dst;
692 /* get required compiler data */
696 v_s1 = VAROP(iptr->s1);
697 v_s2 = VAROP(iptr->sx.s23.s2);
698 v_dst = VAROP(iptr->dst);
700 s1 = v_s1->vv.regoff;
701 s2 = v_s2->vv.regoff;
702 d = v_dst->vv.regoff;
704 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
706 if (IS_INMEMORY(v_dst->flags)) {
707 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
709 M_ILD(RCX, REG_SP, s2);
710 emit_shiftl_membase(cd, shift_op, REG_SP, d);
713 M_ILD(RCX, REG_SP, s2);
714 M_ILD(REG_ITMP2, REG_SP, s1);
715 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
716 M_IST(REG_ITMP2, REG_SP, d);
719 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
720 /* s1 may be equal to RCX */
723 M_ILD(REG_ITMP1, REG_SP, s2);
724 M_IST(s1, REG_SP, d);
725 M_INTMOVE(REG_ITMP1, RCX);
728 M_IST(s1, REG_SP, d);
729 M_ILD(RCX, REG_SP, s2);
733 M_ILD(RCX, REG_SP, s2);
734 M_IST(s1, REG_SP, d);
737 emit_shiftl_membase(cd, shift_op, REG_SP, d);
739 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
742 emit_shiftl_membase(cd, shift_op, REG_SP, d);
746 M_ILD(REG_ITMP2, REG_SP, s1);
747 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
748 M_IST(REG_ITMP2, REG_SP, d);
752 /* s1 may be equal to RCX */
753 M_IST(s1, REG_SP, d);
755 emit_shiftl_membase(cd, shift_op, REG_SP, d);
758 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
766 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
767 M_ILD(RCX, REG_SP, s2);
768 M_ILD(d, REG_SP, s1);
769 emit_shiftl_reg(cd, shift_op, d);
771 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
772 /* s1 may be equal to RCX */
774 M_ILD(RCX, REG_SP, s2);
775 emit_shiftl_reg(cd, shift_op, d);
777 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
779 M_ILD(d, REG_SP, s1);
780 emit_shiftl_reg(cd, shift_op, d);
783 /* s1 may be equal to RCX */
786 /* d cannot be used to backup s1 since this would
788 M_INTMOVE(s1, REG_ITMP3);
790 M_INTMOVE(REG_ITMP3, d);
798 /* d may be equal to s2 */
802 emit_shiftl_reg(cd, shift_op, d);
806 M_INTMOVE(REG_ITMP3, RCX);
808 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
813 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
816 varinfo *v_s1,*v_s2,*v_dst;
819 /* get required compiler data */
823 v_s1 = VAROP(iptr->s1);
824 v_s2 = VAROP(iptr->sx.s23.s2);
825 v_dst = VAROP(iptr->dst);
827 s1 = v_s1->vv.regoff;
828 s2 = v_s2->vv.regoff;
829 d = v_dst->vv.regoff;
831 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
833 if (IS_INMEMORY(v_dst->flags)) {
834 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
836 M_ILD(RCX, REG_SP, s2);
837 emit_shift_membase(cd, shift_op, REG_SP, d);
840 M_ILD(RCX, REG_SP, s2);
841 M_LLD(REG_ITMP2, REG_SP, s1);
842 emit_shift_reg(cd, shift_op, REG_ITMP2);
843 M_LST(REG_ITMP2, REG_SP, d);
846 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
847 /* s1 may be equal to RCX */
850 M_ILD(REG_ITMP1, REG_SP, s2);
851 M_LST(s1, REG_SP, d);
852 M_INTMOVE(REG_ITMP1, RCX);
855 M_LST(s1, REG_SP, d);
856 M_ILD(RCX, REG_SP, s2);
860 M_ILD(RCX, REG_SP, s2);
861 M_LST(s1, REG_SP, d);
864 emit_shift_membase(cd, shift_op, REG_SP, d);
866 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
869 emit_shift_membase(cd, shift_op, REG_SP, d);
873 M_LLD(REG_ITMP2, REG_SP, s1);
874 emit_shift_reg(cd, shift_op, REG_ITMP2);
875 M_LST(REG_ITMP2, REG_SP, d);
879 /* s1 may be equal to RCX */
880 M_LST(s1, REG_SP, d);
882 emit_shift_membase(cd, shift_op, REG_SP, d);
885 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
893 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
894 M_ILD(RCX, REG_SP, s2);
895 M_LLD(d, REG_SP, s1);
896 emit_shift_reg(cd, shift_op, d);
898 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
899 /* s1 may be equal to RCX */
901 M_ILD(RCX, REG_SP, s2);
902 emit_shift_reg(cd, shift_op, d);
904 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
906 M_LLD(d, REG_SP, s1);
907 emit_shift_reg(cd, shift_op, d);
910 /* s1 may be equal to RCX */
913 /* d cannot be used to backup s1 since this would
915 M_INTMOVE(s1, REG_ITMP3);
917 M_INTMOVE(REG_ITMP3, d);
925 /* d may be equal to s2 */
929 emit_shift_reg(cd, shift_op, d);
933 M_INTMOVE(REG_ITMP3, RCX);
935 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
940 /* low-level code emitter functions *******************************************/
942 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
944 emit_rex(1,(reg),0,(dreg));
945 *(cd->mcodeptr++) = 0x89;
946 emit_reg((reg),(dreg));
950 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
952 emit_rex(1,0,0,(reg));
953 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
958 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
960 emit_rex(0,(reg),0,(dreg));
961 *(cd->mcodeptr++) = 0x89;
962 emit_reg((reg),(dreg));
966 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
967 emit_rex(0,0,0,(reg));
968 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
973 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
974 emit_rex(1,(reg),0,(basereg));
975 *(cd->mcodeptr++) = 0x8b;
976 emit_membase(cd, (basereg),(disp),(reg));
981 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
982 * constant membase immediate length of 32bit
984 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
985 emit_rex(1,(reg),0,(basereg));
986 *(cd->mcodeptr++) = 0x8b;
987 emit_membase32(cd, (basereg),(disp),(reg));
991 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
993 emit_rex(0,(reg),0,(basereg));
994 *(cd->mcodeptr++) = 0x8b;
995 emit_membase(cd, (basereg),(disp),(reg));
999 /* ATTENTION: Always emit a REX byte, because the instruction size can
1000 be smaller when all register indexes are smaller than 7. */
1001 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1003 emit_byte_rex((reg),0,(basereg));
1004 *(cd->mcodeptr++) = 0x8b;
1005 emit_membase32(cd, (basereg),(disp),(reg));
1009 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1010 emit_rex(1,(reg),0,(basereg));
1011 *(cd->mcodeptr++) = 0x89;
1012 emit_membase(cd, (basereg),(disp),(reg));
1016 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1017 emit_rex(1,(reg),0,(basereg));
1018 *(cd->mcodeptr++) = 0x89;
1019 emit_membase32(cd, (basereg),(disp),(reg));
1023 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1024 emit_rex(0,(reg),0,(basereg));
1025 *(cd->mcodeptr++) = 0x89;
1026 emit_membase(cd, (basereg),(disp),(reg));
1030 /* Always emit a REX byte, because the instruction size can be smaller when */
1031 /* all register indexes are smaller than 7. */
1032 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1033 emit_byte_rex((reg),0,(basereg));
1034 *(cd->mcodeptr++) = 0x89;
1035 emit_membase32(cd, (basereg),(disp),(reg));
1039 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1040 emit_rex(1,(reg),(indexreg),(basereg));
1041 *(cd->mcodeptr++) = 0x8b;
1042 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1046 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1047 emit_rex(0,(reg),(indexreg),(basereg));
1048 *(cd->mcodeptr++) = 0x8b;
1049 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1053 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1054 emit_rex(1,(reg),(indexreg),(basereg));
1055 *(cd->mcodeptr++) = 0x89;
1056 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1060 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1061 emit_rex(0,(reg),(indexreg),(basereg));
1062 *(cd->mcodeptr++) = 0x89;
1063 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1067 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1068 *(cd->mcodeptr++) = 0x66;
1069 emit_rex(0,(reg),(indexreg),(basereg));
1070 *(cd->mcodeptr++) = 0x89;
1071 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1075 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1076 emit_byte_rex((reg),(indexreg),(basereg));
1077 *(cd->mcodeptr++) = 0x88;
1078 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1082 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1083 emit_rex(1,0,0,(basereg));
1084 *(cd->mcodeptr++) = 0xc7;
1085 emit_membase(cd, (basereg),(disp),0);
1090 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1091 emit_rex(1,0,0,(basereg));
1092 *(cd->mcodeptr++) = 0xc7;
1093 emit_membase32(cd, (basereg),(disp),0);
1098 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1099 emit_rex(0,0,0,(basereg));
1100 *(cd->mcodeptr++) = 0xc7;
1101 emit_membase(cd, (basereg),(disp),0);
1106 /* Always emit a REX byte, because the instruction size can be smaller when */
1107 /* all register indexes are smaller than 7. */
1108 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1109 emit_byte_rex(0,0,(basereg));
1110 *(cd->mcodeptr++) = 0xc7;
1111 emit_membase32(cd, (basereg),(disp),0);
1116 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1118 emit_rex(1,(dreg),0,(reg));
1119 *(cd->mcodeptr++) = 0x0f;
1120 *(cd->mcodeptr++) = 0xbe;
1121 /* XXX: why do reg and dreg have to be exchanged */
1122 emit_reg((dreg),(reg));
1126 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1128 emit_rex(1,(dreg),0,(reg));
1129 *(cd->mcodeptr++) = 0x0f;
1130 *(cd->mcodeptr++) = 0xbf;
1131 /* XXX: why do reg and dreg have to be exchanged */
1132 emit_reg((dreg),(reg));
1136 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1138 emit_rex(1,(dreg),0,(reg));
1139 *(cd->mcodeptr++) = 0x63;
1140 /* XXX: why do reg and dreg have to be exchanged */
1141 emit_reg((dreg),(reg));
1145 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1147 emit_rex(1,(dreg),0,(reg));
1148 *(cd->mcodeptr++) = 0x0f;
1149 *(cd->mcodeptr++) = 0xb7;
1150 /* XXX: why do reg and dreg have to be exchanged */
1151 emit_reg((dreg),(reg));
1155 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1156 emit_rex(1,(reg),(indexreg),(basereg));
1157 *(cd->mcodeptr++) = 0x0f;
1158 *(cd->mcodeptr++) = 0xbf;
1159 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1163 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1164 emit_rex(1,(reg),(indexreg),(basereg));
1165 *(cd->mcodeptr++) = 0x0f;
1166 *(cd->mcodeptr++) = 0xbe;
1167 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1171 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1172 emit_rex(1,(reg),(indexreg),(basereg));
1173 *(cd->mcodeptr++) = 0x0f;
1174 *(cd->mcodeptr++) = 0xb7;
1175 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1179 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1181 emit_rex(1,0,(indexreg),(basereg));
1182 *(cd->mcodeptr++) = 0xc7;
1183 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1188 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1190 emit_rex(0,0,(indexreg),(basereg));
1191 *(cd->mcodeptr++) = 0xc7;
1192 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1197 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1199 *(cd->mcodeptr++) = 0x66;
1200 emit_rex(0,0,(indexreg),(basereg));
1201 *(cd->mcodeptr++) = 0xc7;
1202 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1207 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1209 emit_rex(0,0,(indexreg),(basereg));
1210 *(cd->mcodeptr++) = 0xc6;
1211 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1216 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1218 emit_rex(1, dreg, 0, 0);
1219 *(cd->mcodeptr++) = 0x8b;
1220 emit_address_byte(0, dreg, 4);
1228 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1230 emit_rex(1,(reg),0,(dreg));
1231 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1232 emit_reg((reg),(dreg));
1236 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1238 emit_rex(0,(reg),0,(dreg));
1239 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1240 emit_reg((reg),(dreg));
1244 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1246 emit_rex(1,(reg),0,(basereg));
1247 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1248 emit_membase(cd, (basereg),(disp),(reg));
1252 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1254 emit_rex(0,(reg),0,(basereg));
1255 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1256 emit_membase(cd, (basereg),(disp),(reg));
1260 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1262 emit_rex(1,(reg),0,(basereg));
1263 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1264 emit_membase(cd, (basereg),(disp),(reg));
1268 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1270 emit_rex(0,(reg),0,(basereg));
1271 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1272 emit_membase(cd, (basereg),(disp),(reg));
1276 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1278 emit_rex(1,0,0,(dreg));
1279 *(cd->mcodeptr++) = 0x83;
1280 emit_reg((opc),(dreg));
1283 emit_rex(1,0,0,(dreg));
1284 *(cd->mcodeptr++) = 0x81;
1285 emit_reg((opc),(dreg));
1291 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1293 emit_rex(1,0,0,(dreg));
1294 *(cd->mcodeptr++) = 0x81;
1295 emit_reg((opc),(dreg));
1300 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1302 emit_rex(0,0,0,(dreg));
1303 *(cd->mcodeptr++) = 0x81;
1304 emit_reg((opc),(dreg));
1309 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1311 emit_rex(0,0,0,(dreg));
1312 *(cd->mcodeptr++) = 0x83;
1313 emit_reg((opc),(dreg));
1316 emit_rex(0,0,0,(dreg));
1317 *(cd->mcodeptr++) = 0x81;
1318 emit_reg((opc),(dreg));
1324 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1326 emit_rex(1,(basereg),0,0);
1327 *(cd->mcodeptr++) = 0x83;
1328 emit_membase(cd, (basereg),(disp),(opc));
1331 emit_rex(1,(basereg),0,0);
1332 *(cd->mcodeptr++) = 0x81;
1333 emit_membase(cd, (basereg),(disp),(opc));
1339 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1341 emit_rex(0,(basereg),0,0);
1342 *(cd->mcodeptr++) = 0x83;
1343 emit_membase(cd, (basereg),(disp),(opc));
1346 emit_rex(0,(basereg),0,0);
1347 *(cd->mcodeptr++) = 0x81;
1348 emit_membase(cd, (basereg),(disp),(opc));
1354 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1355 emit_rex(1,(reg),0,(dreg));
1356 *(cd->mcodeptr++) = 0x85;
1357 emit_reg((reg),(dreg));
1361 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1362 emit_rex(0,(reg),0,(dreg));
1363 *(cd->mcodeptr++) = 0x85;
1364 emit_reg((reg),(dreg));
1368 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1369 *(cd->mcodeptr++) = 0xf7;
1375 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1376 *(cd->mcodeptr++) = 0x66;
1377 *(cd->mcodeptr++) = 0xf7;
1383 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1384 *(cd->mcodeptr++) = 0xf6;
1390 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1391 emit_rex(1,(reg),0,(basereg));
1392 *(cd->mcodeptr++) = 0x8d;
1393 emit_membase(cd, (basereg),(disp),(reg));
1397 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1398 emit_rex(0,(reg),0,(basereg));
1399 *(cd->mcodeptr++) = 0x8d;
1400 emit_membase(cd, (basereg),(disp),(reg));
1405 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1407 emit_rex(0,0,0,(basereg));
1408 *(cd->mcodeptr++) = 0xff;
1409 emit_membase(cd, (basereg),(disp),0);
1414 void emit_cltd(codegendata *cd) {
1415 *(cd->mcodeptr++) = 0x99;
1419 void emit_cqto(codegendata *cd) {
1421 *(cd->mcodeptr++) = 0x99;
1426 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1427 emit_rex(1,(dreg),0,(reg));
1428 *(cd->mcodeptr++) = 0x0f;
1429 *(cd->mcodeptr++) = 0xaf;
1430 emit_reg((dreg),(reg));
1434 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1435 emit_rex(0,(dreg),0,(reg));
1436 *(cd->mcodeptr++) = 0x0f;
1437 *(cd->mcodeptr++) = 0xaf;
1438 emit_reg((dreg),(reg));
1442 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1443 emit_rex(1,(dreg),0,(basereg));
1444 *(cd->mcodeptr++) = 0x0f;
1445 *(cd->mcodeptr++) = 0xaf;
1446 emit_membase(cd, (basereg),(disp),(dreg));
1450 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1451 emit_rex(0,(dreg),0,(basereg));
1452 *(cd->mcodeptr++) = 0x0f;
1453 *(cd->mcodeptr++) = 0xaf;
1454 emit_membase(cd, (basereg),(disp),(dreg));
1458 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1459 if (IS_IMM8((imm))) {
1460 emit_rex(1,0,0,(dreg));
1461 *(cd->mcodeptr++) = 0x6b;
1465 emit_rex(1,0,0,(dreg));
1466 *(cd->mcodeptr++) = 0x69;
1473 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1474 if (IS_IMM8((imm))) {
1475 emit_rex(1,(dreg),0,(reg));
1476 *(cd->mcodeptr++) = 0x6b;
1477 emit_reg((dreg),(reg));
1480 emit_rex(1,(dreg),0,(reg));
1481 *(cd->mcodeptr++) = 0x69;
1482 emit_reg((dreg),(reg));
1488 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1489 if (IS_IMM8((imm))) {
1490 emit_rex(0,(dreg),0,(reg));
1491 *(cd->mcodeptr++) = 0x6b;
1492 emit_reg((dreg),(reg));
1495 emit_rex(0,(dreg),0,(reg));
1496 *(cd->mcodeptr++) = 0x69;
1497 emit_reg((dreg),(reg));
1503 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1504 if (IS_IMM8((imm))) {
1505 emit_rex(1,(dreg),0,(basereg));
1506 *(cd->mcodeptr++) = 0x6b;
1507 emit_membase(cd, (basereg),(disp),(dreg));
1510 emit_rex(1,(dreg),0,(basereg));
1511 *(cd->mcodeptr++) = 0x69;
1512 emit_membase(cd, (basereg),(disp),(dreg));
1518 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1519 if (IS_IMM8((imm))) {
1520 emit_rex(0,(dreg),0,(basereg));
1521 *(cd->mcodeptr++) = 0x6b;
1522 emit_membase(cd, (basereg),(disp),(dreg));
1525 emit_rex(0,(dreg),0,(basereg));
1526 *(cd->mcodeptr++) = 0x69;
1527 emit_membase(cd, (basereg),(disp),(dreg));
1533 void emit_idiv_reg(codegendata *cd, s8 reg) {
1534 emit_rex(1,0,0,(reg));
1535 *(cd->mcodeptr++) = 0xf7;
1540 void emit_idivl_reg(codegendata *cd, s8 reg) {
1541 emit_rex(0,0,0,(reg));
1542 *(cd->mcodeptr++) = 0xf7;
1551 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1552 emit_rex(1,0,0,(reg));
1553 *(cd->mcodeptr++) = 0xd3;
1554 emit_reg((opc),(reg));
1558 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1559 emit_rex(0,0,0,(reg));
1560 *(cd->mcodeptr++) = 0xd3;
1561 emit_reg((opc),(reg));
1565 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1566 emit_rex(1,0,0,(basereg));
1567 *(cd->mcodeptr++) = 0xd3;
1568 emit_membase(cd, (basereg),(disp),(opc));
1572 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1573 emit_rex(0,0,0,(basereg));
1574 *(cd->mcodeptr++) = 0xd3;
1575 emit_membase(cd, (basereg),(disp),(opc));
1579 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1581 emit_rex(1,0,0,(dreg));
1582 *(cd->mcodeptr++) = 0xd1;
1583 emit_reg((opc),(dreg));
1585 emit_rex(1,0,0,(dreg));
1586 *(cd->mcodeptr++) = 0xc1;
1587 emit_reg((opc),(dreg));
1593 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1595 emit_rex(0,0,0,(dreg));
1596 *(cd->mcodeptr++) = 0xd1;
1597 emit_reg((opc),(dreg));
1599 emit_rex(0,0,0,(dreg));
1600 *(cd->mcodeptr++) = 0xc1;
1601 emit_reg((opc),(dreg));
1607 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1609 emit_rex(1,0,0,(basereg));
1610 *(cd->mcodeptr++) = 0xd1;
1611 emit_membase(cd, (basereg),(disp),(opc));
1613 emit_rex(1,0,0,(basereg));
1614 *(cd->mcodeptr++) = 0xc1;
1615 emit_membase(cd, (basereg),(disp),(opc));
1621 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1623 emit_rex(0,0,0,(basereg));
1624 *(cd->mcodeptr++) = 0xd1;
1625 emit_membase(cd, (basereg),(disp),(opc));
1627 emit_rex(0,0,0,(basereg));
1628 *(cd->mcodeptr++) = 0xc1;
1629 emit_membase(cd, (basereg),(disp),(opc));
1639 void emit_jmp_imm(codegendata *cd, s8 imm) {
1640 *(cd->mcodeptr++) = 0xe9;
1645 void emit_jmp_reg(codegendata *cd, s8 reg) {
1646 emit_rex(0,0,0,(reg));
1647 *(cd->mcodeptr++) = 0xff;
1652 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1653 *(cd->mcodeptr++) = 0x0f;
1654 *(cd->mcodeptr++) = (0x80 + (opc));
1661 * conditional set and move operations
1664 /* we need the rex byte to get all low bytes */
1665 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1667 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1668 *(cd->mcodeptr++) = 0x0f;
1669 *(cd->mcodeptr++) = (0x90 + (opc));
1674 /* we need the rex byte to get all low bytes */
1675 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1677 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1678 *(cd->mcodeptr++) = 0x0f;
1679 *(cd->mcodeptr++) = (0x90 + (opc));
1680 emit_membase(cd, (basereg),(disp),0);
1684 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1686 emit_rex(1,(dreg),0,(reg));
1687 *(cd->mcodeptr++) = 0x0f;
1688 *(cd->mcodeptr++) = (0x40 + (opc));
1689 emit_reg((dreg),(reg));
1693 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1695 emit_rex(0,(dreg),0,(reg));
1696 *(cd->mcodeptr++) = 0x0f;
1697 *(cd->mcodeptr++) = (0x40 + (opc));
1698 emit_reg((dreg),(reg));
1702 void emit_neg_reg(codegendata *cd, s8 reg)
1704 emit_rex(1,0,0,(reg));
1705 *(cd->mcodeptr++) = 0xf7;
1710 void emit_negl_reg(codegendata *cd, s8 reg)
1712 emit_rex(0,0,0,(reg));
1713 *(cd->mcodeptr++) = 0xf7;
1718 void emit_push_reg(codegendata *cd, s8 reg) {
1719 emit_rex(0,0,0,(reg));
1720 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1724 void emit_push_imm(codegendata *cd, s8 imm) {
1725 *(cd->mcodeptr++) = 0x68;
1730 void emit_pop_reg(codegendata *cd, s8 reg) {
1731 emit_rex(0,0,0,(reg));
1732 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1736 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1737 emit_rex(1,(reg),0,(dreg));
1738 *(cd->mcodeptr++) = 0x87;
1739 emit_reg((reg),(dreg));
1747 void emit_call_reg(codegendata *cd, s8 reg)
1749 emit_rex(0,0,0,(reg));
1750 *(cd->mcodeptr++) = 0xff;
1755 void emit_call_imm(codegendata *cd, s8 imm)
1757 *(cd->mcodeptr++) = 0xe8;
1762 void emit_call_mem(codegendata *cd, ptrint mem)
1764 *(cd->mcodeptr++) = 0xff;
1771 * floating point instructions (SSE2)
1773 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1774 *(cd->mcodeptr++) = 0xf2;
1775 emit_rex(0,(dreg),0,(reg));
1776 *(cd->mcodeptr++) = 0x0f;
1777 *(cd->mcodeptr++) = 0x58;
1778 emit_reg((dreg),(reg));
1782 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1783 *(cd->mcodeptr++) = 0xf3;
1784 emit_rex(0,(dreg),0,(reg));
1785 *(cd->mcodeptr++) = 0x0f;
1786 *(cd->mcodeptr++) = 0x58;
1787 emit_reg((dreg),(reg));
1791 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1792 *(cd->mcodeptr++) = 0xf3;
1793 emit_rex(1,(dreg),0,(reg));
1794 *(cd->mcodeptr++) = 0x0f;
1795 *(cd->mcodeptr++) = 0x2a;
1796 emit_reg((dreg),(reg));
1800 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1801 *(cd->mcodeptr++) = 0xf3;
1802 emit_rex(0,(dreg),0,(reg));
1803 *(cd->mcodeptr++) = 0x0f;
1804 *(cd->mcodeptr++) = 0x2a;
1805 emit_reg((dreg),(reg));
1809 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1810 *(cd->mcodeptr++) = 0xf2;
1811 emit_rex(1,(dreg),0,(reg));
1812 *(cd->mcodeptr++) = 0x0f;
1813 *(cd->mcodeptr++) = 0x2a;
1814 emit_reg((dreg),(reg));
1818 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1819 *(cd->mcodeptr++) = 0xf2;
1820 emit_rex(0,(dreg),0,(reg));
1821 *(cd->mcodeptr++) = 0x0f;
1822 *(cd->mcodeptr++) = 0x2a;
1823 emit_reg((dreg),(reg));
1827 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1828 *(cd->mcodeptr++) = 0xf3;
1829 emit_rex(0,(dreg),0,(reg));
1830 *(cd->mcodeptr++) = 0x0f;
1831 *(cd->mcodeptr++) = 0x5a;
1832 emit_reg((dreg),(reg));
1836 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1837 *(cd->mcodeptr++) = 0xf2;
1838 emit_rex(0,(dreg),0,(reg));
1839 *(cd->mcodeptr++) = 0x0f;
1840 *(cd->mcodeptr++) = 0x5a;
1841 emit_reg((dreg),(reg));
1845 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1846 *(cd->mcodeptr++) = 0xf3;
1847 emit_rex(1,(dreg),0,(reg));
1848 *(cd->mcodeptr++) = 0x0f;
1849 *(cd->mcodeptr++) = 0x2c;
1850 emit_reg((dreg),(reg));
1854 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1855 *(cd->mcodeptr++) = 0xf3;
1856 emit_rex(0,(dreg),0,(reg));
1857 *(cd->mcodeptr++) = 0x0f;
1858 *(cd->mcodeptr++) = 0x2c;
1859 emit_reg((dreg),(reg));
1863 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1864 *(cd->mcodeptr++) = 0xf2;
1865 emit_rex(1,(dreg),0,(reg));
1866 *(cd->mcodeptr++) = 0x0f;
1867 *(cd->mcodeptr++) = 0x2c;
1868 emit_reg((dreg),(reg));
1872 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1873 *(cd->mcodeptr++) = 0xf2;
1874 emit_rex(0,(dreg),0,(reg));
1875 *(cd->mcodeptr++) = 0x0f;
1876 *(cd->mcodeptr++) = 0x2c;
1877 emit_reg((dreg),(reg));
1881 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1882 *(cd->mcodeptr++) = 0xf3;
1883 emit_rex(0,(dreg),0,(reg));
1884 *(cd->mcodeptr++) = 0x0f;
1885 *(cd->mcodeptr++) = 0x5e;
1886 emit_reg((dreg),(reg));
1890 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1891 *(cd->mcodeptr++) = 0xf2;
1892 emit_rex(0,(dreg),0,(reg));
1893 *(cd->mcodeptr++) = 0x0f;
1894 *(cd->mcodeptr++) = 0x5e;
1895 emit_reg((dreg),(reg));
1899 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1900 *(cd->mcodeptr++) = 0x66;
1901 emit_rex(1,(freg),0,(reg));
1902 *(cd->mcodeptr++) = 0x0f;
1903 *(cd->mcodeptr++) = 0x6e;
1904 emit_reg((freg),(reg));
1908 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1909 *(cd->mcodeptr++) = 0x66;
1910 emit_rex(1,(freg),0,(reg));
1911 *(cd->mcodeptr++) = 0x0f;
1912 *(cd->mcodeptr++) = 0x7e;
1913 emit_reg((freg),(reg));
1917 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1918 *(cd->mcodeptr++) = 0x66;
1919 emit_rex(0,(reg),0,(basereg));
1920 *(cd->mcodeptr++) = 0x0f;
1921 *(cd->mcodeptr++) = 0x7e;
1922 emit_membase(cd, (basereg),(disp),(reg));
1926 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1927 *(cd->mcodeptr++) = 0x66;
1928 emit_rex(0,(reg),(indexreg),(basereg));
1929 *(cd->mcodeptr++) = 0x0f;
1930 *(cd->mcodeptr++) = 0x7e;
1931 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1935 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1936 *(cd->mcodeptr++) = 0x66;
1937 emit_rex(1,(dreg),0,(basereg));
1938 *(cd->mcodeptr++) = 0x0f;
1939 *(cd->mcodeptr++) = 0x6e;
1940 emit_membase(cd, (basereg),(disp),(dreg));
1944 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1945 *(cd->mcodeptr++) = 0x66;
1946 emit_rex(0,(dreg),0,(basereg));
1947 *(cd->mcodeptr++) = 0x0f;
1948 *(cd->mcodeptr++) = 0x6e;
1949 emit_membase(cd, (basereg),(disp),(dreg));
1953 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1954 *(cd->mcodeptr++) = 0x66;
1955 emit_rex(0,(dreg),(indexreg),(basereg));
1956 *(cd->mcodeptr++) = 0x0f;
1957 *(cd->mcodeptr++) = 0x6e;
1958 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
1962 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1963 *(cd->mcodeptr++) = 0xf3;
1964 emit_rex(0,(dreg),0,(reg));
1965 *(cd->mcodeptr++) = 0x0f;
1966 *(cd->mcodeptr++) = 0x7e;
1967 emit_reg((dreg),(reg));
1971 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1972 *(cd->mcodeptr++) = 0x66;
1973 emit_rex(0,(reg),0,(basereg));
1974 *(cd->mcodeptr++) = 0x0f;
1975 *(cd->mcodeptr++) = 0xd6;
1976 emit_membase(cd, (basereg),(disp),(reg));
1980 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1981 *(cd->mcodeptr++) = 0xf3;
1982 emit_rex(0,(dreg),0,(basereg));
1983 *(cd->mcodeptr++) = 0x0f;
1984 *(cd->mcodeptr++) = 0x7e;
1985 emit_membase(cd, (basereg),(disp),(dreg));
1989 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1990 *(cd->mcodeptr++) = 0xf3;
1991 emit_rex(0,(reg),0,(dreg));
1992 *(cd->mcodeptr++) = 0x0f;
1993 *(cd->mcodeptr++) = 0x10;
1994 emit_reg((reg),(dreg));
1998 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1999 *(cd->mcodeptr++) = 0xf2;
2000 emit_rex(0,(reg),0,(dreg));
2001 *(cd->mcodeptr++) = 0x0f;
2002 *(cd->mcodeptr++) = 0x10;
2003 emit_reg((reg),(dreg));
2007 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2008 *(cd->mcodeptr++) = 0xf3;
2009 emit_rex(0,(reg),0,(basereg));
2010 *(cd->mcodeptr++) = 0x0f;
2011 *(cd->mcodeptr++) = 0x11;
2012 emit_membase(cd, (basereg),(disp),(reg));
2016 /* Always emit a REX byte, because the instruction size can be smaller when */
2017 /* all register indexes are smaller than 7. */
2018 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2019 *(cd->mcodeptr++) = 0xf3;
2020 emit_byte_rex((reg),0,(basereg));
2021 *(cd->mcodeptr++) = 0x0f;
2022 *(cd->mcodeptr++) = 0x11;
2023 emit_membase32(cd, (basereg),(disp),(reg));
2027 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2028 *(cd->mcodeptr++) = 0xf2;
2029 emit_rex(0,(reg),0,(basereg));
2030 *(cd->mcodeptr++) = 0x0f;
2031 *(cd->mcodeptr++) = 0x11;
2032 emit_membase(cd, (basereg),(disp),(reg));
2036 /* Always emit a REX byte, because the instruction size can be smaller when */
2037 /* all register indexes are smaller than 7. */
2038 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2039 *(cd->mcodeptr++) = 0xf2;
2040 emit_byte_rex((reg),0,(basereg));
2041 *(cd->mcodeptr++) = 0x0f;
2042 *(cd->mcodeptr++) = 0x11;
2043 emit_membase32(cd, (basereg),(disp),(reg));
2047 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2048 *(cd->mcodeptr++) = 0xf3;
2049 emit_rex(0,(dreg),0,(basereg));
2050 *(cd->mcodeptr++) = 0x0f;
2051 *(cd->mcodeptr++) = 0x10;
2052 emit_membase(cd, (basereg),(disp),(dreg));
2056 /* Always emit a REX byte, because the instruction size can be smaller when */
2057 /* all register indexes are smaller than 7. */
2058 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2059 *(cd->mcodeptr++) = 0xf3;
2060 emit_byte_rex((dreg),0,(basereg));
2061 *(cd->mcodeptr++) = 0x0f;
2062 *(cd->mcodeptr++) = 0x10;
2063 emit_membase32(cd, (basereg),(disp),(dreg));
2067 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2069 emit_rex(0,(dreg),0,(basereg));
2070 *(cd->mcodeptr++) = 0x0f;
2071 *(cd->mcodeptr++) = 0x12;
2072 emit_membase(cd, (basereg),(disp),(dreg));
2076 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2078 emit_rex(0,(reg),0,(basereg));
2079 *(cd->mcodeptr++) = 0x0f;
2080 *(cd->mcodeptr++) = 0x13;
2081 emit_membase(cd, (basereg),(disp),(reg));
2085 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2086 *(cd->mcodeptr++) = 0xf2;
2087 emit_rex(0,(dreg),0,(basereg));
2088 *(cd->mcodeptr++) = 0x0f;
2089 *(cd->mcodeptr++) = 0x10;
2090 emit_membase(cd, (basereg),(disp),(dreg));
2094 /* Always emit a REX byte, because the instruction size can be smaller when */
2095 /* all register indexes are smaller than 7. */
2096 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2097 *(cd->mcodeptr++) = 0xf2;
2098 emit_byte_rex((dreg),0,(basereg));
2099 *(cd->mcodeptr++) = 0x0f;
2100 *(cd->mcodeptr++) = 0x10;
2101 emit_membase32(cd, (basereg),(disp),(dreg));
2105 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2107 *(cd->mcodeptr++) = 0x66;
2108 emit_rex(0,(dreg),0,(basereg));
2109 *(cd->mcodeptr++) = 0x0f;
2110 *(cd->mcodeptr++) = 0x12;
2111 emit_membase(cd, (basereg),(disp),(dreg));
2115 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2117 *(cd->mcodeptr++) = 0x66;
2118 emit_rex(0,(reg),0,(basereg));
2119 *(cd->mcodeptr++) = 0x0f;
2120 *(cd->mcodeptr++) = 0x13;
2121 emit_membase(cd, (basereg),(disp),(reg));
2125 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2126 *(cd->mcodeptr++) = 0xf3;
2127 emit_rex(0,(reg),(indexreg),(basereg));
2128 *(cd->mcodeptr++) = 0x0f;
2129 *(cd->mcodeptr++) = 0x11;
2130 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2134 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2135 *(cd->mcodeptr++) = 0xf2;
2136 emit_rex(0,(reg),(indexreg),(basereg));
2137 *(cd->mcodeptr++) = 0x0f;
2138 *(cd->mcodeptr++) = 0x11;
2139 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2143 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2144 *(cd->mcodeptr++) = 0xf3;
2145 emit_rex(0,(dreg),(indexreg),(basereg));
2146 *(cd->mcodeptr++) = 0x0f;
2147 *(cd->mcodeptr++) = 0x10;
2148 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2152 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2153 *(cd->mcodeptr++) = 0xf2;
2154 emit_rex(0,(dreg),(indexreg),(basereg));
2155 *(cd->mcodeptr++) = 0x0f;
2156 *(cd->mcodeptr++) = 0x10;
2157 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2161 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2162 *(cd->mcodeptr++) = 0xf3;
2163 emit_rex(0,(dreg),0,(reg));
2164 *(cd->mcodeptr++) = 0x0f;
2165 *(cd->mcodeptr++) = 0x59;
2166 emit_reg((dreg),(reg));
2170 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2171 *(cd->mcodeptr++) = 0xf2;
2172 emit_rex(0,(dreg),0,(reg));
2173 *(cd->mcodeptr++) = 0x0f;
2174 *(cd->mcodeptr++) = 0x59;
2175 emit_reg((dreg),(reg));
2179 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2180 *(cd->mcodeptr++) = 0xf3;
2181 emit_rex(0,(dreg),0,(reg));
2182 *(cd->mcodeptr++) = 0x0f;
2183 *(cd->mcodeptr++) = 0x5c;
2184 emit_reg((dreg),(reg));
2188 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2189 *(cd->mcodeptr++) = 0xf2;
2190 emit_rex(0,(dreg),0,(reg));
2191 *(cd->mcodeptr++) = 0x0f;
2192 *(cd->mcodeptr++) = 0x5c;
2193 emit_reg((dreg),(reg));
2197 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2198 emit_rex(0,(dreg),0,(reg));
2199 *(cd->mcodeptr++) = 0x0f;
2200 *(cd->mcodeptr++) = 0x2e;
2201 emit_reg((dreg),(reg));
2205 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2206 *(cd->mcodeptr++) = 0x66;
2207 emit_rex(0,(dreg),0,(reg));
2208 *(cd->mcodeptr++) = 0x0f;
2209 *(cd->mcodeptr++) = 0x2e;
2210 emit_reg((dreg),(reg));
2214 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2215 emit_rex(0,(dreg),0,(reg));
2216 *(cd->mcodeptr++) = 0x0f;
2217 *(cd->mcodeptr++) = 0x57;
2218 emit_reg((dreg),(reg));
2222 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2223 emit_rex(0,(dreg),0,(basereg));
2224 *(cd->mcodeptr++) = 0x0f;
2225 *(cd->mcodeptr++) = 0x57;
2226 emit_membase(cd, (basereg),(disp),(dreg));
2230 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2231 *(cd->mcodeptr++) = 0x66;
2232 emit_rex(0,(dreg),0,(reg));
2233 *(cd->mcodeptr++) = 0x0f;
2234 *(cd->mcodeptr++) = 0x57;
2235 emit_reg((dreg),(reg));
2239 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2240 *(cd->mcodeptr++) = 0x66;
2241 emit_rex(0,(dreg),0,(basereg));
2242 *(cd->mcodeptr++) = 0x0f;
2243 *(cd->mcodeptr++) = 0x57;
2244 emit_membase(cd, (basereg),(disp),(dreg));
2248 /* system instructions ********************************************************/
2250 void emit_rdtsc(codegendata *cd)
2252 *(cd->mcodeptr++) = 0x0f;
2253 *(cd->mcodeptr++) = 0x31;
2258 * These are local overrides for various environment variables in Emacs.
2259 * Please do not remove this and leave it at the end of the file, where
2260 * Emacs will automagically detect them.
2261 * ---------------------------------------------------------------------
2264 * indent-tabs-mode: t