1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7813 2007-04-25 19:20:13Z twisti $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #include "threads/lock-common.h"
44 #include "vm/builtin.h"
45 #include "vm/exceptions.h"
47 #include "vm/jit/abi.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
55 #include "vmcore/options.h"
58 /* emit_load *******************************************************************
60 Emits a possible load of an operand.
62 *******************************************************************************/
64 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
70 /* get required compiler data */
74 if (IS_INMEMORY(src->flags)) {
77 disp = src->vv.regoff * 8;
81 M_ILD(tempreg, REG_SP, disp);
85 M_LLD(tempreg, REG_SP, disp);
88 M_FLD(tempreg, REG_SP, disp);
91 M_DLD(tempreg, REG_SP, disp);
94 vm_abort("emit_load: unknown type %d", src->type);
100 reg = src->vv.regoff;
106 /* emit_store ******************************************************************
108 This function generates the code to store the result of an
109 operation back into a spilled pseudo-variable. If the
110 pseudo-variable has not been spilled in the first place, this
111 function will generate nothing.
113 *******************************************************************************/
115 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
124 /* get required compiler data */
129 /* do we have to generate a conditional move? */
131 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
132 /* the passed register d is actually the source register */
136 /* Only pass the opcode to codegen_reg_of_var to get the real
137 destination register. */
139 opcode = iptr->opc & ICMD_OPCODE_MASK;
141 /* get the real destination register */
143 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
145 /* and emit the conditional move */
147 emit_cmovxx(cd, iptr, s, d);
151 if (IS_INMEMORY(dst->flags)) {
154 disp = dst->vv.regoff * 8;
160 M_LST(d, REG_SP, disp);
163 M_FST(d, REG_SP, disp);
166 M_DST(d, REG_SP, disp);
169 vm_abort("emit_store: unknown type %d", dst->type);
175 /* emit_copy *******************************************************************
177 Generates a register/memory to register/memory copy.
179 *******************************************************************************/
181 void emit_copy(jitdata *jd, instruction *iptr)
188 /* get required compiler data */
192 /* get source and destination variables */
194 src = VAROP(iptr->s1);
195 dst = VAROP(iptr->dst);
197 if ((src->vv.regoff != dst->vv.regoff) ||
198 ((src->flags ^ dst->flags) & INMEMORY)) {
200 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
201 /* emit nothing, as the value won't be used anyway */
205 /* If one of the variables resides in memory, we can eliminate
206 the register move from/to the temporary register with the
207 order of getting the destination register and the load. */
209 if (IS_INMEMORY(src->flags)) {
210 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
211 s1 = emit_load(jd, iptr, src, d);
214 s1 = emit_load(jd, iptr, src, REG_IFTMP);
215 d = codegen_reg_of_var(iptr->opc, dst, s1);
230 vm_abort("emit_copy: unknown type %d", src->type);
234 emit_store(jd, iptr, dst, d);
239 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
242 switch (iptr->flags.fields.condition) {
266 /* emit_branch *****************************************************************
268 Emits the code for conditional and unconditional branchs.
270 *******************************************************************************/
272 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
276 /* NOTE: A displacement overflow cannot happen. */
278 /* check which branch to generate */
280 if (condition == BRANCH_UNCONDITIONAL) {
282 /* calculate the different displacements */
284 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
286 M_JMP_IMM(branchdisp);
289 /* calculate the different displacements */
291 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
325 vm_abort("emit_branch: unknown condition %d", condition);
331 /* emit_arithmetic_check *******************************************************
333 Emit an ArithmeticException check.
335 *******************************************************************************/
337 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
339 if (INSTRUCTION_MUST_CHECK(iptr)) {
342 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
347 /* emit_arrayindexoutofbounds_check ********************************************
349 Emit a ArrayIndexOutOfBoundsException check.
351 *******************************************************************************/
353 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
355 if (INSTRUCTION_MUST_CHECK(iptr)) {
356 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
357 M_ICMP(REG_ITMP3, s2);
359 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
364 /* emit_classcast_check ********************************************************
366 Emit a ClassCastException check.
368 *******************************************************************************/
370 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
372 if (INSTRUCTION_MUST_CHECK(iptr)) {
384 vm_abort("emit_classcast_check: unknown condition %d", condition);
386 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
391 /* emit_nullpointer_check ******************************************************
393 Emit a NullPointerException check.
395 *******************************************************************************/
397 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
399 if (INSTRUCTION_MUST_CHECK(iptr)) {
402 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
407 /* emit_exception_check ********************************************************
409 Emit an Exception check.
411 *******************************************************************************/
413 void emit_exception_check(codegendata *cd, instruction *iptr)
415 if (INSTRUCTION_MUST_CHECK(iptr)) {
418 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
423 /* emit_patcher_stubs **********************************************************
425 Generates the code for the patcher stubs.
427 *******************************************************************************/
429 void emit_patcher_stubs(jitdata *jd)
439 /* get required compiler data */
443 /* generate code patching stub call code */
447 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
448 /* check size of code segment */
452 /* Get machine code which is patched back in later. A
453 `call rel32' is 5 bytes long (but read 8 bytes). */
455 savedmcodeptr = cd->mcodebase + pref->branchpos;
456 mcode = *((u8 *) savedmcodeptr);
458 /* patch in `call rel32' to call the following code */
460 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
461 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
463 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
465 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
467 /* move pointer to java_objectheader onto stack */
469 #if defined(ENABLE_THREADS)
470 /* create a virtual java_objectheader */
472 (void) dseg_add_unique_address(cd, NULL); /* flcword */
473 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
474 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
476 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
482 /* move machine code bytes and classinfo pointer into registers */
484 M_MOV_IMM(mcode, REG_ITMP3);
487 M_MOV_IMM(pref->ref, REG_ITMP3);
490 M_MOV_IMM(pref->disp, REG_ITMP3);
493 M_MOV_IMM(pref->patcher, REG_ITMP3);
496 if (targetdisp == 0) {
497 targetdisp = cd->mcodeptr - cd->mcodebase;
499 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
503 M_JMP_IMM((cd->mcodebase + targetdisp) -
504 (cd->mcodeptr + PATCHER_CALL_SIZE));
510 /* emit_replacement_stubs ******************************************************
512 Generates the code for the replacement stubs.
514 *******************************************************************************/
516 #if defined(ENABLE_REPLACEMENT)
517 void emit_replacement_stubs(jitdata *jd)
527 /* get required compiler data */
532 rplp = code->rplpoints;
534 /* store beginning of replacement stubs */
536 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
538 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
539 /* do not generate stubs for non-trappable points */
541 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
544 /* check code segment size */
548 /* note start of stub code */
551 savedmcodeptr = cd->mcodeptr;
554 /* push address of `rplpoint` struct */
556 M_MOV_IMM(rplp, REG_ITMP3);
559 /* jump to replacement function */
561 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
565 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
568 #endif /* defined(ENABLE_REPLACEMENT) */
571 /* emit_verbosecall_enter ******************************************************
573 Generates the code for the call trace.
575 *******************************************************************************/
578 void emit_verbosecall_enter(jitdata *jd)
586 /* get required compiler data */
594 /* mark trace code */
598 /* additional +1 is for 16-byte stack alignment */
600 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
602 /* save argument registers */
604 for (i = 0; i < INT_ARG_CNT; i++)
605 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
607 for (i = 0; i < FLT_ARG_CNT; i++)
608 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
610 /* save temporary registers for leaf methods */
612 if (jd->isleafmethod) {
613 for (i = 0; i < INT_TMP_CNT; i++)
614 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
616 for (i = 0; i < FLT_TMP_CNT; i++)
617 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
620 /* show integer hex code for float arguments */
622 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
623 /* If the paramtype is a float, we have to right shift all
624 following integer registers. */
626 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
627 for (k = INT_ARG_CNT - 2; k >= i; k--)
628 M_MOV(abi_registers_integer_argument[k],
629 abi_registers_integer_argument[k + 1]);
631 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
632 abi_registers_integer_argument[i]);
637 M_MOV_IMM(m, REG_ITMP2);
638 M_AST(REG_ITMP2, REG_SP, 0 * 8);
639 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
642 /* restore argument registers */
644 for (i = 0; i < INT_ARG_CNT; i++)
645 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
647 for (i = 0; i < FLT_ARG_CNT; i++)
648 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
650 /* restore temporary registers for leaf methods */
652 if (jd->isleafmethod) {
653 for (i = 0; i < INT_TMP_CNT; i++)
654 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
656 for (i = 0; i < FLT_TMP_CNT; i++)
657 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
660 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
662 /* mark trace code */
666 #endif /* !defined(NDEBUG) */
669 /* emit_verbosecall_exit *******************************************************
671 Generates the code for the call trace.
673 *******************************************************************************/
676 void emit_verbosecall_exit(jitdata *jd)
682 /* get required compiler data */
688 /* mark trace code */
692 M_ASUB_IMM(2 * 8, REG_SP);
694 M_LST(REG_RESULT, REG_SP, 0 * 8);
695 M_DST(REG_FRESULT, REG_SP, 1 * 8);
697 M_INTMOVE(REG_RESULT, REG_A0);
698 M_FLTMOVE(REG_FRESULT, REG_FA0);
699 M_FLTMOVE(REG_FRESULT, REG_FA1);
700 M_MOV_IMM(m, REG_A1);
702 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
705 M_LLD(REG_RESULT, REG_SP, 0 * 8);
706 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
708 M_AADD_IMM(2 * 8, REG_SP);
710 /* mark trace code */
714 #endif /* !defined(NDEBUG) */
717 /* code generation functions **************************************************/
719 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
721 if ((basereg == REG_SP) || (basereg == R12)) {
723 emit_address_byte(0, dreg, REG_SP);
724 emit_address_byte(0, REG_SP, REG_SP);
726 } else if (IS_IMM8(disp)) {
727 emit_address_byte(1, dreg, REG_SP);
728 emit_address_byte(0, REG_SP, REG_SP);
732 emit_address_byte(2, dreg, REG_SP);
733 emit_address_byte(0, REG_SP, REG_SP);
737 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
738 emit_address_byte(0,(dreg),(basereg));
740 } else if ((basereg) == RIP) {
741 emit_address_byte(0, dreg, RBP);
746 emit_address_byte(1, dreg, basereg);
750 emit_address_byte(2, dreg, basereg);
757 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
759 if ((basereg == REG_SP) || (basereg == R12)) {
760 emit_address_byte(2, dreg, REG_SP);
761 emit_address_byte(0, REG_SP, REG_SP);
765 emit_address_byte(2, dreg, basereg);
771 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
774 emit_address_byte(0, reg, 4);
775 emit_address_byte(scale, indexreg, 5);
778 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
779 emit_address_byte(0, reg, 4);
780 emit_address_byte(scale, indexreg, basereg);
782 else if (IS_IMM8(disp)) {
783 emit_address_byte(1, reg, 4);
784 emit_address_byte(scale, indexreg, basereg);
788 emit_address_byte(2, reg, 4);
789 emit_address_byte(scale, indexreg, basereg);
795 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
798 varinfo *v_s1,*v_s2,*v_dst;
801 /* get required compiler data */
805 v_s1 = VAROP(iptr->s1);
806 v_s2 = VAROP(iptr->sx.s23.s2);
807 v_dst = VAROP(iptr->dst);
809 s1 = v_s1->vv.regoff;
810 s2 = v_s2->vv.regoff;
811 d = v_dst->vv.regoff;
813 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
815 if (IS_INMEMORY(v_dst->flags)) {
816 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
818 M_ILD(RCX, REG_SP, s2 * 8);
819 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
822 M_ILD(RCX, REG_SP, s2 * 8);
823 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
824 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
825 M_IST(REG_ITMP2, REG_SP, d * 8);
828 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
829 /* s1 may be equal to RCX */
832 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
833 M_IST(s1, REG_SP, d * 8);
834 M_INTMOVE(REG_ITMP1, RCX);
837 M_IST(s1, REG_SP, d * 8);
838 M_ILD(RCX, REG_SP, s2 * 8);
842 M_ILD(RCX, REG_SP, s2 * 8);
843 M_IST(s1, REG_SP, d * 8);
846 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
848 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
851 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
855 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
856 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
857 M_IST(REG_ITMP2, REG_SP, d * 8);
861 /* s1 may be equal to RCX */
862 M_IST(s1, REG_SP, d * 8);
864 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
867 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
875 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
876 M_ILD(RCX, REG_SP, s2 * 8);
877 M_ILD(d, REG_SP, s1 * 8);
878 emit_shiftl_reg(cd, shift_op, d);
880 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
881 /* s1 may be equal to RCX */
883 M_ILD(RCX, REG_SP, s2 * 8);
884 emit_shiftl_reg(cd, shift_op, d);
886 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
888 M_ILD(d, REG_SP, s1 * 8);
889 emit_shiftl_reg(cd, shift_op, d);
892 /* s1 may be equal to RCX */
895 /* d cannot be used to backup s1 since this would
897 M_INTMOVE(s1, REG_ITMP3);
899 M_INTMOVE(REG_ITMP3, d);
907 /* d may be equal to s2 */
911 emit_shiftl_reg(cd, shift_op, d);
915 M_INTMOVE(REG_ITMP3, RCX);
917 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
922 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
925 varinfo *v_s1,*v_s2,*v_dst;
928 /* get required compiler data */
932 v_s1 = VAROP(iptr->s1);
933 v_s2 = VAROP(iptr->sx.s23.s2);
934 v_dst = VAROP(iptr->dst);
936 s1 = v_s1->vv.regoff;
937 s2 = v_s2->vv.regoff;
938 d = v_dst->vv.regoff;
940 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
942 if (IS_INMEMORY(v_dst->flags)) {
943 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
945 M_ILD(RCX, REG_SP, s2 * 8);
946 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
949 M_ILD(RCX, REG_SP, s2 * 8);
950 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
951 emit_shift_reg(cd, shift_op, REG_ITMP2);
952 M_LST(REG_ITMP2, REG_SP, d * 8);
955 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
956 /* s1 may be equal to RCX */
959 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
960 M_LST(s1, REG_SP, d * 8);
961 M_INTMOVE(REG_ITMP1, RCX);
964 M_LST(s1, REG_SP, d * 8);
965 M_ILD(RCX, REG_SP, s2 * 8);
969 M_ILD(RCX, REG_SP, s2 * 8);
970 M_LST(s1, REG_SP, d * 8);
973 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
975 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
978 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
982 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
983 emit_shift_reg(cd, shift_op, REG_ITMP2);
984 M_LST(REG_ITMP2, REG_SP, d * 8);
988 /* s1 may be equal to RCX */
989 M_LST(s1, REG_SP, d * 8);
991 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
994 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1002 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1003 M_ILD(RCX, REG_SP, s2 * 8);
1004 M_LLD(d, REG_SP, s1 * 8);
1005 emit_shift_reg(cd, shift_op, d);
1007 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1008 /* s1 may be equal to RCX */
1010 M_ILD(RCX, REG_SP, s2 * 8);
1011 emit_shift_reg(cd, shift_op, d);
1013 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1015 M_LLD(d, REG_SP, s1 * 8);
1016 emit_shift_reg(cd, shift_op, d);
1019 /* s1 may be equal to RCX */
1022 /* d cannot be used to backup s1 since this would
1024 M_INTMOVE(s1, REG_ITMP3);
1026 M_INTMOVE(REG_ITMP3, d);
1034 /* d may be equal to s2 */
1038 emit_shift_reg(cd, shift_op, d);
1042 M_INTMOVE(REG_ITMP3, RCX);
1044 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1049 /* low-level code emitter functions *******************************************/
1051 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1053 emit_rex(1,(reg),0,(dreg));
1054 *(cd->mcodeptr++) = 0x89;
1055 emit_reg((reg),(dreg));
1059 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1061 emit_rex(1,0,0,(reg));
1062 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1067 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1069 emit_rex(0,(reg),0,(dreg));
1070 *(cd->mcodeptr++) = 0x89;
1071 emit_reg((reg),(dreg));
1075 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1076 emit_rex(0,0,0,(reg));
1077 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1082 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1083 emit_rex(1,(reg),0,(basereg));
1084 *(cd->mcodeptr++) = 0x8b;
1085 emit_membase(cd, (basereg),(disp),(reg));
1090 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1091 * constant membase immediate length of 32bit
1093 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1094 emit_rex(1,(reg),0,(basereg));
1095 *(cd->mcodeptr++) = 0x8b;
1096 emit_membase32(cd, (basereg),(disp),(reg));
1100 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1102 emit_rex(0,(reg),0,(basereg));
1103 *(cd->mcodeptr++) = 0x8b;
1104 emit_membase(cd, (basereg),(disp),(reg));
1108 /* ATTENTION: Always emit a REX byte, because the instruction size can
1109 be smaller when all register indexes are smaller than 7. */
1110 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1112 emit_byte_rex((reg),0,(basereg));
1113 *(cd->mcodeptr++) = 0x8b;
1114 emit_membase32(cd, (basereg),(disp),(reg));
1118 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1119 emit_rex(1,(reg),0,(basereg));
1120 *(cd->mcodeptr++) = 0x89;
1121 emit_membase(cd, (basereg),(disp),(reg));
1125 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1126 emit_rex(1,(reg),0,(basereg));
1127 *(cd->mcodeptr++) = 0x89;
1128 emit_membase32(cd, (basereg),(disp),(reg));
1132 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1133 emit_rex(0,(reg),0,(basereg));
1134 *(cd->mcodeptr++) = 0x89;
1135 emit_membase(cd, (basereg),(disp),(reg));
1139 /* Always emit a REX byte, because the instruction size can be smaller when */
1140 /* all register indexes are smaller than 7. */
1141 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1142 emit_byte_rex((reg),0,(basereg));
1143 *(cd->mcodeptr++) = 0x89;
1144 emit_membase32(cd, (basereg),(disp),(reg));
1148 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1149 emit_rex(1,(reg),(indexreg),(basereg));
1150 *(cd->mcodeptr++) = 0x8b;
1151 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1155 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1156 emit_rex(0,(reg),(indexreg),(basereg));
1157 *(cd->mcodeptr++) = 0x8b;
1158 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1162 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1163 emit_rex(1,(reg),(indexreg),(basereg));
1164 *(cd->mcodeptr++) = 0x89;
1165 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1169 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1170 emit_rex(0,(reg),(indexreg),(basereg));
1171 *(cd->mcodeptr++) = 0x89;
1172 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1176 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1177 *(cd->mcodeptr++) = 0x66;
1178 emit_rex(0,(reg),(indexreg),(basereg));
1179 *(cd->mcodeptr++) = 0x89;
1180 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1184 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1185 emit_byte_rex((reg),(indexreg),(basereg));
1186 *(cd->mcodeptr++) = 0x88;
1187 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1191 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1192 emit_rex(1,0,0,(basereg));
1193 *(cd->mcodeptr++) = 0xc7;
1194 emit_membase(cd, (basereg),(disp),0);
1199 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1200 emit_rex(1,0,0,(basereg));
1201 *(cd->mcodeptr++) = 0xc7;
1202 emit_membase32(cd, (basereg),(disp),0);
1207 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1208 emit_rex(0,0,0,(basereg));
1209 *(cd->mcodeptr++) = 0xc7;
1210 emit_membase(cd, (basereg),(disp),0);
1215 /* Always emit a REX byte, because the instruction size can be smaller when */
1216 /* all register indexes are smaller than 7. */
1217 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1218 emit_byte_rex(0,0,(basereg));
1219 *(cd->mcodeptr++) = 0xc7;
1220 emit_membase32(cd, (basereg),(disp),0);
1225 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1227 emit_rex(1,(dreg),0,(reg));
1228 *(cd->mcodeptr++) = 0x0f;
1229 *(cd->mcodeptr++) = 0xbe;
1230 /* XXX: why do reg and dreg have to be exchanged */
1231 emit_reg((dreg),(reg));
1235 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1237 emit_rex(1,(dreg),0,(reg));
1238 *(cd->mcodeptr++) = 0x0f;
1239 *(cd->mcodeptr++) = 0xbf;
1240 /* XXX: why do reg and dreg have to be exchanged */
1241 emit_reg((dreg),(reg));
1245 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1247 emit_rex(1,(dreg),0,(reg));
1248 *(cd->mcodeptr++) = 0x63;
1249 /* XXX: why do reg and dreg have to be exchanged */
1250 emit_reg((dreg),(reg));
1254 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1256 emit_rex(1,(dreg),0,(reg));
1257 *(cd->mcodeptr++) = 0x0f;
1258 *(cd->mcodeptr++) = 0xb7;
1259 /* XXX: why do reg and dreg have to be exchanged */
1260 emit_reg((dreg),(reg));
1264 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1265 emit_rex(1,(reg),(indexreg),(basereg));
1266 *(cd->mcodeptr++) = 0x0f;
1267 *(cd->mcodeptr++) = 0xbf;
1268 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1272 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1273 emit_rex(1,(reg),(indexreg),(basereg));
1274 *(cd->mcodeptr++) = 0x0f;
1275 *(cd->mcodeptr++) = 0xbe;
1276 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1280 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1281 emit_rex(1,(reg),(indexreg),(basereg));
1282 *(cd->mcodeptr++) = 0x0f;
1283 *(cd->mcodeptr++) = 0xb7;
1284 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1288 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1290 emit_rex(1,0,(indexreg),(basereg));
1291 *(cd->mcodeptr++) = 0xc7;
1292 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1297 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1299 emit_rex(0,0,(indexreg),(basereg));
1300 *(cd->mcodeptr++) = 0xc7;
1301 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1306 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1308 *(cd->mcodeptr++) = 0x66;
1309 emit_rex(0,0,(indexreg),(basereg));
1310 *(cd->mcodeptr++) = 0xc7;
1311 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1316 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1318 emit_rex(0,0,(indexreg),(basereg));
1319 *(cd->mcodeptr++) = 0xc6;
1320 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1325 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1327 emit_rex(1, dreg, 0, 0);
1328 *(cd->mcodeptr++) = 0x8b;
1329 emit_address_byte(0, dreg, 4);
1337 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1339 emit_rex(1,(reg),0,(dreg));
1340 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1341 emit_reg((reg),(dreg));
1345 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1347 emit_rex(0,(reg),0,(dreg));
1348 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1349 emit_reg((reg),(dreg));
1353 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1355 emit_rex(1,(reg),0,(basereg));
1356 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1357 emit_membase(cd, (basereg),(disp),(reg));
1361 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1363 emit_rex(0,(reg),0,(basereg));
1364 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1365 emit_membase(cd, (basereg),(disp),(reg));
1369 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1371 emit_rex(1,(reg),0,(basereg));
1372 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1373 emit_membase(cd, (basereg),(disp),(reg));
1377 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1379 emit_rex(0,(reg),0,(basereg));
1380 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1381 emit_membase(cd, (basereg),(disp),(reg));
1385 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1387 emit_rex(1,0,0,(dreg));
1388 *(cd->mcodeptr++) = 0x83;
1389 emit_reg((opc),(dreg));
1392 emit_rex(1,0,0,(dreg));
1393 *(cd->mcodeptr++) = 0x81;
1394 emit_reg((opc),(dreg));
1400 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1402 emit_rex(1,0,0,(dreg));
1403 *(cd->mcodeptr++) = 0x81;
1404 emit_reg((opc),(dreg));
1409 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1411 emit_rex(0,0,0,(dreg));
1412 *(cd->mcodeptr++) = 0x81;
1413 emit_reg((opc),(dreg));
1418 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1420 emit_rex(0,0,0,(dreg));
1421 *(cd->mcodeptr++) = 0x83;
1422 emit_reg((opc),(dreg));
1425 emit_rex(0,0,0,(dreg));
1426 *(cd->mcodeptr++) = 0x81;
1427 emit_reg((opc),(dreg));
1433 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1435 emit_rex(1,(basereg),0,0);
1436 *(cd->mcodeptr++) = 0x83;
1437 emit_membase(cd, (basereg),(disp),(opc));
1440 emit_rex(1,(basereg),0,0);
1441 *(cd->mcodeptr++) = 0x81;
1442 emit_membase(cd, (basereg),(disp),(opc));
1448 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1450 emit_rex(0,(basereg),0,0);
1451 *(cd->mcodeptr++) = 0x83;
1452 emit_membase(cd, (basereg),(disp),(opc));
1455 emit_rex(0,(basereg),0,0);
1456 *(cd->mcodeptr++) = 0x81;
1457 emit_membase(cd, (basereg),(disp),(opc));
1463 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1464 emit_rex(1,(reg),0,(dreg));
1465 *(cd->mcodeptr++) = 0x85;
1466 emit_reg((reg),(dreg));
1470 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1471 emit_rex(0,(reg),0,(dreg));
1472 *(cd->mcodeptr++) = 0x85;
1473 emit_reg((reg),(dreg));
1477 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1478 *(cd->mcodeptr++) = 0xf7;
1484 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1485 *(cd->mcodeptr++) = 0x66;
1486 *(cd->mcodeptr++) = 0xf7;
1492 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1493 *(cd->mcodeptr++) = 0xf6;
1499 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1500 emit_rex(1,(reg),0,(basereg));
1501 *(cd->mcodeptr++) = 0x8d;
1502 emit_membase(cd, (basereg),(disp),(reg));
1506 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1507 emit_rex(0,(reg),0,(basereg));
1508 *(cd->mcodeptr++) = 0x8d;
1509 emit_membase(cd, (basereg),(disp),(reg));
1514 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1516 emit_rex(0,0,0,(basereg));
1517 *(cd->mcodeptr++) = 0xff;
1518 emit_membase(cd, (basereg),(disp),0);
1523 void emit_cltd(codegendata *cd) {
1524 *(cd->mcodeptr++) = 0x99;
1528 void emit_cqto(codegendata *cd) {
1530 *(cd->mcodeptr++) = 0x99;
1535 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1536 emit_rex(1,(dreg),0,(reg));
1537 *(cd->mcodeptr++) = 0x0f;
1538 *(cd->mcodeptr++) = 0xaf;
1539 emit_reg((dreg),(reg));
1543 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1544 emit_rex(0,(dreg),0,(reg));
1545 *(cd->mcodeptr++) = 0x0f;
1546 *(cd->mcodeptr++) = 0xaf;
1547 emit_reg((dreg),(reg));
1551 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1552 emit_rex(1,(dreg),0,(basereg));
1553 *(cd->mcodeptr++) = 0x0f;
1554 *(cd->mcodeptr++) = 0xaf;
1555 emit_membase(cd, (basereg),(disp),(dreg));
1559 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1560 emit_rex(0,(dreg),0,(basereg));
1561 *(cd->mcodeptr++) = 0x0f;
1562 *(cd->mcodeptr++) = 0xaf;
1563 emit_membase(cd, (basereg),(disp),(dreg));
1567 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1568 if (IS_IMM8((imm))) {
1569 emit_rex(1,0,0,(dreg));
1570 *(cd->mcodeptr++) = 0x6b;
1574 emit_rex(1,0,0,(dreg));
1575 *(cd->mcodeptr++) = 0x69;
1582 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1583 if (IS_IMM8((imm))) {
1584 emit_rex(1,(dreg),0,(reg));
1585 *(cd->mcodeptr++) = 0x6b;
1586 emit_reg((dreg),(reg));
1589 emit_rex(1,(dreg),0,(reg));
1590 *(cd->mcodeptr++) = 0x69;
1591 emit_reg((dreg),(reg));
1597 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1598 if (IS_IMM8((imm))) {
1599 emit_rex(0,(dreg),0,(reg));
1600 *(cd->mcodeptr++) = 0x6b;
1601 emit_reg((dreg),(reg));
1604 emit_rex(0,(dreg),0,(reg));
1605 *(cd->mcodeptr++) = 0x69;
1606 emit_reg((dreg),(reg));
1612 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1613 if (IS_IMM8((imm))) {
1614 emit_rex(1,(dreg),0,(basereg));
1615 *(cd->mcodeptr++) = 0x6b;
1616 emit_membase(cd, (basereg),(disp),(dreg));
1619 emit_rex(1,(dreg),0,(basereg));
1620 *(cd->mcodeptr++) = 0x69;
1621 emit_membase(cd, (basereg),(disp),(dreg));
1627 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1628 if (IS_IMM8((imm))) {
1629 emit_rex(0,(dreg),0,(basereg));
1630 *(cd->mcodeptr++) = 0x6b;
1631 emit_membase(cd, (basereg),(disp),(dreg));
1634 emit_rex(0,(dreg),0,(basereg));
1635 *(cd->mcodeptr++) = 0x69;
1636 emit_membase(cd, (basereg),(disp),(dreg));
1642 void emit_idiv_reg(codegendata *cd, s8 reg) {
1643 emit_rex(1,0,0,(reg));
1644 *(cd->mcodeptr++) = 0xf7;
1649 void emit_idivl_reg(codegendata *cd, s8 reg) {
1650 emit_rex(0,0,0,(reg));
1651 *(cd->mcodeptr++) = 0xf7;
1657 void emit_ret(codegendata *cd) {
1658 *(cd->mcodeptr++) = 0xc3;
1666 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1667 emit_rex(1,0,0,(reg));
1668 *(cd->mcodeptr++) = 0xd3;
1669 emit_reg((opc),(reg));
1673 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1674 emit_rex(0,0,0,(reg));
1675 *(cd->mcodeptr++) = 0xd3;
1676 emit_reg((opc),(reg));
1680 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1681 emit_rex(1,0,0,(basereg));
1682 *(cd->mcodeptr++) = 0xd3;
1683 emit_membase(cd, (basereg),(disp),(opc));
1687 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1688 emit_rex(0,0,0,(basereg));
1689 *(cd->mcodeptr++) = 0xd3;
1690 emit_membase(cd, (basereg),(disp),(opc));
1694 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1696 emit_rex(1,0,0,(dreg));
1697 *(cd->mcodeptr++) = 0xd1;
1698 emit_reg((opc),(dreg));
1700 emit_rex(1,0,0,(dreg));
1701 *(cd->mcodeptr++) = 0xc1;
1702 emit_reg((opc),(dreg));
1708 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1710 emit_rex(0,0,0,(dreg));
1711 *(cd->mcodeptr++) = 0xd1;
1712 emit_reg((opc),(dreg));
1714 emit_rex(0,0,0,(dreg));
1715 *(cd->mcodeptr++) = 0xc1;
1716 emit_reg((opc),(dreg));
1722 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1724 emit_rex(1,0,0,(basereg));
1725 *(cd->mcodeptr++) = 0xd1;
1726 emit_membase(cd, (basereg),(disp),(opc));
1728 emit_rex(1,0,0,(basereg));
1729 *(cd->mcodeptr++) = 0xc1;
1730 emit_membase(cd, (basereg),(disp),(opc));
1736 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1738 emit_rex(0,0,0,(basereg));
1739 *(cd->mcodeptr++) = 0xd1;
1740 emit_membase(cd, (basereg),(disp),(opc));
1742 emit_rex(0,0,0,(basereg));
1743 *(cd->mcodeptr++) = 0xc1;
1744 emit_membase(cd, (basereg),(disp),(opc));
1754 void emit_jmp_imm(codegendata *cd, s8 imm) {
1755 *(cd->mcodeptr++) = 0xe9;
1760 void emit_jmp_reg(codegendata *cd, s8 reg) {
1761 emit_rex(0,0,0,(reg));
1762 *(cd->mcodeptr++) = 0xff;
1767 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1768 *(cd->mcodeptr++) = 0x0f;
1769 *(cd->mcodeptr++) = (0x80 + (opc));
1776 * conditional set and move operations
1779 /* we need the rex byte to get all low bytes */
1780 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1782 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1783 *(cd->mcodeptr++) = 0x0f;
1784 *(cd->mcodeptr++) = (0x90 + (opc));
1789 /* we need the rex byte to get all low bytes */
1790 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1792 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1793 *(cd->mcodeptr++) = 0x0f;
1794 *(cd->mcodeptr++) = (0x90 + (opc));
1795 emit_membase(cd, (basereg),(disp),0);
1799 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1801 emit_rex(1,(dreg),0,(reg));
1802 *(cd->mcodeptr++) = 0x0f;
1803 *(cd->mcodeptr++) = (0x40 + (opc));
1804 emit_reg((dreg),(reg));
1808 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1810 emit_rex(0,(dreg),0,(reg));
1811 *(cd->mcodeptr++) = 0x0f;
1812 *(cd->mcodeptr++) = (0x40 + (opc));
1813 emit_reg((dreg),(reg));
1817 void emit_neg_reg(codegendata *cd, s8 reg)
1819 emit_rex(1,0,0,(reg));
1820 *(cd->mcodeptr++) = 0xf7;
1825 void emit_negl_reg(codegendata *cd, s8 reg)
1827 emit_rex(0,0,0,(reg));
1828 *(cd->mcodeptr++) = 0xf7;
1833 void emit_push_reg(codegendata *cd, s8 reg) {
1834 emit_rex(0,0,0,(reg));
1835 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1839 void emit_push_imm(codegendata *cd, s8 imm) {
1840 *(cd->mcodeptr++) = 0x68;
1845 void emit_pop_reg(codegendata *cd, s8 reg) {
1846 emit_rex(0,0,0,(reg));
1847 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1851 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1852 emit_rex(1,(reg),0,(dreg));
1853 *(cd->mcodeptr++) = 0x87;
1854 emit_reg((reg),(dreg));
1858 void emit_nop(codegendata *cd) {
1859 *(cd->mcodeptr++) = 0x90;
1867 void emit_call_reg(codegendata *cd, s8 reg)
1869 emit_rex(0,0,0,(reg));
1870 *(cd->mcodeptr++) = 0xff;
1875 void emit_call_imm(codegendata *cd, s8 imm)
1877 *(cd->mcodeptr++) = 0xe8;
1882 void emit_call_mem(codegendata *cd, ptrint mem)
1884 *(cd->mcodeptr++) = 0xff;
1891 * floating point instructions (SSE2)
1893 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1894 *(cd->mcodeptr++) = 0xf2;
1895 emit_rex(0,(dreg),0,(reg));
1896 *(cd->mcodeptr++) = 0x0f;
1897 *(cd->mcodeptr++) = 0x58;
1898 emit_reg((dreg),(reg));
1902 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1903 *(cd->mcodeptr++) = 0xf3;
1904 emit_rex(0,(dreg),0,(reg));
1905 *(cd->mcodeptr++) = 0x0f;
1906 *(cd->mcodeptr++) = 0x58;
1907 emit_reg((dreg),(reg));
1911 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1912 *(cd->mcodeptr++) = 0xf3;
1913 emit_rex(1,(dreg),0,(reg));
1914 *(cd->mcodeptr++) = 0x0f;
1915 *(cd->mcodeptr++) = 0x2a;
1916 emit_reg((dreg),(reg));
1920 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1921 *(cd->mcodeptr++) = 0xf3;
1922 emit_rex(0,(dreg),0,(reg));
1923 *(cd->mcodeptr++) = 0x0f;
1924 *(cd->mcodeptr++) = 0x2a;
1925 emit_reg((dreg),(reg));
1929 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1930 *(cd->mcodeptr++) = 0xf2;
1931 emit_rex(1,(dreg),0,(reg));
1932 *(cd->mcodeptr++) = 0x0f;
1933 *(cd->mcodeptr++) = 0x2a;
1934 emit_reg((dreg),(reg));
1938 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1939 *(cd->mcodeptr++) = 0xf2;
1940 emit_rex(0,(dreg),0,(reg));
1941 *(cd->mcodeptr++) = 0x0f;
1942 *(cd->mcodeptr++) = 0x2a;
1943 emit_reg((dreg),(reg));
1947 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1948 *(cd->mcodeptr++) = 0xf3;
1949 emit_rex(0,(dreg),0,(reg));
1950 *(cd->mcodeptr++) = 0x0f;
1951 *(cd->mcodeptr++) = 0x5a;
1952 emit_reg((dreg),(reg));
1956 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1957 *(cd->mcodeptr++) = 0xf2;
1958 emit_rex(0,(dreg),0,(reg));
1959 *(cd->mcodeptr++) = 0x0f;
1960 *(cd->mcodeptr++) = 0x5a;
1961 emit_reg((dreg),(reg));
1965 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1966 *(cd->mcodeptr++) = 0xf3;
1967 emit_rex(1,(dreg),0,(reg));
1968 *(cd->mcodeptr++) = 0x0f;
1969 *(cd->mcodeptr++) = 0x2c;
1970 emit_reg((dreg),(reg));
1974 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1975 *(cd->mcodeptr++) = 0xf3;
1976 emit_rex(0,(dreg),0,(reg));
1977 *(cd->mcodeptr++) = 0x0f;
1978 *(cd->mcodeptr++) = 0x2c;
1979 emit_reg((dreg),(reg));
1983 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1984 *(cd->mcodeptr++) = 0xf2;
1985 emit_rex(1,(dreg),0,(reg));
1986 *(cd->mcodeptr++) = 0x0f;
1987 *(cd->mcodeptr++) = 0x2c;
1988 emit_reg((dreg),(reg));
1992 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1993 *(cd->mcodeptr++) = 0xf2;
1994 emit_rex(0,(dreg),0,(reg));
1995 *(cd->mcodeptr++) = 0x0f;
1996 *(cd->mcodeptr++) = 0x2c;
1997 emit_reg((dreg),(reg));
2001 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2002 *(cd->mcodeptr++) = 0xf3;
2003 emit_rex(0,(dreg),0,(reg));
2004 *(cd->mcodeptr++) = 0x0f;
2005 *(cd->mcodeptr++) = 0x5e;
2006 emit_reg((dreg),(reg));
2010 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2011 *(cd->mcodeptr++) = 0xf2;
2012 emit_rex(0,(dreg),0,(reg));
2013 *(cd->mcodeptr++) = 0x0f;
2014 *(cd->mcodeptr++) = 0x5e;
2015 emit_reg((dreg),(reg));
2019 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2020 *(cd->mcodeptr++) = 0x66;
2021 emit_rex(1,(freg),0,(reg));
2022 *(cd->mcodeptr++) = 0x0f;
2023 *(cd->mcodeptr++) = 0x6e;
2024 emit_reg((freg),(reg));
2028 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2029 *(cd->mcodeptr++) = 0x66;
2030 emit_rex(1,(freg),0,(reg));
2031 *(cd->mcodeptr++) = 0x0f;
2032 *(cd->mcodeptr++) = 0x7e;
2033 emit_reg((freg),(reg));
2037 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2038 *(cd->mcodeptr++) = 0x66;
2039 emit_rex(0,(reg),0,(basereg));
2040 *(cd->mcodeptr++) = 0x0f;
2041 *(cd->mcodeptr++) = 0x7e;
2042 emit_membase(cd, (basereg),(disp),(reg));
2046 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2047 *(cd->mcodeptr++) = 0x66;
2048 emit_rex(0,(reg),(indexreg),(basereg));
2049 *(cd->mcodeptr++) = 0x0f;
2050 *(cd->mcodeptr++) = 0x7e;
2051 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2055 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2056 *(cd->mcodeptr++) = 0x66;
2057 emit_rex(1,(dreg),0,(basereg));
2058 *(cd->mcodeptr++) = 0x0f;
2059 *(cd->mcodeptr++) = 0x6e;
2060 emit_membase(cd, (basereg),(disp),(dreg));
2064 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2065 *(cd->mcodeptr++) = 0x66;
2066 emit_rex(0,(dreg),0,(basereg));
2067 *(cd->mcodeptr++) = 0x0f;
2068 *(cd->mcodeptr++) = 0x6e;
2069 emit_membase(cd, (basereg),(disp),(dreg));
2073 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2074 *(cd->mcodeptr++) = 0x66;
2075 emit_rex(0,(dreg),(indexreg),(basereg));
2076 *(cd->mcodeptr++) = 0x0f;
2077 *(cd->mcodeptr++) = 0x6e;
2078 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2082 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2083 *(cd->mcodeptr++) = 0xf3;
2084 emit_rex(0,(dreg),0,(reg));
2085 *(cd->mcodeptr++) = 0x0f;
2086 *(cd->mcodeptr++) = 0x7e;
2087 emit_reg((dreg),(reg));
2091 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2092 *(cd->mcodeptr++) = 0x66;
2093 emit_rex(0,(reg),0,(basereg));
2094 *(cd->mcodeptr++) = 0x0f;
2095 *(cd->mcodeptr++) = 0xd6;
2096 emit_membase(cd, (basereg),(disp),(reg));
2100 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2101 *(cd->mcodeptr++) = 0xf3;
2102 emit_rex(0,(dreg),0,(basereg));
2103 *(cd->mcodeptr++) = 0x0f;
2104 *(cd->mcodeptr++) = 0x7e;
2105 emit_membase(cd, (basereg),(disp),(dreg));
2109 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2110 *(cd->mcodeptr++) = 0xf3;
2111 emit_rex(0,(reg),0,(dreg));
2112 *(cd->mcodeptr++) = 0x0f;
2113 *(cd->mcodeptr++) = 0x10;
2114 emit_reg((reg),(dreg));
2118 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2119 *(cd->mcodeptr++) = 0xf2;
2120 emit_rex(0,(reg),0,(dreg));
2121 *(cd->mcodeptr++) = 0x0f;
2122 *(cd->mcodeptr++) = 0x10;
2123 emit_reg((reg),(dreg));
2127 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2128 *(cd->mcodeptr++) = 0xf3;
2129 emit_rex(0,(reg),0,(basereg));
2130 *(cd->mcodeptr++) = 0x0f;
2131 *(cd->mcodeptr++) = 0x11;
2132 emit_membase(cd, (basereg),(disp),(reg));
2136 /* Always emit a REX byte, because the instruction size can be smaller when */
2137 /* all register indexes are smaller than 7. */
2138 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2139 *(cd->mcodeptr++) = 0xf3;
2140 emit_byte_rex((reg),0,(basereg));
2141 *(cd->mcodeptr++) = 0x0f;
2142 *(cd->mcodeptr++) = 0x11;
2143 emit_membase32(cd, (basereg),(disp),(reg));
2147 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2148 *(cd->mcodeptr++) = 0xf2;
2149 emit_rex(0,(reg),0,(basereg));
2150 *(cd->mcodeptr++) = 0x0f;
2151 *(cd->mcodeptr++) = 0x11;
2152 emit_membase(cd, (basereg),(disp),(reg));
2156 /* Always emit a REX byte, because the instruction size can be smaller when */
2157 /* all register indexes are smaller than 7. */
2158 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2159 *(cd->mcodeptr++) = 0xf2;
2160 emit_byte_rex((reg),0,(basereg));
2161 *(cd->mcodeptr++) = 0x0f;
2162 *(cd->mcodeptr++) = 0x11;
2163 emit_membase32(cd, (basereg),(disp),(reg));
2167 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2168 *(cd->mcodeptr++) = 0xf3;
2169 emit_rex(0,(dreg),0,(basereg));
2170 *(cd->mcodeptr++) = 0x0f;
2171 *(cd->mcodeptr++) = 0x10;
2172 emit_membase(cd, (basereg),(disp),(dreg));
2176 /* Always emit a REX byte, because the instruction size can be smaller when */
2177 /* all register indexes are smaller than 7. */
2178 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2179 *(cd->mcodeptr++) = 0xf3;
2180 emit_byte_rex((dreg),0,(basereg));
2181 *(cd->mcodeptr++) = 0x0f;
2182 *(cd->mcodeptr++) = 0x10;
2183 emit_membase32(cd, (basereg),(disp),(dreg));
2187 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2189 emit_rex(0,(dreg),0,(basereg));
2190 *(cd->mcodeptr++) = 0x0f;
2191 *(cd->mcodeptr++) = 0x12;
2192 emit_membase(cd, (basereg),(disp),(dreg));
2196 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2198 emit_rex(0,(reg),0,(basereg));
2199 *(cd->mcodeptr++) = 0x0f;
2200 *(cd->mcodeptr++) = 0x13;
2201 emit_membase(cd, (basereg),(disp),(reg));
2205 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2206 *(cd->mcodeptr++) = 0xf2;
2207 emit_rex(0,(dreg),0,(basereg));
2208 *(cd->mcodeptr++) = 0x0f;
2209 *(cd->mcodeptr++) = 0x10;
2210 emit_membase(cd, (basereg),(disp),(dreg));
2214 /* Always emit a REX byte, because the instruction size can be smaller when */
2215 /* all register indexes are smaller than 7. */
2216 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2217 *(cd->mcodeptr++) = 0xf2;
2218 emit_byte_rex((dreg),0,(basereg));
2219 *(cd->mcodeptr++) = 0x0f;
2220 *(cd->mcodeptr++) = 0x10;
2221 emit_membase32(cd, (basereg),(disp),(dreg));
2225 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2227 *(cd->mcodeptr++) = 0x66;
2228 emit_rex(0,(dreg),0,(basereg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x12;
2231 emit_membase(cd, (basereg),(disp),(dreg));
2235 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2237 *(cd->mcodeptr++) = 0x66;
2238 emit_rex(0,(reg),0,(basereg));
2239 *(cd->mcodeptr++) = 0x0f;
2240 *(cd->mcodeptr++) = 0x13;
2241 emit_membase(cd, (basereg),(disp),(reg));
2245 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2246 *(cd->mcodeptr++) = 0xf3;
2247 emit_rex(0,(reg),(indexreg),(basereg));
2248 *(cd->mcodeptr++) = 0x0f;
2249 *(cd->mcodeptr++) = 0x11;
2250 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2254 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2255 *(cd->mcodeptr++) = 0xf2;
2256 emit_rex(0,(reg),(indexreg),(basereg));
2257 *(cd->mcodeptr++) = 0x0f;
2258 *(cd->mcodeptr++) = 0x11;
2259 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2263 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2264 *(cd->mcodeptr++) = 0xf3;
2265 emit_rex(0,(dreg),(indexreg),(basereg));
2266 *(cd->mcodeptr++) = 0x0f;
2267 *(cd->mcodeptr++) = 0x10;
2268 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2272 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2273 *(cd->mcodeptr++) = 0xf2;
2274 emit_rex(0,(dreg),(indexreg),(basereg));
2275 *(cd->mcodeptr++) = 0x0f;
2276 *(cd->mcodeptr++) = 0x10;
2277 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2281 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2282 *(cd->mcodeptr++) = 0xf3;
2283 emit_rex(0,(dreg),0,(reg));
2284 *(cd->mcodeptr++) = 0x0f;
2285 *(cd->mcodeptr++) = 0x59;
2286 emit_reg((dreg),(reg));
2290 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2291 *(cd->mcodeptr++) = 0xf2;
2292 emit_rex(0,(dreg),0,(reg));
2293 *(cd->mcodeptr++) = 0x0f;
2294 *(cd->mcodeptr++) = 0x59;
2295 emit_reg((dreg),(reg));
2299 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2300 *(cd->mcodeptr++) = 0xf3;
2301 emit_rex(0,(dreg),0,(reg));
2302 *(cd->mcodeptr++) = 0x0f;
2303 *(cd->mcodeptr++) = 0x5c;
2304 emit_reg((dreg),(reg));
2308 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2309 *(cd->mcodeptr++) = 0xf2;
2310 emit_rex(0,(dreg),0,(reg));
2311 *(cd->mcodeptr++) = 0x0f;
2312 *(cd->mcodeptr++) = 0x5c;
2313 emit_reg((dreg),(reg));
2317 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2318 emit_rex(0,(dreg),0,(reg));
2319 *(cd->mcodeptr++) = 0x0f;
2320 *(cd->mcodeptr++) = 0x2e;
2321 emit_reg((dreg),(reg));
2325 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2326 *(cd->mcodeptr++) = 0x66;
2327 emit_rex(0,(dreg),0,(reg));
2328 *(cd->mcodeptr++) = 0x0f;
2329 *(cd->mcodeptr++) = 0x2e;
2330 emit_reg((dreg),(reg));
2334 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2335 emit_rex(0,(dreg),0,(reg));
2336 *(cd->mcodeptr++) = 0x0f;
2337 *(cd->mcodeptr++) = 0x57;
2338 emit_reg((dreg),(reg));
2342 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2343 emit_rex(0,(dreg),0,(basereg));
2344 *(cd->mcodeptr++) = 0x0f;
2345 *(cd->mcodeptr++) = 0x57;
2346 emit_membase(cd, (basereg),(disp),(dreg));
2350 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2351 *(cd->mcodeptr++) = 0x66;
2352 emit_rex(0,(dreg),0,(reg));
2353 *(cd->mcodeptr++) = 0x0f;
2354 *(cd->mcodeptr++) = 0x57;
2355 emit_reg((dreg),(reg));
2359 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2360 *(cd->mcodeptr++) = 0x66;
2361 emit_rex(0,(dreg),0,(basereg));
2362 *(cd->mcodeptr++) = 0x0f;
2363 *(cd->mcodeptr++) = 0x57;
2364 emit_membase(cd, (basereg),(disp),(dreg));
2368 /* system instructions ********************************************************/
2370 void emit_rdtsc(codegendata *cd)
2372 *(cd->mcodeptr++) = 0x0f;
2373 *(cd->mcodeptr++) = 0x31;
2378 * These are local overrides for various environment variables in Emacs.
2379 * Please do not remove this and leave it at the end of the file, where
2380 * Emacs will automagically detect them.
2381 * ---------------------------------------------------------------------
2384 * indent-tabs-mode: t