1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8318 2007-08-16 10:05:34Z michi $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #include "threads/lock-common.h"
44 #include "vm/builtin.h"
45 #include "vm/exceptions.h"
47 #include "vm/jit/abi.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
55 #include "vmcore/options.h"
58 /* emit_load *******************************************************************
60 Emits a possible load of an operand.
62 *******************************************************************************/
64 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
70 /* get required compiler data */
74 if (IS_INMEMORY(src->flags)) {
77 disp = src->vv.regoff;
81 M_ILD(tempreg, REG_SP, disp);
85 M_LLD(tempreg, REG_SP, disp);
88 M_FLD(tempreg, REG_SP, disp);
91 M_DLD(tempreg, REG_SP, disp);
94 vm_abort("emit_load: unknown type %d", src->type);
100 reg = src->vv.regoff;
106 /* emit_store ******************************************************************
108 This function generates the code to store the result of an
109 operation back into a spilled pseudo-variable. If the
110 pseudo-variable has not been spilled in the first place, this
111 function will generate nothing.
113 *******************************************************************************/
115 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
124 /* get required compiler data */
129 /* do we have to generate a conditional move? */
131 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
132 /* the passed register d is actually the source register */
136 /* Only pass the opcode to codegen_reg_of_var to get the real
137 destination register. */
139 opcode = iptr->opc & ICMD_OPCODE_MASK;
141 /* get the real destination register */
143 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
145 /* and emit the conditional move */
147 emit_cmovxx(cd, iptr, s, d);
151 if (IS_INMEMORY(dst->flags)) {
154 disp = dst->vv.regoff;
160 M_LST(d, REG_SP, disp);
163 M_FST(d, REG_SP, disp);
166 M_DST(d, REG_SP, disp);
169 vm_abort("emit_store: unknown type %d", dst->type);
175 /* emit_copy *******************************************************************
177 Generates a register/memory to register/memory copy.
179 *******************************************************************************/
181 void emit_copy(jitdata *jd, instruction *iptr)
188 /* get required compiler data */
192 /* get source and destination variables */
194 src = VAROP(iptr->s1);
195 dst = VAROP(iptr->dst);
197 if ((src->vv.regoff != dst->vv.regoff) ||
198 ((src->flags ^ dst->flags) & INMEMORY)) {
200 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
201 /* emit nothing, as the value won't be used anyway */
205 /* If one of the variables resides in memory, we can eliminate
206 the register move from/to the temporary register with the
207 order of getting the destination register and the load. */
209 if (IS_INMEMORY(src->flags)) {
210 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
211 s1 = emit_load(jd, iptr, src, d);
214 s1 = emit_load(jd, iptr, src, REG_IFTMP);
215 d = codegen_reg_of_var(iptr->opc, dst, s1);
230 vm_abort("emit_copy: unknown type %d", src->type);
234 emit_store(jd, iptr, dst, d);
239 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
242 switch (iptr->flags.fields.condition) {
266 /* emit_branch *****************************************************************
268 Emits the code for conditional and unconditional branchs.
270 *******************************************************************************/
272 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
276 /* NOTE: A displacement overflow cannot happen. */
278 /* check which branch to generate */
280 if (condition == BRANCH_UNCONDITIONAL) {
282 /* calculate the different displacements */
284 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
286 M_JMP_IMM(branchdisp);
289 /* calculate the different displacements */
291 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
325 vm_abort("emit_branch: unknown condition %d", condition);
331 /* emit_arithmetic_check *******************************************************
333 Emit an ArithmeticException check.
335 *******************************************************************************/
337 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
339 if (INSTRUCTION_MUST_CHECK(iptr)) {
342 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
347 /* emit_arrayindexoutofbounds_check ********************************************
349 Emit a ArrayIndexOutOfBoundsException check.
351 *******************************************************************************/
353 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
355 if (INSTRUCTION_MUST_CHECK(iptr)) {
356 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
357 M_ICMP(REG_ITMP3, s2);
359 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
364 /* emit_classcast_check ********************************************************
366 Emit a ClassCastException check.
368 *******************************************************************************/
370 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
372 if (INSTRUCTION_MUST_CHECK(iptr)) {
384 vm_abort("emit_classcast_check: unknown condition %d", condition);
386 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
391 /* emit_nullpointer_check ******************************************************
393 Emit a NullPointerException check.
395 *******************************************************************************/
397 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
399 if (INSTRUCTION_MUST_CHECK(iptr)) {
402 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
407 /* emit_exception_check ********************************************************
409 Emit an Exception check.
411 *******************************************************************************/
413 void emit_exception_check(codegendata *cd, instruction *iptr)
415 if (INSTRUCTION_MUST_CHECK(iptr)) {
418 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
423 /* emit_patcher_stubs **********************************************************
425 Generates the code for the patcher stubs.
427 *******************************************************************************/
429 void emit_patcher_stubs(jitdata *jd)
439 /* get required compiler data */
443 /* generate code patching stub call code */
447 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
448 /* check size of code segment */
452 /* Get machine code which is patched back in later. A
453 `call rel32' is 5 bytes long (but read 8 bytes). */
455 savedmcodeptr = cd->mcodebase + pref->branchpos;
456 mcode = *((u8 *) savedmcodeptr);
458 /* patch in `call rel32' to call the following code */
460 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
461 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
463 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
465 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
467 /* move pointer to java_objectheader onto stack */
469 #if defined(ENABLE_THREADS)
470 /* create a virtual java_objectheader */
472 (void) dseg_add_unique_address(cd, NULL); /* flcword */
473 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
474 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
476 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
482 /* move machine code bytes and classinfo pointer into registers */
484 M_MOV_IMM(mcode, REG_ITMP3);
487 M_MOV_IMM(pref->ref, REG_ITMP3);
490 M_MOV_IMM(pref->disp, REG_ITMP3);
493 M_MOV_IMM(pref->patcher, REG_ITMP3);
496 if (targetdisp == 0) {
497 targetdisp = cd->mcodeptr - cd->mcodebase;
499 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
503 M_JMP_IMM((cd->mcodebase + targetdisp) -
504 (cd->mcodeptr + PATCHER_CALL_SIZE));
510 /* emit_trap *******************************************************************
512 Emit a trap instruction and return the original machine code.
514 *******************************************************************************/
516 uint32_t emit_trap(codegendata *cd)
520 /* Get machine code which is patched back in later. The
521 trap is 1 instruction word long. */
523 mcode = *((uint32_t *) cd->mcodeptr);
531 /* emit_verbosecall_enter ******************************************************
533 Generates the code for the call trace.
535 *******************************************************************************/
538 void emit_verbosecall_enter(jitdata *jd)
546 /* get required compiler data */
554 /* mark trace code */
558 /* additional +1 is for 16-byte stack alignment */
560 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
562 /* save argument registers */
564 for (i = 0; i < INT_ARG_CNT; i++)
565 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
567 for (i = 0; i < FLT_ARG_CNT; i++)
568 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
570 /* save temporary registers for leaf methods */
572 if (jd->isleafmethod) {
573 for (i = 0; i < INT_TMP_CNT; i++)
574 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
576 for (i = 0; i < FLT_TMP_CNT; i++)
577 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
580 /* show integer hex code for float arguments */
582 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
583 /* If the paramtype is a float, we have to right shift all
584 following integer registers. */
586 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
587 for (k = INT_ARG_CNT - 2; k >= i; k--)
588 M_MOV(abi_registers_integer_argument[k],
589 abi_registers_integer_argument[k + 1]);
591 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
592 abi_registers_integer_argument[i]);
597 M_MOV_IMM(m, REG_ITMP2);
598 M_AST(REG_ITMP2, REG_SP, 0 * 8);
599 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
602 /* restore argument registers */
604 for (i = 0; i < INT_ARG_CNT; i++)
605 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
607 for (i = 0; i < FLT_ARG_CNT; i++)
608 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
610 /* restore temporary registers for leaf methods */
612 if (jd->isleafmethod) {
613 for (i = 0; i < INT_TMP_CNT; i++)
614 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
616 for (i = 0; i < FLT_TMP_CNT; i++)
617 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
620 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
622 /* mark trace code */
626 #endif /* !defined(NDEBUG) */
629 /* emit_verbosecall_exit *******************************************************
631 Generates the code for the call trace.
633 *******************************************************************************/
636 void emit_verbosecall_exit(jitdata *jd)
642 /* get required compiler data */
648 /* mark trace code */
652 M_ASUB_IMM(2 * 8, REG_SP);
654 M_LST(REG_RESULT, REG_SP, 0 * 8);
655 M_DST(REG_FRESULT, REG_SP, 1 * 8);
657 M_INTMOVE(REG_RESULT, REG_A0);
658 M_FLTMOVE(REG_FRESULT, REG_FA0);
659 M_FLTMOVE(REG_FRESULT, REG_FA1);
660 M_MOV_IMM(m, REG_A1);
662 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
665 M_LLD(REG_RESULT, REG_SP, 0 * 8);
666 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
668 M_AADD_IMM(2 * 8, REG_SP);
670 /* mark trace code */
674 #endif /* !defined(NDEBUG) */
677 /* code generation functions **************************************************/
679 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
681 if ((basereg == REG_SP) || (basereg == R12)) {
683 emit_address_byte(0, dreg, REG_SP);
684 emit_address_byte(0, REG_SP, REG_SP);
686 } else if (IS_IMM8(disp)) {
687 emit_address_byte(1, dreg, REG_SP);
688 emit_address_byte(0, REG_SP, REG_SP);
692 emit_address_byte(2, dreg, REG_SP);
693 emit_address_byte(0, REG_SP, REG_SP);
697 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
698 emit_address_byte(0,(dreg),(basereg));
700 } else if ((basereg) == RIP) {
701 emit_address_byte(0, dreg, RBP);
706 emit_address_byte(1, dreg, basereg);
710 emit_address_byte(2, dreg, basereg);
717 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
719 if ((basereg == REG_SP) || (basereg == R12)) {
720 emit_address_byte(2, dreg, REG_SP);
721 emit_address_byte(0, REG_SP, REG_SP);
725 emit_address_byte(2, dreg, basereg);
731 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
734 emit_address_byte(0, reg, 4);
735 emit_address_byte(scale, indexreg, 5);
738 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
739 emit_address_byte(0, reg, 4);
740 emit_address_byte(scale, indexreg, basereg);
742 else if (IS_IMM8(disp)) {
743 emit_address_byte(1, reg, 4);
744 emit_address_byte(scale, indexreg, basereg);
748 emit_address_byte(2, reg, 4);
749 emit_address_byte(scale, indexreg, basereg);
755 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
758 varinfo *v_s1,*v_s2,*v_dst;
761 /* get required compiler data */
765 v_s1 = VAROP(iptr->s1);
766 v_s2 = VAROP(iptr->sx.s23.s2);
767 v_dst = VAROP(iptr->dst);
769 s1 = v_s1->vv.regoff;
770 s2 = v_s2->vv.regoff;
771 d = v_dst->vv.regoff;
773 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
775 if (IS_INMEMORY(v_dst->flags)) {
776 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
778 M_ILD(RCX, REG_SP, s2);
779 emit_shiftl_membase(cd, shift_op, REG_SP, d);
782 M_ILD(RCX, REG_SP, s2);
783 M_ILD(REG_ITMP2, REG_SP, s1);
784 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
785 M_IST(REG_ITMP2, REG_SP, d);
788 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
789 /* s1 may be equal to RCX */
792 M_ILD(REG_ITMP1, REG_SP, s2);
793 M_IST(s1, REG_SP, d);
794 M_INTMOVE(REG_ITMP1, RCX);
797 M_IST(s1, REG_SP, d);
798 M_ILD(RCX, REG_SP, s2);
802 M_ILD(RCX, REG_SP, s2);
803 M_IST(s1, REG_SP, d);
806 emit_shiftl_membase(cd, shift_op, REG_SP, d);
808 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
811 emit_shiftl_membase(cd, shift_op, REG_SP, d);
815 M_ILD(REG_ITMP2, REG_SP, s1);
816 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
817 M_IST(REG_ITMP2, REG_SP, d);
821 /* s1 may be equal to RCX */
822 M_IST(s1, REG_SP, d);
824 emit_shiftl_membase(cd, shift_op, REG_SP, d);
827 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
835 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
836 M_ILD(RCX, REG_SP, s2);
837 M_ILD(d, REG_SP, s1);
838 emit_shiftl_reg(cd, shift_op, d);
840 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
841 /* s1 may be equal to RCX */
843 M_ILD(RCX, REG_SP, s2);
844 emit_shiftl_reg(cd, shift_op, d);
846 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
848 M_ILD(d, REG_SP, s1);
849 emit_shiftl_reg(cd, shift_op, d);
852 /* s1 may be equal to RCX */
855 /* d cannot be used to backup s1 since this would
857 M_INTMOVE(s1, REG_ITMP3);
859 M_INTMOVE(REG_ITMP3, d);
867 /* d may be equal to s2 */
871 emit_shiftl_reg(cd, shift_op, d);
875 M_INTMOVE(REG_ITMP3, RCX);
877 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
882 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
885 varinfo *v_s1,*v_s2,*v_dst;
888 /* get required compiler data */
892 v_s1 = VAROP(iptr->s1);
893 v_s2 = VAROP(iptr->sx.s23.s2);
894 v_dst = VAROP(iptr->dst);
896 s1 = v_s1->vv.regoff;
897 s2 = v_s2->vv.regoff;
898 d = v_dst->vv.regoff;
900 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
902 if (IS_INMEMORY(v_dst->flags)) {
903 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
905 M_ILD(RCX, REG_SP, s2);
906 emit_shift_membase(cd, shift_op, REG_SP, d);
909 M_ILD(RCX, REG_SP, s2);
910 M_LLD(REG_ITMP2, REG_SP, s1);
911 emit_shift_reg(cd, shift_op, REG_ITMP2);
912 M_LST(REG_ITMP2, REG_SP, d);
915 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
916 /* s1 may be equal to RCX */
919 M_ILD(REG_ITMP1, REG_SP, s2);
920 M_LST(s1, REG_SP, d);
921 M_INTMOVE(REG_ITMP1, RCX);
924 M_LST(s1, REG_SP, d);
925 M_ILD(RCX, REG_SP, s2);
929 M_ILD(RCX, REG_SP, s2);
930 M_LST(s1, REG_SP, d);
933 emit_shift_membase(cd, shift_op, REG_SP, d);
935 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
938 emit_shift_membase(cd, shift_op, REG_SP, d);
942 M_LLD(REG_ITMP2, REG_SP, s1);
943 emit_shift_reg(cd, shift_op, REG_ITMP2);
944 M_LST(REG_ITMP2, REG_SP, d);
948 /* s1 may be equal to RCX */
949 M_LST(s1, REG_SP, d);
951 emit_shift_membase(cd, shift_op, REG_SP, d);
954 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
962 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
963 M_ILD(RCX, REG_SP, s2);
964 M_LLD(d, REG_SP, s1);
965 emit_shift_reg(cd, shift_op, d);
967 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
968 /* s1 may be equal to RCX */
970 M_ILD(RCX, REG_SP, s2);
971 emit_shift_reg(cd, shift_op, d);
973 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
975 M_LLD(d, REG_SP, s1);
976 emit_shift_reg(cd, shift_op, d);
979 /* s1 may be equal to RCX */
982 /* d cannot be used to backup s1 since this would
984 M_INTMOVE(s1, REG_ITMP3);
986 M_INTMOVE(REG_ITMP3, d);
994 /* d may be equal to s2 */
998 emit_shift_reg(cd, shift_op, d);
1002 M_INTMOVE(REG_ITMP3, RCX);
1004 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1009 /* low-level code emitter functions *******************************************/
1011 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1013 emit_rex(1,(reg),0,(dreg));
1014 *(cd->mcodeptr++) = 0x89;
1015 emit_reg((reg),(dreg));
1019 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1021 emit_rex(1,0,0,(reg));
1022 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1027 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1029 emit_rex(0,(reg),0,(dreg));
1030 *(cd->mcodeptr++) = 0x89;
1031 emit_reg((reg),(dreg));
1035 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1036 emit_rex(0,0,0,(reg));
1037 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1042 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1043 emit_rex(1,(reg),0,(basereg));
1044 *(cd->mcodeptr++) = 0x8b;
1045 emit_membase(cd, (basereg),(disp),(reg));
1050 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1051 * constant membase immediate length of 32bit
1053 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1054 emit_rex(1,(reg),0,(basereg));
1055 *(cd->mcodeptr++) = 0x8b;
1056 emit_membase32(cd, (basereg),(disp),(reg));
1060 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1062 emit_rex(0,(reg),0,(basereg));
1063 *(cd->mcodeptr++) = 0x8b;
1064 emit_membase(cd, (basereg),(disp),(reg));
1068 /* ATTENTION: Always emit a REX byte, because the instruction size can
1069 be smaller when all register indexes are smaller than 7. */
1070 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1072 emit_byte_rex((reg),0,(basereg));
1073 *(cd->mcodeptr++) = 0x8b;
1074 emit_membase32(cd, (basereg),(disp),(reg));
1078 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1079 emit_rex(1,(reg),0,(basereg));
1080 *(cd->mcodeptr++) = 0x89;
1081 emit_membase(cd, (basereg),(disp),(reg));
1085 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1086 emit_rex(1,(reg),0,(basereg));
1087 *(cd->mcodeptr++) = 0x89;
1088 emit_membase32(cd, (basereg),(disp),(reg));
1092 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1093 emit_rex(0,(reg),0,(basereg));
1094 *(cd->mcodeptr++) = 0x89;
1095 emit_membase(cd, (basereg),(disp),(reg));
1099 /* Always emit a REX byte, because the instruction size can be smaller when */
1100 /* all register indexes are smaller than 7. */
1101 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1102 emit_byte_rex((reg),0,(basereg));
1103 *(cd->mcodeptr++) = 0x89;
1104 emit_membase32(cd, (basereg),(disp),(reg));
1108 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1109 emit_rex(1,(reg),(indexreg),(basereg));
1110 *(cd->mcodeptr++) = 0x8b;
1111 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1115 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1116 emit_rex(0,(reg),(indexreg),(basereg));
1117 *(cd->mcodeptr++) = 0x8b;
1118 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1122 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1123 emit_rex(1,(reg),(indexreg),(basereg));
1124 *(cd->mcodeptr++) = 0x89;
1125 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1129 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1130 emit_rex(0,(reg),(indexreg),(basereg));
1131 *(cd->mcodeptr++) = 0x89;
1132 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1136 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1137 *(cd->mcodeptr++) = 0x66;
1138 emit_rex(0,(reg),(indexreg),(basereg));
1139 *(cd->mcodeptr++) = 0x89;
1140 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1144 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1145 emit_byte_rex((reg),(indexreg),(basereg));
1146 *(cd->mcodeptr++) = 0x88;
1147 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1151 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1152 emit_rex(1,0,0,(basereg));
1153 *(cd->mcodeptr++) = 0xc7;
1154 emit_membase(cd, (basereg),(disp),0);
1159 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1160 emit_rex(1,0,0,(basereg));
1161 *(cd->mcodeptr++) = 0xc7;
1162 emit_membase32(cd, (basereg),(disp),0);
1167 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1168 emit_rex(0,0,0,(basereg));
1169 *(cd->mcodeptr++) = 0xc7;
1170 emit_membase(cd, (basereg),(disp),0);
1175 /* Always emit a REX byte, because the instruction size can be smaller when */
1176 /* all register indexes are smaller than 7. */
1177 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1178 emit_byte_rex(0,0,(basereg));
1179 *(cd->mcodeptr++) = 0xc7;
1180 emit_membase32(cd, (basereg),(disp),0);
1185 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1187 emit_rex(1,(dreg),0,(reg));
1188 *(cd->mcodeptr++) = 0x0f;
1189 *(cd->mcodeptr++) = 0xbe;
1190 /* XXX: why do reg and dreg have to be exchanged */
1191 emit_reg((dreg),(reg));
1195 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1197 emit_rex(1,(dreg),0,(reg));
1198 *(cd->mcodeptr++) = 0x0f;
1199 *(cd->mcodeptr++) = 0xbf;
1200 /* XXX: why do reg and dreg have to be exchanged */
1201 emit_reg((dreg),(reg));
1205 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1207 emit_rex(1,(dreg),0,(reg));
1208 *(cd->mcodeptr++) = 0x63;
1209 /* XXX: why do reg and dreg have to be exchanged */
1210 emit_reg((dreg),(reg));
1214 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1216 emit_rex(1,(dreg),0,(reg));
1217 *(cd->mcodeptr++) = 0x0f;
1218 *(cd->mcodeptr++) = 0xb7;
1219 /* XXX: why do reg and dreg have to be exchanged */
1220 emit_reg((dreg),(reg));
1224 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1225 emit_rex(1,(reg),(indexreg),(basereg));
1226 *(cd->mcodeptr++) = 0x0f;
1227 *(cd->mcodeptr++) = 0xbf;
1228 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1232 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1233 emit_rex(1,(reg),(indexreg),(basereg));
1234 *(cd->mcodeptr++) = 0x0f;
1235 *(cd->mcodeptr++) = 0xbe;
1236 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1240 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1241 emit_rex(1,(reg),(indexreg),(basereg));
1242 *(cd->mcodeptr++) = 0x0f;
1243 *(cd->mcodeptr++) = 0xb7;
1244 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1248 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1250 emit_rex(1,0,(indexreg),(basereg));
1251 *(cd->mcodeptr++) = 0xc7;
1252 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1257 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1259 emit_rex(0,0,(indexreg),(basereg));
1260 *(cd->mcodeptr++) = 0xc7;
1261 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1266 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1268 *(cd->mcodeptr++) = 0x66;
1269 emit_rex(0,0,(indexreg),(basereg));
1270 *(cd->mcodeptr++) = 0xc7;
1271 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1276 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1278 emit_rex(0,0,(indexreg),(basereg));
1279 *(cd->mcodeptr++) = 0xc6;
1280 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1285 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1287 emit_rex(1, dreg, 0, 0);
1288 *(cd->mcodeptr++) = 0x8b;
1289 emit_address_byte(0, dreg, 4);
1297 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1299 emit_rex(1,(reg),0,(dreg));
1300 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1301 emit_reg((reg),(dreg));
1305 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1307 emit_rex(0,(reg),0,(dreg));
1308 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1309 emit_reg((reg),(dreg));
1313 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1315 emit_rex(1,(reg),0,(basereg));
1316 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1317 emit_membase(cd, (basereg),(disp),(reg));
1321 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1323 emit_rex(0,(reg),0,(basereg));
1324 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1325 emit_membase(cd, (basereg),(disp),(reg));
1329 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1331 emit_rex(1,(reg),0,(basereg));
1332 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1333 emit_membase(cd, (basereg),(disp),(reg));
1337 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1339 emit_rex(0,(reg),0,(basereg));
1340 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1341 emit_membase(cd, (basereg),(disp),(reg));
1345 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1347 emit_rex(1,0,0,(dreg));
1348 *(cd->mcodeptr++) = 0x83;
1349 emit_reg((opc),(dreg));
1352 emit_rex(1,0,0,(dreg));
1353 *(cd->mcodeptr++) = 0x81;
1354 emit_reg((opc),(dreg));
1360 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1362 emit_rex(1,0,0,(dreg));
1363 *(cd->mcodeptr++) = 0x81;
1364 emit_reg((opc),(dreg));
1369 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1371 emit_rex(0,0,0,(dreg));
1372 *(cd->mcodeptr++) = 0x81;
1373 emit_reg((opc),(dreg));
1378 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1380 emit_rex(0,0,0,(dreg));
1381 *(cd->mcodeptr++) = 0x83;
1382 emit_reg((opc),(dreg));
1385 emit_rex(0,0,0,(dreg));
1386 *(cd->mcodeptr++) = 0x81;
1387 emit_reg((opc),(dreg));
1393 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1395 emit_rex(1,(basereg),0,0);
1396 *(cd->mcodeptr++) = 0x83;
1397 emit_membase(cd, (basereg),(disp),(opc));
1400 emit_rex(1,(basereg),0,0);
1401 *(cd->mcodeptr++) = 0x81;
1402 emit_membase(cd, (basereg),(disp),(opc));
1408 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1410 emit_rex(0,(basereg),0,0);
1411 *(cd->mcodeptr++) = 0x83;
1412 emit_membase(cd, (basereg),(disp),(opc));
1415 emit_rex(0,(basereg),0,0);
1416 *(cd->mcodeptr++) = 0x81;
1417 emit_membase(cd, (basereg),(disp),(opc));
1423 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1424 emit_rex(1,(reg),0,(dreg));
1425 *(cd->mcodeptr++) = 0x85;
1426 emit_reg((reg),(dreg));
1430 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1431 emit_rex(0,(reg),0,(dreg));
1432 *(cd->mcodeptr++) = 0x85;
1433 emit_reg((reg),(dreg));
1437 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1438 *(cd->mcodeptr++) = 0xf7;
1444 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1445 *(cd->mcodeptr++) = 0x66;
1446 *(cd->mcodeptr++) = 0xf7;
1452 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1453 *(cd->mcodeptr++) = 0xf6;
1459 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1460 emit_rex(1,(reg),0,(basereg));
1461 *(cd->mcodeptr++) = 0x8d;
1462 emit_membase(cd, (basereg),(disp),(reg));
1466 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1467 emit_rex(0,(reg),0,(basereg));
1468 *(cd->mcodeptr++) = 0x8d;
1469 emit_membase(cd, (basereg),(disp),(reg));
1474 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1476 emit_rex(0,0,0,(basereg));
1477 *(cd->mcodeptr++) = 0xff;
1478 emit_membase(cd, (basereg),(disp),0);
1483 void emit_cltd(codegendata *cd) {
1484 *(cd->mcodeptr++) = 0x99;
1488 void emit_cqto(codegendata *cd) {
1490 *(cd->mcodeptr++) = 0x99;
1495 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1496 emit_rex(1,(dreg),0,(reg));
1497 *(cd->mcodeptr++) = 0x0f;
1498 *(cd->mcodeptr++) = 0xaf;
1499 emit_reg((dreg),(reg));
1503 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1504 emit_rex(0,(dreg),0,(reg));
1505 *(cd->mcodeptr++) = 0x0f;
1506 *(cd->mcodeptr++) = 0xaf;
1507 emit_reg((dreg),(reg));
1511 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1512 emit_rex(1,(dreg),0,(basereg));
1513 *(cd->mcodeptr++) = 0x0f;
1514 *(cd->mcodeptr++) = 0xaf;
1515 emit_membase(cd, (basereg),(disp),(dreg));
1519 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1520 emit_rex(0,(dreg),0,(basereg));
1521 *(cd->mcodeptr++) = 0x0f;
1522 *(cd->mcodeptr++) = 0xaf;
1523 emit_membase(cd, (basereg),(disp),(dreg));
1527 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1528 if (IS_IMM8((imm))) {
1529 emit_rex(1,0,0,(dreg));
1530 *(cd->mcodeptr++) = 0x6b;
1534 emit_rex(1,0,0,(dreg));
1535 *(cd->mcodeptr++) = 0x69;
1542 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1543 if (IS_IMM8((imm))) {
1544 emit_rex(1,(dreg),0,(reg));
1545 *(cd->mcodeptr++) = 0x6b;
1546 emit_reg((dreg),(reg));
1549 emit_rex(1,(dreg),0,(reg));
1550 *(cd->mcodeptr++) = 0x69;
1551 emit_reg((dreg),(reg));
1557 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1558 if (IS_IMM8((imm))) {
1559 emit_rex(0,(dreg),0,(reg));
1560 *(cd->mcodeptr++) = 0x6b;
1561 emit_reg((dreg),(reg));
1564 emit_rex(0,(dreg),0,(reg));
1565 *(cd->mcodeptr++) = 0x69;
1566 emit_reg((dreg),(reg));
1572 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1573 if (IS_IMM8((imm))) {
1574 emit_rex(1,(dreg),0,(basereg));
1575 *(cd->mcodeptr++) = 0x6b;
1576 emit_membase(cd, (basereg),(disp),(dreg));
1579 emit_rex(1,(dreg),0,(basereg));
1580 *(cd->mcodeptr++) = 0x69;
1581 emit_membase(cd, (basereg),(disp),(dreg));
1587 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1588 if (IS_IMM8((imm))) {
1589 emit_rex(0,(dreg),0,(basereg));
1590 *(cd->mcodeptr++) = 0x6b;
1591 emit_membase(cd, (basereg),(disp),(dreg));
1594 emit_rex(0,(dreg),0,(basereg));
1595 *(cd->mcodeptr++) = 0x69;
1596 emit_membase(cd, (basereg),(disp),(dreg));
1602 void emit_idiv_reg(codegendata *cd, s8 reg) {
1603 emit_rex(1,0,0,(reg));
1604 *(cd->mcodeptr++) = 0xf7;
1609 void emit_idivl_reg(codegendata *cd, s8 reg) {
1610 emit_rex(0,0,0,(reg));
1611 *(cd->mcodeptr++) = 0xf7;
1617 void emit_ret(codegendata *cd) {
1618 *(cd->mcodeptr++) = 0xc3;
1626 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1627 emit_rex(1,0,0,(reg));
1628 *(cd->mcodeptr++) = 0xd3;
1629 emit_reg((opc),(reg));
1633 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1634 emit_rex(0,0,0,(reg));
1635 *(cd->mcodeptr++) = 0xd3;
1636 emit_reg((opc),(reg));
1640 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1641 emit_rex(1,0,0,(basereg));
1642 *(cd->mcodeptr++) = 0xd3;
1643 emit_membase(cd, (basereg),(disp),(opc));
1647 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1648 emit_rex(0,0,0,(basereg));
1649 *(cd->mcodeptr++) = 0xd3;
1650 emit_membase(cd, (basereg),(disp),(opc));
1654 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1656 emit_rex(1,0,0,(dreg));
1657 *(cd->mcodeptr++) = 0xd1;
1658 emit_reg((opc),(dreg));
1660 emit_rex(1,0,0,(dreg));
1661 *(cd->mcodeptr++) = 0xc1;
1662 emit_reg((opc),(dreg));
1668 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1670 emit_rex(0,0,0,(dreg));
1671 *(cd->mcodeptr++) = 0xd1;
1672 emit_reg((opc),(dreg));
1674 emit_rex(0,0,0,(dreg));
1675 *(cd->mcodeptr++) = 0xc1;
1676 emit_reg((opc),(dreg));
1682 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1684 emit_rex(1,0,0,(basereg));
1685 *(cd->mcodeptr++) = 0xd1;
1686 emit_membase(cd, (basereg),(disp),(opc));
1688 emit_rex(1,0,0,(basereg));
1689 *(cd->mcodeptr++) = 0xc1;
1690 emit_membase(cd, (basereg),(disp),(opc));
1696 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1698 emit_rex(0,0,0,(basereg));
1699 *(cd->mcodeptr++) = 0xd1;
1700 emit_membase(cd, (basereg),(disp),(opc));
1702 emit_rex(0,0,0,(basereg));
1703 *(cd->mcodeptr++) = 0xc1;
1704 emit_membase(cd, (basereg),(disp),(opc));
1714 void emit_jmp_imm(codegendata *cd, s8 imm) {
1715 *(cd->mcodeptr++) = 0xe9;
1720 void emit_jmp_reg(codegendata *cd, s8 reg) {
1721 emit_rex(0,0,0,(reg));
1722 *(cd->mcodeptr++) = 0xff;
1727 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1728 *(cd->mcodeptr++) = 0x0f;
1729 *(cd->mcodeptr++) = (0x80 + (opc));
1736 * conditional set and move operations
1739 /* we need the rex byte to get all low bytes */
1740 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1742 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1743 *(cd->mcodeptr++) = 0x0f;
1744 *(cd->mcodeptr++) = (0x90 + (opc));
1749 /* we need the rex byte to get all low bytes */
1750 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1752 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1753 *(cd->mcodeptr++) = 0x0f;
1754 *(cd->mcodeptr++) = (0x90 + (opc));
1755 emit_membase(cd, (basereg),(disp),0);
1759 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1761 emit_rex(1,(dreg),0,(reg));
1762 *(cd->mcodeptr++) = 0x0f;
1763 *(cd->mcodeptr++) = (0x40 + (opc));
1764 emit_reg((dreg),(reg));
1768 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1770 emit_rex(0,(dreg),0,(reg));
1771 *(cd->mcodeptr++) = 0x0f;
1772 *(cd->mcodeptr++) = (0x40 + (opc));
1773 emit_reg((dreg),(reg));
1777 void emit_neg_reg(codegendata *cd, s8 reg)
1779 emit_rex(1,0,0,(reg));
1780 *(cd->mcodeptr++) = 0xf7;
1785 void emit_negl_reg(codegendata *cd, s8 reg)
1787 emit_rex(0,0,0,(reg));
1788 *(cd->mcodeptr++) = 0xf7;
1793 void emit_push_reg(codegendata *cd, s8 reg) {
1794 emit_rex(0,0,0,(reg));
1795 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1799 void emit_push_imm(codegendata *cd, s8 imm) {
1800 *(cd->mcodeptr++) = 0x68;
1805 void emit_pop_reg(codegendata *cd, s8 reg) {
1806 emit_rex(0,0,0,(reg));
1807 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1811 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1812 emit_rex(1,(reg),0,(dreg));
1813 *(cd->mcodeptr++) = 0x87;
1814 emit_reg((reg),(dreg));
1818 void emit_nop(codegendata *cd) {
1819 *(cd->mcodeptr++) = 0x90;
1827 void emit_call_reg(codegendata *cd, s8 reg)
1829 emit_rex(0,0,0,(reg));
1830 *(cd->mcodeptr++) = 0xff;
1835 void emit_call_imm(codegendata *cd, s8 imm)
1837 *(cd->mcodeptr++) = 0xe8;
1842 void emit_call_mem(codegendata *cd, ptrint mem)
1844 *(cd->mcodeptr++) = 0xff;
1851 * floating point instructions (SSE2)
1853 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1854 *(cd->mcodeptr++) = 0xf2;
1855 emit_rex(0,(dreg),0,(reg));
1856 *(cd->mcodeptr++) = 0x0f;
1857 *(cd->mcodeptr++) = 0x58;
1858 emit_reg((dreg),(reg));
1862 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1863 *(cd->mcodeptr++) = 0xf3;
1864 emit_rex(0,(dreg),0,(reg));
1865 *(cd->mcodeptr++) = 0x0f;
1866 *(cd->mcodeptr++) = 0x58;
1867 emit_reg((dreg),(reg));
1871 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1872 *(cd->mcodeptr++) = 0xf3;
1873 emit_rex(1,(dreg),0,(reg));
1874 *(cd->mcodeptr++) = 0x0f;
1875 *(cd->mcodeptr++) = 0x2a;
1876 emit_reg((dreg),(reg));
1880 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1881 *(cd->mcodeptr++) = 0xf3;
1882 emit_rex(0,(dreg),0,(reg));
1883 *(cd->mcodeptr++) = 0x0f;
1884 *(cd->mcodeptr++) = 0x2a;
1885 emit_reg((dreg),(reg));
1889 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1890 *(cd->mcodeptr++) = 0xf2;
1891 emit_rex(1,(dreg),0,(reg));
1892 *(cd->mcodeptr++) = 0x0f;
1893 *(cd->mcodeptr++) = 0x2a;
1894 emit_reg((dreg),(reg));
1898 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1899 *(cd->mcodeptr++) = 0xf2;
1900 emit_rex(0,(dreg),0,(reg));
1901 *(cd->mcodeptr++) = 0x0f;
1902 *(cd->mcodeptr++) = 0x2a;
1903 emit_reg((dreg),(reg));
1907 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1908 *(cd->mcodeptr++) = 0xf3;
1909 emit_rex(0,(dreg),0,(reg));
1910 *(cd->mcodeptr++) = 0x0f;
1911 *(cd->mcodeptr++) = 0x5a;
1912 emit_reg((dreg),(reg));
1916 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1917 *(cd->mcodeptr++) = 0xf2;
1918 emit_rex(0,(dreg),0,(reg));
1919 *(cd->mcodeptr++) = 0x0f;
1920 *(cd->mcodeptr++) = 0x5a;
1921 emit_reg((dreg),(reg));
1925 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1926 *(cd->mcodeptr++) = 0xf3;
1927 emit_rex(1,(dreg),0,(reg));
1928 *(cd->mcodeptr++) = 0x0f;
1929 *(cd->mcodeptr++) = 0x2c;
1930 emit_reg((dreg),(reg));
1934 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1935 *(cd->mcodeptr++) = 0xf3;
1936 emit_rex(0,(dreg),0,(reg));
1937 *(cd->mcodeptr++) = 0x0f;
1938 *(cd->mcodeptr++) = 0x2c;
1939 emit_reg((dreg),(reg));
1943 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1944 *(cd->mcodeptr++) = 0xf2;
1945 emit_rex(1,(dreg),0,(reg));
1946 *(cd->mcodeptr++) = 0x0f;
1947 *(cd->mcodeptr++) = 0x2c;
1948 emit_reg((dreg),(reg));
1952 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1953 *(cd->mcodeptr++) = 0xf2;
1954 emit_rex(0,(dreg),0,(reg));
1955 *(cd->mcodeptr++) = 0x0f;
1956 *(cd->mcodeptr++) = 0x2c;
1957 emit_reg((dreg),(reg));
1961 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1962 *(cd->mcodeptr++) = 0xf3;
1963 emit_rex(0,(dreg),0,(reg));
1964 *(cd->mcodeptr++) = 0x0f;
1965 *(cd->mcodeptr++) = 0x5e;
1966 emit_reg((dreg),(reg));
1970 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1971 *(cd->mcodeptr++) = 0xf2;
1972 emit_rex(0,(dreg),0,(reg));
1973 *(cd->mcodeptr++) = 0x0f;
1974 *(cd->mcodeptr++) = 0x5e;
1975 emit_reg((dreg),(reg));
1979 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1980 *(cd->mcodeptr++) = 0x66;
1981 emit_rex(1,(freg),0,(reg));
1982 *(cd->mcodeptr++) = 0x0f;
1983 *(cd->mcodeptr++) = 0x6e;
1984 emit_reg((freg),(reg));
1988 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1989 *(cd->mcodeptr++) = 0x66;
1990 emit_rex(1,(freg),0,(reg));
1991 *(cd->mcodeptr++) = 0x0f;
1992 *(cd->mcodeptr++) = 0x7e;
1993 emit_reg((freg),(reg));
1997 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1998 *(cd->mcodeptr++) = 0x66;
1999 emit_rex(0,(reg),0,(basereg));
2000 *(cd->mcodeptr++) = 0x0f;
2001 *(cd->mcodeptr++) = 0x7e;
2002 emit_membase(cd, (basereg),(disp),(reg));
2006 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2007 *(cd->mcodeptr++) = 0x66;
2008 emit_rex(0,(reg),(indexreg),(basereg));
2009 *(cd->mcodeptr++) = 0x0f;
2010 *(cd->mcodeptr++) = 0x7e;
2011 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2015 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2016 *(cd->mcodeptr++) = 0x66;
2017 emit_rex(1,(dreg),0,(basereg));
2018 *(cd->mcodeptr++) = 0x0f;
2019 *(cd->mcodeptr++) = 0x6e;
2020 emit_membase(cd, (basereg),(disp),(dreg));
2024 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2025 *(cd->mcodeptr++) = 0x66;
2026 emit_rex(0,(dreg),0,(basereg));
2027 *(cd->mcodeptr++) = 0x0f;
2028 *(cd->mcodeptr++) = 0x6e;
2029 emit_membase(cd, (basereg),(disp),(dreg));
2033 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2034 *(cd->mcodeptr++) = 0x66;
2035 emit_rex(0,(dreg),(indexreg),(basereg));
2036 *(cd->mcodeptr++) = 0x0f;
2037 *(cd->mcodeptr++) = 0x6e;
2038 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2042 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2043 *(cd->mcodeptr++) = 0xf3;
2044 emit_rex(0,(dreg),0,(reg));
2045 *(cd->mcodeptr++) = 0x0f;
2046 *(cd->mcodeptr++) = 0x7e;
2047 emit_reg((dreg),(reg));
2051 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2052 *(cd->mcodeptr++) = 0x66;
2053 emit_rex(0,(reg),0,(basereg));
2054 *(cd->mcodeptr++) = 0x0f;
2055 *(cd->mcodeptr++) = 0xd6;
2056 emit_membase(cd, (basereg),(disp),(reg));
2060 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2061 *(cd->mcodeptr++) = 0xf3;
2062 emit_rex(0,(dreg),0,(basereg));
2063 *(cd->mcodeptr++) = 0x0f;
2064 *(cd->mcodeptr++) = 0x7e;
2065 emit_membase(cd, (basereg),(disp),(dreg));
2069 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2070 *(cd->mcodeptr++) = 0xf3;
2071 emit_rex(0,(reg),0,(dreg));
2072 *(cd->mcodeptr++) = 0x0f;
2073 *(cd->mcodeptr++) = 0x10;
2074 emit_reg((reg),(dreg));
2078 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2079 *(cd->mcodeptr++) = 0xf2;
2080 emit_rex(0,(reg),0,(dreg));
2081 *(cd->mcodeptr++) = 0x0f;
2082 *(cd->mcodeptr++) = 0x10;
2083 emit_reg((reg),(dreg));
2087 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2088 *(cd->mcodeptr++) = 0xf3;
2089 emit_rex(0,(reg),0,(basereg));
2090 *(cd->mcodeptr++) = 0x0f;
2091 *(cd->mcodeptr++) = 0x11;
2092 emit_membase(cd, (basereg),(disp),(reg));
2096 /* Always emit a REX byte, because the instruction size can be smaller when */
2097 /* all register indexes are smaller than 7. */
2098 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2099 *(cd->mcodeptr++) = 0xf3;
2100 emit_byte_rex((reg),0,(basereg));
2101 *(cd->mcodeptr++) = 0x0f;
2102 *(cd->mcodeptr++) = 0x11;
2103 emit_membase32(cd, (basereg),(disp),(reg));
2107 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2108 *(cd->mcodeptr++) = 0xf2;
2109 emit_rex(0,(reg),0,(basereg));
2110 *(cd->mcodeptr++) = 0x0f;
2111 *(cd->mcodeptr++) = 0x11;
2112 emit_membase(cd, (basereg),(disp),(reg));
2116 /* Always emit a REX byte, because the instruction size can be smaller when */
2117 /* all register indexes are smaller than 7. */
2118 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2119 *(cd->mcodeptr++) = 0xf2;
2120 emit_byte_rex((reg),0,(basereg));
2121 *(cd->mcodeptr++) = 0x0f;
2122 *(cd->mcodeptr++) = 0x11;
2123 emit_membase32(cd, (basereg),(disp),(reg));
2127 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2128 *(cd->mcodeptr++) = 0xf3;
2129 emit_rex(0,(dreg),0,(basereg));
2130 *(cd->mcodeptr++) = 0x0f;
2131 *(cd->mcodeptr++) = 0x10;
2132 emit_membase(cd, (basereg),(disp),(dreg));
2136 /* Always emit a REX byte, because the instruction size can be smaller when */
2137 /* all register indexes are smaller than 7. */
2138 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2139 *(cd->mcodeptr++) = 0xf3;
2140 emit_byte_rex((dreg),0,(basereg));
2141 *(cd->mcodeptr++) = 0x0f;
2142 *(cd->mcodeptr++) = 0x10;
2143 emit_membase32(cd, (basereg),(disp),(dreg));
2147 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2149 emit_rex(0,(dreg),0,(basereg));
2150 *(cd->mcodeptr++) = 0x0f;
2151 *(cd->mcodeptr++) = 0x12;
2152 emit_membase(cd, (basereg),(disp),(dreg));
2156 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2158 emit_rex(0,(reg),0,(basereg));
2159 *(cd->mcodeptr++) = 0x0f;
2160 *(cd->mcodeptr++) = 0x13;
2161 emit_membase(cd, (basereg),(disp),(reg));
2165 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2166 *(cd->mcodeptr++) = 0xf2;
2167 emit_rex(0,(dreg),0,(basereg));
2168 *(cd->mcodeptr++) = 0x0f;
2169 *(cd->mcodeptr++) = 0x10;
2170 emit_membase(cd, (basereg),(disp),(dreg));
2174 /* Always emit a REX byte, because the instruction size can be smaller when */
2175 /* all register indexes are smaller than 7. */
2176 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2177 *(cd->mcodeptr++) = 0xf2;
2178 emit_byte_rex((dreg),0,(basereg));
2179 *(cd->mcodeptr++) = 0x0f;
2180 *(cd->mcodeptr++) = 0x10;
2181 emit_membase32(cd, (basereg),(disp),(dreg));
2185 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2187 *(cd->mcodeptr++) = 0x66;
2188 emit_rex(0,(dreg),0,(basereg));
2189 *(cd->mcodeptr++) = 0x0f;
2190 *(cd->mcodeptr++) = 0x12;
2191 emit_membase(cd, (basereg),(disp),(dreg));
2195 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2197 *(cd->mcodeptr++) = 0x66;
2198 emit_rex(0,(reg),0,(basereg));
2199 *(cd->mcodeptr++) = 0x0f;
2200 *(cd->mcodeptr++) = 0x13;
2201 emit_membase(cd, (basereg),(disp),(reg));
2205 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2206 *(cd->mcodeptr++) = 0xf3;
2207 emit_rex(0,(reg),(indexreg),(basereg));
2208 *(cd->mcodeptr++) = 0x0f;
2209 *(cd->mcodeptr++) = 0x11;
2210 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2214 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2215 *(cd->mcodeptr++) = 0xf2;
2216 emit_rex(0,(reg),(indexreg),(basereg));
2217 *(cd->mcodeptr++) = 0x0f;
2218 *(cd->mcodeptr++) = 0x11;
2219 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2223 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2224 *(cd->mcodeptr++) = 0xf3;
2225 emit_rex(0,(dreg),(indexreg),(basereg));
2226 *(cd->mcodeptr++) = 0x0f;
2227 *(cd->mcodeptr++) = 0x10;
2228 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2232 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2233 *(cd->mcodeptr++) = 0xf2;
2234 emit_rex(0,(dreg),(indexreg),(basereg));
2235 *(cd->mcodeptr++) = 0x0f;
2236 *(cd->mcodeptr++) = 0x10;
2237 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2241 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2242 *(cd->mcodeptr++) = 0xf3;
2243 emit_rex(0,(dreg),0,(reg));
2244 *(cd->mcodeptr++) = 0x0f;
2245 *(cd->mcodeptr++) = 0x59;
2246 emit_reg((dreg),(reg));
2250 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2251 *(cd->mcodeptr++) = 0xf2;
2252 emit_rex(0,(dreg),0,(reg));
2253 *(cd->mcodeptr++) = 0x0f;
2254 *(cd->mcodeptr++) = 0x59;
2255 emit_reg((dreg),(reg));
2259 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2260 *(cd->mcodeptr++) = 0xf3;
2261 emit_rex(0,(dreg),0,(reg));
2262 *(cd->mcodeptr++) = 0x0f;
2263 *(cd->mcodeptr++) = 0x5c;
2264 emit_reg((dreg),(reg));
2268 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2269 *(cd->mcodeptr++) = 0xf2;
2270 emit_rex(0,(dreg),0,(reg));
2271 *(cd->mcodeptr++) = 0x0f;
2272 *(cd->mcodeptr++) = 0x5c;
2273 emit_reg((dreg),(reg));
2277 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2278 emit_rex(0,(dreg),0,(reg));
2279 *(cd->mcodeptr++) = 0x0f;
2280 *(cd->mcodeptr++) = 0x2e;
2281 emit_reg((dreg),(reg));
2285 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2286 *(cd->mcodeptr++) = 0x66;
2287 emit_rex(0,(dreg),0,(reg));
2288 *(cd->mcodeptr++) = 0x0f;
2289 *(cd->mcodeptr++) = 0x2e;
2290 emit_reg((dreg),(reg));
2294 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2295 emit_rex(0,(dreg),0,(reg));
2296 *(cd->mcodeptr++) = 0x0f;
2297 *(cd->mcodeptr++) = 0x57;
2298 emit_reg((dreg),(reg));
2302 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2303 emit_rex(0,(dreg),0,(basereg));
2304 *(cd->mcodeptr++) = 0x0f;
2305 *(cd->mcodeptr++) = 0x57;
2306 emit_membase(cd, (basereg),(disp),(dreg));
2310 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2311 *(cd->mcodeptr++) = 0x66;
2312 emit_rex(0,(dreg),0,(reg));
2313 *(cd->mcodeptr++) = 0x0f;
2314 *(cd->mcodeptr++) = 0x57;
2315 emit_reg((dreg),(reg));
2319 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2320 *(cd->mcodeptr++) = 0x66;
2321 emit_rex(0,(dreg),0,(basereg));
2322 *(cd->mcodeptr++) = 0x0f;
2323 *(cd->mcodeptr++) = 0x57;
2324 emit_membase(cd, (basereg),(disp),(dreg));
2328 /* system instructions ********************************************************/
2330 void emit_rdtsc(codegendata *cd)
2332 *(cd->mcodeptr++) = 0x0f;
2333 *(cd->mcodeptr++) = 0x31;
2338 * These are local overrides for various environment variables in Emacs.
2339 * Please do not remove this and leave it at the end of the file, where
2340 * Emacs will automagically detect them.
2341 * ---------------------------------------------------------------------
2344 * indent-tabs-mode: t