1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2011
4 CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 This file is part of CACAO.
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at
11 your option) any later version.
13 This program is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
34 #include "vm/jit/x86_64/codegen.h"
35 #include "vm/jit/x86_64/emit.h"
37 #include "mm/memory.hpp"
39 #include "threads/lock.hpp"
41 #include "vm/options.h"
43 #include "vm/jit/abi.h"
44 #include "vm/jit/abi-asm.h"
45 #include "vm/jit/asmpart.h"
46 #include "vm/jit/codegen-common.hpp"
47 #include "vm/jit/emit-common.hpp"
48 #include "vm/jit/jit.hpp"
49 #include "vm/jit/patcher-common.hpp"
50 #include "vm/jit/replace.hpp"
51 #include "vm/jit/trace.hpp"
52 #include "vm/jit/trap.hpp"
55 /* emit_load *******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
78 M_ILD(tempreg, REG_SP, disp);
82 M_LLD(tempreg, REG_SP, disp);
85 M_FLD(tempreg, REG_SP, disp);
88 M_DLD(tempreg, REG_SP, disp);
91 vm_abort("emit_load: unknown type %d", src->type);
103 /* emit_store ******************************************************************
105 This function generates the code to store the result of an
106 operation back into a spilled pseudo-variable. If the
107 pseudo-variable has not been spilled in the first place, this
108 function will generate nothing.
110 *******************************************************************************/
112 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
117 /* get required compiler data */
121 if (IS_INMEMORY(dst->flags)) {
124 disp = dst->vv.regoff;
130 M_LST(d, REG_SP, disp);
133 M_FST(d, REG_SP, disp);
136 M_DST(d, REG_SP, disp);
139 vm_abort("emit_store: unknown type %d", dst->type);
145 /* emit_copy *******************************************************************
147 Generates a register/memory to register/memory copy.
149 *******************************************************************************/
151 void emit_copy(jitdata *jd, instruction *iptr)
158 /* get required compiler data */
162 /* get source and destination variables */
164 src = VAROP(iptr->s1);
165 dst = VAROP(iptr->dst);
167 if ((src->vv.regoff != dst->vv.regoff) ||
168 ((src->flags ^ dst->flags) & INMEMORY)) {
170 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
171 /* emit nothing, as the value won't be used anyway */
175 /* If one of the variables resides in memory, we can eliminate
176 the register move from/to the temporary register with the
177 order of getting the destination register and the load. */
179 if (IS_INMEMORY(src->flags)) {
180 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
181 s1 = emit_load(jd, iptr, src, d);
184 s1 = emit_load(jd, iptr, src, REG_IFTMP);
185 d = codegen_reg_of_var(iptr->opc, dst, s1);
200 vm_abort("emit_copy: unknown type %d", src->type);
204 emit_store(jd, iptr, dst, d);
209 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
212 switch (iptr->flags.fields.condition) {
237 * Emits code updating the condition register by comparing one integer
238 * register to an immediate integer value.
240 void emit_icmp_imm(codegendata* cd, int reg, int32_t value)
242 M_ICMP_IMM(value, reg);
246 /* emit_branch *****************************************************************
248 Emits the code for conditional and unconditional branchs.
250 *******************************************************************************/
252 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
256 /* NOTE: A displacement overflow cannot happen. */
258 /* check which branch to generate */
260 if (condition == BRANCH_UNCONDITIONAL) {
262 /* calculate the different displacements */
264 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
266 M_JMP_IMM(branchdisp);
269 /* calculate the different displacements */
271 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
305 vm_abort("emit_branch: unknown condition %d", condition);
311 /* emit_arithmetic_check *******************************************************
313 Emit an ArithmeticException check.
315 *******************************************************************************/
317 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
319 if (INSTRUCTION_MUST_CHECK(iptr)) {
322 M_ALD_MEM(reg, TRAP_ArithmeticException);
327 /* emit_arrayindexoutofbounds_check ********************************************
329 Emit a ArrayIndexOutOfBoundsException check.
331 *******************************************************************************/
333 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
335 if (INSTRUCTION_MUST_CHECK(iptr)) {
336 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
337 M_ICMP(REG_ITMP3, s2);
339 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
344 /* emit_arraystore_check *******************************************************
346 Emit an ArrayStoreException check.
348 *******************************************************************************/
350 void emit_arraystore_check(codegendata *cd, instruction *iptr)
352 if (INSTRUCTION_MUST_CHECK(iptr)) {
355 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
360 /* emit_classcast_check ********************************************************
362 Emit a ClassCastException check.
364 *******************************************************************************/
366 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
368 if (INSTRUCTION_MUST_CHECK(iptr)) {
386 vm_abort("emit_classcast_check: unknown condition %d", condition);
388 M_ALD_MEM(s1, TRAP_ClassCastException);
393 /* emit_nullpointer_check ******************************************************
395 Emit a NullPointerException check.
397 *******************************************************************************/
399 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
401 if (INSTRUCTION_MUST_CHECK(iptr)) {
404 M_ALD_MEM(reg, TRAP_NullPointerException);
409 /* emit_exception_check ********************************************************
411 Emit an Exception check.
413 *******************************************************************************/
415 void emit_exception_check(codegendata *cd, instruction *iptr)
417 if (INSTRUCTION_MUST_CHECK(iptr)) {
420 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
425 /* emit_trap_compiler **********************************************************
427 Emit a trap instruction which calls the JIT compiler.
429 *******************************************************************************/
431 void emit_trap_compiler(codegendata *cd)
433 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
437 /* emit_patcher_alignment ******************************************************
439 Emit NOP to ensure placement at an even address.
441 *******************************************************************************/
443 void emit_patcher_alignment(codegendata *cd)
445 if ((uintptr_t) cd->mcodeptr & 1)
450 /* emit_trap *******************************************************************
452 Emit a trap instruction and return the original machine code.
454 *******************************************************************************/
456 uint32_t emit_trap(codegendata *cd)
460 /* Get machine code which is patched back in later. The trap is 2
463 mcode = *((uint16_t *) cd->mcodeptr);
465 /* XXX This needs to be change to INT3 when the debugging problems
466 with gdb are resolved. */
475 * Generates fast-path code for the below builtin.
476 * Function: LOCK_monitor_enter
477 * Signature: (Ljava/lang/Object;)V
478 * Slow-path: bool lock_monitor_enter(java_handle_t*);
480 void emit_fastpath_monitor_enter(jitdata* jd, instruction* iptr, int d)
482 // Get required compiler data.
483 codegendata* cd = jd->cd;
485 // XXX Currently the fast-path always fails. Implement me!
491 * Generates fast-path code for the below builtin.
492 * Function: LOCK_monitor_exit
493 * Signature: (Ljava/lang/Object;)V
494 * Slow-path: bool lock_monitor_exit(java_handle_t*);
496 void emit_fastpath_monitor_exit(jitdata* jd, instruction* iptr, int d)
498 // Get required compiler data.
499 codegendata* cd = jd->cd;
501 // XXX Currently the fast-path always fails. Implement me!
507 * Generates synchronization code to enter a monitor.
509 #if defined(ENABLE_THREADS)
510 void emit_monitor_enter(jitdata* jd, int32_t syncslot_offset)
514 // Get required compiler data.
515 methodinfo* m = jd->m;
516 codegendata* cd = jd->cd;
518 # if !defined(NDEBUG)
519 if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) {
520 M_LSUB_IMM((INT_ARG_CNT + FLT_ARG_CNT) * 8, REG_SP);
522 for (p = 0; p < INT_ARG_CNT; p++)
523 M_LST(abi_registers_integer_argument[p], REG_SP, p * 8);
525 for (p = 0; p < FLT_ARG_CNT; p++)
526 M_DST(abi_registers_float_argument[p], REG_SP, (INT_ARG_CNT + p) * 8);
528 syncslot_offset += (INT_ARG_CNT + FLT_ARG_CNT) * 8;
532 /* decide which monitor enter function to call */
534 if (m->flags & ACC_STATIC) {
535 M_MOV_IMM(&m->clazz->object.header, REG_A0);
540 M_ALD_MEM(REG_A0, TRAP_NullPointerException);
543 M_AST(REG_A0, REG_SP, syncslot_offset);
544 M_MOV_IMM(LOCK_monitor_enter, REG_ITMP1);
547 # if !defined(NDEBUG)
548 if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) {
550 for (p = 0; p < INT_ARG_CNT; p++)
551 M_LLD(abi_registers_integer_argument[p], REG_SP, p * 8);
553 for (p = 0; p < FLT_ARG_CNT; p++)
554 M_DLD(abi_registers_float_argument[p], REG_SP, (INT_ARG_CNT + p) * 8);
556 M_LADD_IMM((INT_ARG_CNT + FLT_ARG_CNT) * 8, REG_SP);
564 * Generates synchronization code to leave a monitor.
566 #if defined(ENABLE_THREADS)
567 void emit_monitor_exit(jitdata* jd, int32_t syncslot_offset)
569 // Get required compiler data.
570 methodinfo* m = jd->m;
571 codegendata* cd = jd->cd;
573 M_ALD(REG_A0, REG_SP, syncslot_offset);
575 /* we need to save the proper return value */
577 methoddesc* md = m->parseddesc;
579 switch (md->returntype.type) {
583 M_LST(REG_RESULT, REG_SP, syncslot_offset);
587 M_DST(REG_FRESULT, REG_SP, syncslot_offset);
591 M_MOV_IMM(LOCK_monitor_exit, REG_ITMP1);
594 /* and now restore the proper return value */
596 switch (md->returntype.type) {
600 M_LLD(REG_RESULT, REG_SP, syncslot_offset);
604 M_DLD(REG_FRESULT, REG_SP, syncslot_offset);
612 * Emit profiling code for method frequency counting.
614 #if defined(ENABLE_PROFILING)
615 void emit_profile_method(codegendata* cd, codeinfo* code)
617 M_MOV_IMM(code, REG_ITMP3);
618 M_IINC_MEMBASE(REG_ITMP3, OFFSET(codeinfo, frequency));
624 * Emit profiling code for basicblock frequency counting.
626 #if defined(ENABLE_PROFILING)
627 void emit_profile_basicblock(codegendata* cd, codeinfo* code, basicblock* bptr)
629 M_MOV_IMM(code->bbfrequency, REG_ITMP3);
630 M_IINC_MEMBASE(REG_ITMP3, bptr->nr * 4);
636 * Emit profiling code to start CPU cycle counting.
638 #if defined(ENABLE_PROFILING)
639 void emit_profile_cycle_start(codegendata* cd, codeinfo* code)
644 M_MOV_IMM(code, REG_ITMP3);
646 M_ISUB_MEMBASE(RAX, REG_ITMP3, OFFSET(codeinfo, cycles));
647 M_ISBB_MEMBASE(RDX, REG_ITMP3, OFFSET(codeinfo, cycles) + 4);
656 * Emit profiling code to stop CPU cycle counting.
658 #if defined(ENABLE_PROFILING)
659 void emit_profile_cycle_stop(codegendata* cd, codeinfo* code)
664 M_MOV_IMM(code, REG_ITMP3);
666 M_IADD_MEMBASE(RAX, REG_ITMP3, OFFSET(codeinfo, cycles));
667 M_IADC_MEMBASE(RDX, REG_ITMP3, OFFSET(codeinfo, cycles) + 4);
675 /* emit_verbosecall_enter ******************************************************
677 Generates the code for the call trace.
679 *******************************************************************************/
682 void emit_verbosecall_enter(jitdata *jd)
692 /* get required compiler data */
701 /* mark trace code */
705 /* keep 16-byte stack alignment */
707 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
708 ALIGN_2(stackframesize);
710 M_LSUB_IMM(stackframesize * 8, REG_SP);
712 /* save argument registers */
714 for (i = 0; i < md->paramcount; i++) {
715 if (!md->params[i].inmemory) {
716 s = md->params[i].regoff;
718 switch (md->paramtypes[i].type) {
722 M_LST(s, REG_SP, i * 8);
726 M_DST(s, REG_SP, i * 8);
732 /* save all argument and temporary registers for leaf methods */
734 if (code_is_leafmethod(code)) {
735 for (i = 0; i < INT_ARG_CNT; i++)
736 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
738 for (i = 0; i < FLT_ARG_CNT; i++)
739 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
741 for (i = 0; i < INT_TMP_CNT; i++)
742 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
744 for (i = 0; i < FLT_TMP_CNT; i++)
745 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
748 M_MOV_IMM(m, REG_A0);
749 M_MOV(REG_SP, REG_A1);
750 M_MOV(REG_SP, REG_A2);
751 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
752 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
755 /* restore argument registers */
757 for (i = 0; i < md->paramcount; i++) {
758 if (!md->params[i].inmemory) {
759 s = md->params[i].regoff;
761 switch (md->paramtypes[i].type) {
765 M_LLD(s, REG_SP, i * 8);
769 M_DLD(s, REG_SP, i * 8);
776 /* restore all argument and temporary registers for leaf methods */
778 if (code_is_leafmethod(code)) {
779 for (i = 0; i < INT_ARG_CNT; i++)
780 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
782 for (i = 0; i < FLT_ARG_CNT; i++)
783 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
785 for (i = 0; i < INT_TMP_CNT; i++)
786 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
788 for (i = 0; i < FLT_TMP_CNT; i++)
789 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
792 M_LADD_IMM(stackframesize * 8, REG_SP);
794 /* mark trace code */
798 #endif /* !defined(NDEBUG) */
801 /* emit_verbosecall_exit *******************************************************
803 Generates the code for the call trace.
805 *******************************************************************************/
808 void emit_verbosecall_exit(jitdata *jd)
815 /* get required compiler data */
823 /* mark trace code */
827 /* keep 16-byte stack alignment */
829 M_ASUB_IMM(2 * 8, REG_SP);
831 /* save return value */
833 switch (md->returntype.type) {
837 M_LST(REG_RESULT, REG_SP, 0 * 8);
841 M_DST(REG_FRESULT, REG_SP, 0 * 8);
845 M_MOV_IMM(m, REG_A0);
846 M_MOV(REG_SP, REG_A1);
848 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
851 /* restore return value */
853 switch (md->returntype.type) {
857 M_LLD(REG_RESULT, REG_SP, 0 * 8);
861 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
865 M_AADD_IMM(2 * 8, REG_SP);
867 /* mark trace code */
871 #endif /* !defined(NDEBUG) */
874 /* code generation functions **************************************************/
876 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
878 if ((basereg == REG_SP) || (basereg == R12)) {
880 emit_address_byte(0, dreg, REG_SP);
881 emit_address_byte(0, REG_SP, REG_SP);
883 } else if (IS_IMM8(disp)) {
884 emit_address_byte(1, dreg, REG_SP);
885 emit_address_byte(0, REG_SP, REG_SP);
889 emit_address_byte(2, dreg, REG_SP);
890 emit_address_byte(0, REG_SP, REG_SP);
894 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
895 emit_address_byte(0,(dreg),(basereg));
897 } else if ((basereg) == RIP) {
898 emit_address_byte(0, dreg, RBP);
903 emit_address_byte(1, dreg, basereg);
907 emit_address_byte(2, dreg, basereg);
914 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
916 if ((basereg == REG_SP) || (basereg == R12)) {
917 emit_address_byte(2, dreg, REG_SP);
918 emit_address_byte(0, REG_SP, REG_SP);
922 emit_address_byte(2, dreg, basereg);
928 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
931 emit_address_byte(0, reg, 4);
932 emit_address_byte(scale, indexreg, 5);
935 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
936 emit_address_byte(0, reg, 4);
937 emit_address_byte(scale, indexreg, basereg);
939 else if (IS_IMM8(disp)) {
940 emit_address_byte(1, reg, 4);
941 emit_address_byte(scale, indexreg, basereg);
945 emit_address_byte(2, reg, 4);
946 emit_address_byte(scale, indexreg, basereg);
952 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
955 varinfo *v_s1,*v_s2,*v_dst;
958 /* get required compiler data */
962 v_s1 = VAROP(iptr->s1);
963 v_s2 = VAROP(iptr->sx.s23.s2);
964 v_dst = VAROP(iptr->dst);
966 s1 = v_s1->vv.regoff;
967 s2 = v_s2->vv.regoff;
968 d = v_dst->vv.regoff;
970 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
972 if (IS_INMEMORY(v_dst->flags)) {
973 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
975 M_ILD(RCX, REG_SP, s2);
976 emit_shiftl_membase(cd, shift_op, REG_SP, d);
979 M_ILD(RCX, REG_SP, s2);
980 M_ILD(REG_ITMP2, REG_SP, s1);
981 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
982 M_IST(REG_ITMP2, REG_SP, d);
985 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
986 /* s1 may be equal to RCX */
989 M_ILD(REG_ITMP1, REG_SP, s2);
990 M_IST(s1, REG_SP, d);
991 M_INTMOVE(REG_ITMP1, RCX);
994 M_IST(s1, REG_SP, d);
995 M_ILD(RCX, REG_SP, s2);
999 M_ILD(RCX, REG_SP, s2);
1000 M_IST(s1, REG_SP, d);
1003 emit_shiftl_membase(cd, shift_op, REG_SP, d);
1005 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1008 emit_shiftl_membase(cd, shift_op, REG_SP, d);
1012 M_ILD(REG_ITMP2, REG_SP, s1);
1013 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
1014 M_IST(REG_ITMP2, REG_SP, d);
1018 /* s1 may be equal to RCX */
1019 M_IST(s1, REG_SP, d);
1021 emit_shiftl_membase(cd, shift_op, REG_SP, d);
1024 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1032 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1033 M_ILD(RCX, REG_SP, s2);
1034 M_ILD(d, REG_SP, s1);
1035 emit_shiftl_reg(cd, shift_op, d);
1037 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1038 /* s1 may be equal to RCX */
1040 M_ILD(RCX, REG_SP, s2);
1041 emit_shiftl_reg(cd, shift_op, d);
1043 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1045 M_ILD(d, REG_SP, s1);
1046 emit_shiftl_reg(cd, shift_op, d);
1049 /* s1 may be equal to RCX */
1052 /* d cannot be used to backup s1 since this would
1054 M_INTMOVE(s1, REG_ITMP3);
1056 M_INTMOVE(REG_ITMP3, d);
1064 /* d may be equal to s2 */
1068 emit_shiftl_reg(cd, shift_op, d);
1072 M_INTMOVE(REG_ITMP3, RCX);
1074 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1079 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
1081 s4 s1, s2, d, d_old;
1082 varinfo *v_s1,*v_s2,*v_dst;
1085 /* get required compiler data */
1089 v_s1 = VAROP(iptr->s1);
1090 v_s2 = VAROP(iptr->sx.s23.s2);
1091 v_dst = VAROP(iptr->dst);
1093 s1 = v_s1->vv.regoff;
1094 s2 = v_s2->vv.regoff;
1095 d = v_dst->vv.regoff;
1097 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
1099 if (IS_INMEMORY(v_dst->flags)) {
1100 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1102 M_ILD(RCX, REG_SP, s2);
1103 emit_shift_membase(cd, shift_op, REG_SP, d);
1106 M_ILD(RCX, REG_SP, s2);
1107 M_LLD(REG_ITMP2, REG_SP, s1);
1108 emit_shift_reg(cd, shift_op, REG_ITMP2);
1109 M_LST(REG_ITMP2, REG_SP, d);
1112 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1113 /* s1 may be equal to RCX */
1116 M_ILD(REG_ITMP1, REG_SP, s2);
1117 M_LST(s1, REG_SP, d);
1118 M_INTMOVE(REG_ITMP1, RCX);
1121 M_LST(s1, REG_SP, d);
1122 M_ILD(RCX, REG_SP, s2);
1126 M_ILD(RCX, REG_SP, s2);
1127 M_LST(s1, REG_SP, d);
1130 emit_shift_membase(cd, shift_op, REG_SP, d);
1132 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1135 emit_shift_membase(cd, shift_op, REG_SP, d);
1139 M_LLD(REG_ITMP2, REG_SP, s1);
1140 emit_shift_reg(cd, shift_op, REG_ITMP2);
1141 M_LST(REG_ITMP2, REG_SP, d);
1145 /* s1 may be equal to RCX */
1146 M_LST(s1, REG_SP, d);
1148 emit_shift_membase(cd, shift_op, REG_SP, d);
1151 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1159 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1160 M_ILD(RCX, REG_SP, s2);
1161 M_LLD(d, REG_SP, s1);
1162 emit_shift_reg(cd, shift_op, d);
1164 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1165 /* s1 may be equal to RCX */
1167 M_ILD(RCX, REG_SP, s2);
1168 emit_shift_reg(cd, shift_op, d);
1170 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1172 M_LLD(d, REG_SP, s1);
1173 emit_shift_reg(cd, shift_op, d);
1176 /* s1 may be equal to RCX */
1179 /* d cannot be used to backup s1 since this would
1181 M_INTMOVE(s1, REG_ITMP3);
1183 M_INTMOVE(REG_ITMP3, d);
1191 /* d may be equal to s2 */
1195 emit_shift_reg(cd, shift_op, d);
1199 M_INTMOVE(REG_ITMP3, RCX);
1201 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1206 /* low-level code emitter functions *******************************************/
1208 void emit_nop(codegendata *cd, int length)
1210 assert(length >= 1 && length <= 9);
1213 *(cd->mcodeptr++) = 0x90;
1216 *(cd->mcodeptr++) = 0x66;
1217 *(cd->mcodeptr++) = 0x90;
1220 *(cd->mcodeptr++) = 0x0f;
1221 *(cd->mcodeptr++) = 0x1f;
1222 *(cd->mcodeptr++) = 0x00;
1225 *(cd->mcodeptr++) = 0x0f;
1226 *(cd->mcodeptr++) = 0x1f;
1227 *(cd->mcodeptr++) = 0x40;
1228 *(cd->mcodeptr++) = 0x00;
1231 *(cd->mcodeptr++) = 0x0f;
1232 *(cd->mcodeptr++) = 0x1f;
1233 *(cd->mcodeptr++) = 0x44;
1234 *(cd->mcodeptr++) = 0x00;
1235 *(cd->mcodeptr++) = 0x00;
1238 *(cd->mcodeptr++) = 0x66;
1239 *(cd->mcodeptr++) = 0x0f;
1240 *(cd->mcodeptr++) = 0x1f;
1241 *(cd->mcodeptr++) = 0x44;
1242 *(cd->mcodeptr++) = 0x00;
1243 *(cd->mcodeptr++) = 0x00;
1246 *(cd->mcodeptr++) = 0x0f;
1247 *(cd->mcodeptr++) = 0x1f;
1248 *(cd->mcodeptr++) = 0x80;
1249 *(cd->mcodeptr++) = 0x00;
1250 *(cd->mcodeptr++) = 0x00;
1251 *(cd->mcodeptr++) = 0x00;
1252 *(cd->mcodeptr++) = 0x00;
1255 *(cd->mcodeptr++) = 0x0f;
1256 *(cd->mcodeptr++) = 0x1f;
1257 *(cd->mcodeptr++) = 0x84;
1258 *(cd->mcodeptr++) = 0x00;
1259 *(cd->mcodeptr++) = 0x00;
1260 *(cd->mcodeptr++) = 0x00;
1261 *(cd->mcodeptr++) = 0x00;
1262 *(cd->mcodeptr++) = 0x00;
1265 *(cd->mcodeptr++) = 0x66;
1266 *(cd->mcodeptr++) = 0x0f;
1267 *(cd->mcodeptr++) = 0x1f;
1268 *(cd->mcodeptr++) = 0x84;
1269 *(cd->mcodeptr++) = 0x00;
1270 *(cd->mcodeptr++) = 0x00;
1271 *(cd->mcodeptr++) = 0x00;
1272 *(cd->mcodeptr++) = 0x00;
1273 *(cd->mcodeptr++) = 0x00;
1278 void emit_arbitrary_nop(codegendata *cd, int disp)
1281 int x = disp < 9 ? disp : 9;
1287 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1289 emit_rex(1,(reg),0,(dreg));
1290 *(cd->mcodeptr++) = 0x89;
1291 emit_reg((reg),(dreg));
1295 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1297 emit_rex(1,0,0,(reg));
1298 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1303 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1305 emit_rex(0,(reg),0,(dreg));
1306 *(cd->mcodeptr++) = 0x89;
1307 emit_reg((reg),(dreg));
1311 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1312 emit_rex(0,0,0,(reg));
1313 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1318 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1319 emit_rex(1,(reg),0,(basereg));
1320 *(cd->mcodeptr++) = 0x8b;
1321 emit_membase(cd, (basereg),(disp),(reg));
1326 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1327 * constant membase immediate length of 32bit
1329 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1330 emit_rex(1,(reg),0,(basereg));
1331 *(cd->mcodeptr++) = 0x8b;
1332 emit_membase32(cd, (basereg),(disp),(reg));
1336 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1338 emit_rex(0,(reg),0,(basereg));
1339 *(cd->mcodeptr++) = 0x8b;
1340 emit_membase(cd, (basereg),(disp),(reg));
1344 /* ATTENTION: Always emit a REX byte, because the instruction size can
1345 be smaller when all register indexes are smaller than 7. */
1346 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1348 emit_byte_rex((reg),0,(basereg));
1349 *(cd->mcodeptr++) = 0x8b;
1350 emit_membase32(cd, (basereg),(disp),(reg));
1354 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1355 emit_rex(1,(reg),0,(basereg));
1356 *(cd->mcodeptr++) = 0x89;
1357 emit_membase(cd, (basereg),(disp),(reg));
1361 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1362 emit_rex(1,(reg),0,(basereg));
1363 *(cd->mcodeptr++) = 0x89;
1364 emit_membase32(cd, (basereg),(disp),(reg));
1368 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1369 emit_rex(0,(reg),0,(basereg));
1370 *(cd->mcodeptr++) = 0x89;
1371 emit_membase(cd, (basereg),(disp),(reg));
1375 /* Always emit a REX byte, because the instruction size can be smaller when */
1376 /* all register indexes are smaller than 7. */
1377 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1378 emit_byte_rex((reg),0,(basereg));
1379 *(cd->mcodeptr++) = 0x89;
1380 emit_membase32(cd, (basereg),(disp),(reg));
1384 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1385 emit_rex(1,(reg),(indexreg),(basereg));
1386 *(cd->mcodeptr++) = 0x8b;
1387 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1391 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1392 emit_rex(0,(reg),(indexreg),(basereg));
1393 *(cd->mcodeptr++) = 0x8b;
1394 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1398 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1399 emit_rex(1,(reg),(indexreg),(basereg));
1400 *(cd->mcodeptr++) = 0x89;
1401 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1405 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1406 emit_rex(0,(reg),(indexreg),(basereg));
1407 *(cd->mcodeptr++) = 0x89;
1408 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1412 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1413 *(cd->mcodeptr++) = 0x66;
1414 emit_rex(0,(reg),(indexreg),(basereg));
1415 *(cd->mcodeptr++) = 0x89;
1416 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1420 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1421 emit_byte_rex((reg),(indexreg),(basereg));
1422 *(cd->mcodeptr++) = 0x88;
1423 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1427 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1428 emit_rex(1,0,0,(basereg));
1429 *(cd->mcodeptr++) = 0xc7;
1430 emit_membase(cd, (basereg),(disp),0);
1435 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1436 emit_rex(1,0,0,(basereg));
1437 *(cd->mcodeptr++) = 0xc7;
1438 emit_membase32(cd, (basereg),(disp),0);
1443 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1444 emit_rex(0,0,0,(basereg));
1445 *(cd->mcodeptr++) = 0xc7;
1446 emit_membase(cd, (basereg),(disp),0);
1451 /* Always emit a REX byte, because the instruction size can be smaller when */
1452 /* all register indexes are smaller than 7. */
1453 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1454 emit_byte_rex(0,0,(basereg));
1455 *(cd->mcodeptr++) = 0xc7;
1456 emit_membase32(cd, (basereg),(disp),0);
1461 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1463 emit_rex(1,(dreg),0,(reg));
1464 *(cd->mcodeptr++) = 0x0f;
1465 *(cd->mcodeptr++) = 0xbe;
1466 /* XXX: why do reg and dreg have to be exchanged */
1467 emit_reg((dreg),(reg));
1471 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1473 emit_rex(1,(dreg),0,(reg));
1474 *(cd->mcodeptr++) = 0x0f;
1475 *(cd->mcodeptr++) = 0xbf;
1476 /* XXX: why do reg and dreg have to be exchanged */
1477 emit_reg((dreg),(reg));
1481 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1483 emit_rex(1,(dreg),0,(reg));
1484 *(cd->mcodeptr++) = 0x63;
1485 /* XXX: why do reg and dreg have to be exchanged */
1486 emit_reg((dreg),(reg));
1490 void emit_movzbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1492 emit_rex(1,(dreg),0,(reg));
1493 *(cd->mcodeptr++) = 0x0f;
1494 *(cd->mcodeptr++) = 0xb6;
1495 /* XXX: why do reg and dreg have to be exchanged */
1496 emit_reg((dreg),(reg));
1500 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1502 emit_rex(1,(dreg),0,(reg));
1503 *(cd->mcodeptr++) = 0x0f;
1504 *(cd->mcodeptr++) = 0xb7;
1505 /* XXX: why do reg and dreg have to be exchanged */
1506 emit_reg((dreg),(reg));
1510 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1511 emit_rex(1,(reg),(indexreg),(basereg));
1512 *(cd->mcodeptr++) = 0x0f;
1513 *(cd->mcodeptr++) = 0xbf;
1514 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1518 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1519 emit_rex(1,(reg),(indexreg),(basereg));
1520 *(cd->mcodeptr++) = 0x0f;
1521 *(cd->mcodeptr++) = 0xbe;
1522 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1526 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1527 emit_rex(1,(reg),(indexreg),(basereg));
1528 *(cd->mcodeptr++) = 0x0f;
1529 *(cd->mcodeptr++) = 0xb7;
1530 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1534 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1536 emit_rex(1,0,(indexreg),(basereg));
1537 *(cd->mcodeptr++) = 0xc7;
1538 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1543 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1545 emit_rex(0,0,(indexreg),(basereg));
1546 *(cd->mcodeptr++) = 0xc7;
1547 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1552 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1554 *(cd->mcodeptr++) = 0x66;
1555 emit_rex(0,0,(indexreg),(basereg));
1556 *(cd->mcodeptr++) = 0xc7;
1557 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1562 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1564 emit_rex(0,0,(indexreg),(basereg));
1565 *(cd->mcodeptr++) = 0xc6;
1566 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1571 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1573 emit_rex(1, dreg, 0, 0);
1574 *(cd->mcodeptr++) = 0x8b;
1575 emit_address_byte(0, dreg, 4);
1583 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1585 emit_rex(1,(reg),0,(dreg));
1586 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1587 emit_reg((reg),(dreg));
1591 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1593 emit_rex(0,(reg),0,(dreg));
1594 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1595 emit_reg((reg),(dreg));
1599 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1601 emit_rex(1,(reg),0,(basereg));
1602 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1603 emit_membase(cd, (basereg),(disp),(reg));
1607 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1609 emit_rex(0,(reg),0,(basereg));
1610 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1611 emit_membase(cd, (basereg),(disp),(reg));
1615 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1617 emit_rex(1,(reg),0,(basereg));
1618 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1619 emit_membase(cd, (basereg),(disp),(reg));
1623 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1625 emit_rex(0,(reg),0,(basereg));
1626 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1627 emit_membase(cd, (basereg),(disp),(reg));
1631 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1633 emit_rex(1,0,0,(dreg));
1634 *(cd->mcodeptr++) = 0x83;
1635 emit_reg((opc),(dreg));
1638 emit_rex(1,0,0,(dreg));
1639 *(cd->mcodeptr++) = 0x81;
1640 emit_reg((opc),(dreg));
1646 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1648 emit_rex(1,0,0,(dreg));
1649 *(cd->mcodeptr++) = 0x81;
1650 emit_reg((opc),(dreg));
1655 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1657 emit_rex(0,0,0,(dreg));
1658 *(cd->mcodeptr++) = 0x81;
1659 emit_reg((opc),(dreg));
1664 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1666 emit_rex(0,0,0,(dreg));
1667 *(cd->mcodeptr++) = 0x83;
1668 emit_reg((opc),(dreg));
1671 emit_rex(0,0,0,(dreg));
1672 *(cd->mcodeptr++) = 0x81;
1673 emit_reg((opc),(dreg));
1679 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1681 emit_rex(1,0,0,(basereg));
1682 *(cd->mcodeptr++) = 0x83;
1683 emit_membase(cd, (basereg),(disp),(opc));
1686 emit_rex(1,0,0,(basereg));
1687 *(cd->mcodeptr++) = 0x81;
1688 emit_membase(cd, (basereg),(disp),(opc));
1694 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1696 emit_rex(0,0,0,(basereg));
1697 *(cd->mcodeptr++) = 0x83;
1698 emit_membase(cd, (basereg),(disp),(opc));
1701 emit_rex(0,0,0,(basereg));
1702 *(cd->mcodeptr++) = 0x81;
1703 emit_membase(cd, (basereg),(disp),(opc));
1708 void emit_alu_memindex_reg(codegendata *cd, s8 opc, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg)
1710 emit_rex(1,(reg),(indexreg),(basereg));
1711 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1712 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1715 void emit_alul_memindex_reg(codegendata *cd, s8 opc, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg)
1717 emit_rex(0,(reg),(indexreg),(basereg));
1718 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1719 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1722 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1723 emit_rex(1,(reg),0,(dreg));
1724 *(cd->mcodeptr++) = 0x85;
1725 emit_reg((reg),(dreg));
1729 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1730 emit_rex(0,(reg),0,(dreg));
1731 *(cd->mcodeptr++) = 0x85;
1732 emit_reg((reg),(dreg));
1736 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1737 *(cd->mcodeptr++) = 0xf7;
1743 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1744 *(cd->mcodeptr++) = 0x66;
1745 *(cd->mcodeptr++) = 0xf7;
1751 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1752 *(cd->mcodeptr++) = 0xf6;
1758 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1759 emit_rex(1,(reg),0,(basereg));
1760 *(cd->mcodeptr++) = 0x8d;
1761 emit_membase(cd, (basereg),(disp),(reg));
1765 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1766 emit_rex(0,(reg),0,(basereg));
1767 *(cd->mcodeptr++) = 0x8d;
1768 emit_membase(cd, (basereg),(disp),(reg));
1772 void emit_incl_reg(codegendata *cd, s8 reg)
1774 *(cd->mcodeptr++) = 0xff;
1778 void emit_incq_reg(codegendata *cd, s8 reg)
1780 emit_rex(1,0,0,(reg));
1781 *(cd->mcodeptr++) = 0xff;
1785 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1787 emit_rex(0,0,0,(basereg));
1788 *(cd->mcodeptr++) = 0xff;
1789 emit_membase(cd, (basereg),(disp),0);
1792 void emit_incq_membase(codegendata *cd, s8 basereg, s8 disp)
1794 emit_rex(1,0,0,(basereg));
1795 *(cd->mcodeptr++) = 0xff;
1796 emit_membase(cd, (basereg),(disp),0);
1801 void emit_cltd(codegendata *cd) {
1802 *(cd->mcodeptr++) = 0x99;
1806 void emit_cqto(codegendata *cd) {
1808 *(cd->mcodeptr++) = 0x99;
1813 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1814 emit_rex(1,(dreg),0,(reg));
1815 *(cd->mcodeptr++) = 0x0f;
1816 *(cd->mcodeptr++) = 0xaf;
1817 emit_reg((dreg),(reg));
1821 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1822 emit_rex(0,(dreg),0,(reg));
1823 *(cd->mcodeptr++) = 0x0f;
1824 *(cd->mcodeptr++) = 0xaf;
1825 emit_reg((dreg),(reg));
1829 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1830 emit_rex(1,(dreg),0,(basereg));
1831 *(cd->mcodeptr++) = 0x0f;
1832 *(cd->mcodeptr++) = 0xaf;
1833 emit_membase(cd, (basereg),(disp),(dreg));
1837 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1838 emit_rex(0,(dreg),0,(basereg));
1839 *(cd->mcodeptr++) = 0x0f;
1840 *(cd->mcodeptr++) = 0xaf;
1841 emit_membase(cd, (basereg),(disp),(dreg));
1845 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1846 if (IS_IMM8((imm))) {
1847 emit_rex(1,0,0,(dreg));
1848 *(cd->mcodeptr++) = 0x6b;
1852 emit_rex(1,0,0,(dreg));
1853 *(cd->mcodeptr++) = 0x69;
1860 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1861 if (IS_IMM8((imm))) {
1862 emit_rex(1,(dreg),0,(reg));
1863 *(cd->mcodeptr++) = 0x6b;
1864 emit_reg((dreg),(reg));
1867 emit_rex(1,(dreg),0,(reg));
1868 *(cd->mcodeptr++) = 0x69;
1869 emit_reg((dreg),(reg));
1875 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1876 if (IS_IMM8((imm))) {
1877 emit_rex(0,(dreg),0,(reg));
1878 *(cd->mcodeptr++) = 0x6b;
1879 emit_reg((dreg),(reg));
1882 emit_rex(0,(dreg),0,(reg));
1883 *(cd->mcodeptr++) = 0x69;
1884 emit_reg((dreg),(reg));
1890 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1891 if (IS_IMM8((imm))) {
1892 emit_rex(1,(dreg),0,(basereg));
1893 *(cd->mcodeptr++) = 0x6b;
1894 emit_membase(cd, (basereg),(disp),(dreg));
1897 emit_rex(1,(dreg),0,(basereg));
1898 *(cd->mcodeptr++) = 0x69;
1899 emit_membase(cd, (basereg),(disp),(dreg));
1905 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1906 if (IS_IMM8((imm))) {
1907 emit_rex(0,(dreg),0,(basereg));
1908 *(cd->mcodeptr++) = 0x6b;
1909 emit_membase(cd, (basereg),(disp),(dreg));
1912 emit_rex(0,(dreg),0,(basereg));
1913 *(cd->mcodeptr++) = 0x69;
1914 emit_membase(cd, (basereg),(disp),(dreg));
1920 void emit_idiv_reg(codegendata *cd, s8 reg) {
1921 emit_rex(1,0,0,(reg));
1922 *(cd->mcodeptr++) = 0xf7;
1927 void emit_idivl_reg(codegendata *cd, s8 reg) {
1928 emit_rex(0,0,0,(reg));
1929 *(cd->mcodeptr++) = 0xf7;
1938 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1939 emit_rex(1,0,0,(reg));
1940 *(cd->mcodeptr++) = 0xd3;
1941 emit_reg((opc),(reg));
1945 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1946 emit_rex(0,0,0,(reg));
1947 *(cd->mcodeptr++) = 0xd3;
1948 emit_reg((opc),(reg));
1952 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1953 emit_rex(1,0,0,(basereg));
1954 *(cd->mcodeptr++) = 0xd3;
1955 emit_membase(cd, (basereg),(disp),(opc));
1959 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1960 emit_rex(0,0,0,(basereg));
1961 *(cd->mcodeptr++) = 0xd3;
1962 emit_membase(cd, (basereg),(disp),(opc));
1966 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1968 emit_rex(1,0,0,(dreg));
1969 *(cd->mcodeptr++) = 0xd1;
1970 emit_reg((opc),(dreg));
1972 emit_rex(1,0,0,(dreg));
1973 *(cd->mcodeptr++) = 0xc1;
1974 emit_reg((opc),(dreg));
1980 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1982 emit_rex(0,0,0,(dreg));
1983 *(cd->mcodeptr++) = 0xd1;
1984 emit_reg((opc),(dreg));
1986 emit_rex(0,0,0,(dreg));
1987 *(cd->mcodeptr++) = 0xc1;
1988 emit_reg((opc),(dreg));
1994 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1996 emit_rex(1,0,0,(basereg));
1997 *(cd->mcodeptr++) = 0xd1;
1998 emit_membase(cd, (basereg),(disp),(opc));
2000 emit_rex(1,0,0,(basereg));
2001 *(cd->mcodeptr++) = 0xc1;
2002 emit_membase(cd, (basereg),(disp),(opc));
2008 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
2010 emit_rex(0,0,0,(basereg));
2011 *(cd->mcodeptr++) = 0xd1;
2012 emit_membase(cd, (basereg),(disp),(opc));
2014 emit_rex(0,0,0,(basereg));
2015 *(cd->mcodeptr++) = 0xc1;
2016 emit_membase(cd, (basereg),(disp),(opc));
2026 void emit_jmp_imm(codegendata *cd, s8 imm) {
2027 *(cd->mcodeptr++) = 0xe9;
2031 /* like emit_jmp_imm but allows 8 bit optimization */
2032 void emit_jmp_imm2(codegendata *cd, s8 imm) {
2034 *(cd->mcodeptr++) = 0xeb;
2038 *(cd->mcodeptr++) = 0xe9;
2044 void emit_jmp_reg(codegendata *cd, s8 reg) {
2045 emit_rex(0,0,0,(reg));
2046 *(cd->mcodeptr++) = 0xff;
2051 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
2052 *(cd->mcodeptr++) = 0x0f;
2053 *(cd->mcodeptr++) = (0x80 + (opc));
2060 * conditional set and move operations
2063 /* we need the rex byte to get all low bytes */
2064 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
2066 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
2067 *(cd->mcodeptr++) = 0x0f;
2068 *(cd->mcodeptr++) = (0x90 + (opc));
2073 /* we need the rex byte to get all low bytes */
2074 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
2076 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
2077 *(cd->mcodeptr++) = 0x0f;
2078 *(cd->mcodeptr++) = (0x90 + (opc));
2079 emit_membase(cd, (basereg),(disp),0);
2083 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
2085 emit_rex(1,(dreg),0,(reg));
2086 *(cd->mcodeptr++) = 0x0f;
2087 *(cd->mcodeptr++) = (0x40 + (opc));
2088 emit_reg((dreg),(reg));
2092 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
2094 emit_rex(0,(dreg),0,(reg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = (0x40 + (opc));
2097 emit_reg((dreg),(reg));
2101 void emit_neg_reg(codegendata *cd, s8 reg)
2103 emit_rex(1,0,0,(reg));
2104 *(cd->mcodeptr++) = 0xf7;
2109 void emit_negl_reg(codegendata *cd, s8 reg)
2111 emit_rex(0,0,0,(reg));
2112 *(cd->mcodeptr++) = 0xf7;
2117 void emit_push_reg(codegendata *cd, s8 reg) {
2118 emit_rex(0,0,0,(reg));
2119 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
2123 void emit_push_imm(codegendata *cd, s8 imm) {
2124 *(cd->mcodeptr++) = 0x68;
2129 void emit_pop_reg(codegendata *cd, s8 reg) {
2130 emit_rex(0,0,0,(reg));
2131 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
2135 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2136 emit_rex(1,(reg),0,(dreg));
2137 *(cd->mcodeptr++) = 0x87;
2138 emit_reg((reg),(dreg));
2146 void emit_call_reg(codegendata *cd, s8 reg)
2148 emit_rex(0,0,0,(reg));
2149 *(cd->mcodeptr++) = 0xff;
2154 void emit_call_imm(codegendata *cd, s8 imm)
2156 *(cd->mcodeptr++) = 0xe8;
2161 void emit_call_mem(codegendata *cd, ptrint mem)
2163 *(cd->mcodeptr++) = 0xff;
2170 * floating point instructions (SSE2)
2172 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2173 *(cd->mcodeptr++) = 0xf2;
2174 emit_rex(0,(dreg),0,(reg));
2175 *(cd->mcodeptr++) = 0x0f;
2176 *(cd->mcodeptr++) = 0x58;
2177 emit_reg((dreg),(reg));
2181 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2182 *(cd->mcodeptr++) = 0xf3;
2183 emit_rex(0,(dreg),0,(reg));
2184 *(cd->mcodeptr++) = 0x0f;
2185 *(cd->mcodeptr++) = 0x58;
2186 emit_reg((dreg),(reg));
2190 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2191 *(cd->mcodeptr++) = 0xf3;
2192 emit_rex(1,(dreg),0,(reg));
2193 *(cd->mcodeptr++) = 0x0f;
2194 *(cd->mcodeptr++) = 0x2a;
2195 emit_reg((dreg),(reg));
2199 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2200 *(cd->mcodeptr++) = 0xf3;
2201 emit_rex(0,(dreg),0,(reg));
2202 *(cd->mcodeptr++) = 0x0f;
2203 *(cd->mcodeptr++) = 0x2a;
2204 emit_reg((dreg),(reg));
2208 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2209 *(cd->mcodeptr++) = 0xf2;
2210 emit_rex(1,(dreg),0,(reg));
2211 *(cd->mcodeptr++) = 0x0f;
2212 *(cd->mcodeptr++) = 0x2a;
2213 emit_reg((dreg),(reg));
2217 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2218 *(cd->mcodeptr++) = 0xf2;
2219 emit_rex(0,(dreg),0,(reg));
2220 *(cd->mcodeptr++) = 0x0f;
2221 *(cd->mcodeptr++) = 0x2a;
2222 emit_reg((dreg),(reg));
2226 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2227 *(cd->mcodeptr++) = 0xf3;
2228 emit_rex(0,(dreg),0,(reg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x5a;
2231 emit_reg((dreg),(reg));
2235 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2236 *(cd->mcodeptr++) = 0xf2;
2237 emit_rex(0,(dreg),0,(reg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x5a;
2240 emit_reg((dreg),(reg));
2244 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2245 *(cd->mcodeptr++) = 0xf3;
2246 emit_rex(1,(dreg),0,(reg));
2247 *(cd->mcodeptr++) = 0x0f;
2248 *(cd->mcodeptr++) = 0x2c;
2249 emit_reg((dreg),(reg));
2253 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2254 *(cd->mcodeptr++) = 0xf3;
2255 emit_rex(0,(dreg),0,(reg));
2256 *(cd->mcodeptr++) = 0x0f;
2257 *(cd->mcodeptr++) = 0x2c;
2258 emit_reg((dreg),(reg));
2262 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2263 *(cd->mcodeptr++) = 0xf2;
2264 emit_rex(1,(dreg),0,(reg));
2265 *(cd->mcodeptr++) = 0x0f;
2266 *(cd->mcodeptr++) = 0x2c;
2267 emit_reg((dreg),(reg));
2271 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2272 *(cd->mcodeptr++) = 0xf2;
2273 emit_rex(0,(dreg),0,(reg));
2274 *(cd->mcodeptr++) = 0x0f;
2275 *(cd->mcodeptr++) = 0x2c;
2276 emit_reg((dreg),(reg));
2280 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2281 *(cd->mcodeptr++) = 0xf3;
2282 emit_rex(0,(dreg),0,(reg));
2283 *(cd->mcodeptr++) = 0x0f;
2284 *(cd->mcodeptr++) = 0x5e;
2285 emit_reg((dreg),(reg));
2289 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2290 *(cd->mcodeptr++) = 0xf2;
2291 emit_rex(0,(dreg),0,(reg));
2292 *(cd->mcodeptr++) = 0x0f;
2293 *(cd->mcodeptr++) = 0x5e;
2294 emit_reg((dreg),(reg));
2298 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2299 *(cd->mcodeptr++) = 0x66;
2300 emit_rex(1,(freg),0,(reg));
2301 *(cd->mcodeptr++) = 0x0f;
2302 *(cd->mcodeptr++) = 0x6e;
2303 emit_reg((freg),(reg));
2307 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2308 *(cd->mcodeptr++) = 0x66;
2309 emit_rex(1,(freg),0,(reg));
2310 *(cd->mcodeptr++) = 0x0f;
2311 *(cd->mcodeptr++) = 0x7e;
2312 emit_reg((freg),(reg));
2316 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2317 *(cd->mcodeptr++) = 0x66;
2318 emit_rex(0,(reg),0,(basereg));
2319 *(cd->mcodeptr++) = 0x0f;
2320 *(cd->mcodeptr++) = 0x7e;
2321 emit_membase(cd, (basereg),(disp),(reg));
2325 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2326 *(cd->mcodeptr++) = 0x66;
2327 emit_rex(0,(reg),(indexreg),(basereg));
2328 *(cd->mcodeptr++) = 0x0f;
2329 *(cd->mcodeptr++) = 0x7e;
2330 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2334 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2335 *(cd->mcodeptr++) = 0x66;
2336 emit_rex(1,(dreg),0,(basereg));
2337 *(cd->mcodeptr++) = 0x0f;
2338 *(cd->mcodeptr++) = 0x6e;
2339 emit_membase(cd, (basereg),(disp),(dreg));
2343 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2344 *(cd->mcodeptr++) = 0x66;
2345 emit_rex(0,(dreg),0,(basereg));
2346 *(cd->mcodeptr++) = 0x0f;
2347 *(cd->mcodeptr++) = 0x6e;
2348 emit_membase(cd, (basereg),(disp),(dreg));
2352 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2353 *(cd->mcodeptr++) = 0x66;
2354 emit_rex(0,(dreg),(indexreg),(basereg));
2355 *(cd->mcodeptr++) = 0x0f;
2356 *(cd->mcodeptr++) = 0x6e;
2357 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2361 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2362 *(cd->mcodeptr++) = 0xf3;
2363 emit_rex(0,(dreg),0,(reg));
2364 *(cd->mcodeptr++) = 0x0f;
2365 *(cd->mcodeptr++) = 0x7e;
2366 emit_reg((dreg),(reg));
2370 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2371 *(cd->mcodeptr++) = 0x66;
2372 emit_rex(0,(reg),0,(basereg));
2373 *(cd->mcodeptr++) = 0x0f;
2374 *(cd->mcodeptr++) = 0xd6;
2375 emit_membase(cd, (basereg),(disp),(reg));
2379 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2380 *(cd->mcodeptr++) = 0xf3;
2381 emit_rex(0,(dreg),0,(basereg));
2382 *(cd->mcodeptr++) = 0x0f;
2383 *(cd->mcodeptr++) = 0x7e;
2384 emit_membase(cd, (basereg),(disp),(dreg));
2388 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2389 *(cd->mcodeptr++) = 0xf3;
2390 emit_rex(0,(reg),0,(dreg));
2391 *(cd->mcodeptr++) = 0x0f;
2392 *(cd->mcodeptr++) = 0x10;
2393 emit_reg((reg),(dreg));
2397 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2398 *(cd->mcodeptr++) = 0xf2;
2399 emit_rex(0,(reg),0,(dreg));
2400 *(cd->mcodeptr++) = 0x0f;
2401 *(cd->mcodeptr++) = 0x10;
2402 emit_reg((reg),(dreg));
2406 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2407 *(cd->mcodeptr++) = 0xf3;
2408 emit_rex(0,(reg),0,(basereg));
2409 *(cd->mcodeptr++) = 0x0f;
2410 *(cd->mcodeptr++) = 0x11;
2411 emit_membase(cd, (basereg),(disp),(reg));
2415 /* Always emit a REX byte, because the instruction size can be smaller when */
2416 /* all register indexes are smaller than 7. */
2417 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2418 *(cd->mcodeptr++) = 0xf3;
2419 emit_byte_rex((reg),0,(basereg));
2420 *(cd->mcodeptr++) = 0x0f;
2421 *(cd->mcodeptr++) = 0x11;
2422 emit_membase32(cd, (basereg),(disp),(reg));
2426 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2427 *(cd->mcodeptr++) = 0xf2;
2428 emit_rex(0,(reg),0,(basereg));
2429 *(cd->mcodeptr++) = 0x0f;
2430 *(cd->mcodeptr++) = 0x11;
2431 emit_membase(cd, (basereg),(disp),(reg));
2435 /* Always emit a REX byte, because the instruction size can be smaller when */
2436 /* all register indexes are smaller than 7. */
2437 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2438 *(cd->mcodeptr++) = 0xf2;
2439 emit_byte_rex((reg),0,(basereg));
2440 *(cd->mcodeptr++) = 0x0f;
2441 *(cd->mcodeptr++) = 0x11;
2442 emit_membase32(cd, (basereg),(disp),(reg));
2446 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2447 *(cd->mcodeptr++) = 0xf3;
2448 emit_rex(0,(dreg),0,(basereg));
2449 *(cd->mcodeptr++) = 0x0f;
2450 *(cd->mcodeptr++) = 0x10;
2451 emit_membase(cd, (basereg),(disp),(dreg));
2455 /* Always emit a REX byte, because the instruction size can be smaller when */
2456 /* all register indexes are smaller than 7. */
2457 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2458 *(cd->mcodeptr++) = 0xf3;
2459 emit_byte_rex((dreg),0,(basereg));
2460 *(cd->mcodeptr++) = 0x0f;
2461 *(cd->mcodeptr++) = 0x10;
2462 emit_membase32(cd, (basereg),(disp),(dreg));
2466 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2468 emit_rex(0,(dreg),0,(basereg));
2469 *(cd->mcodeptr++) = 0x0f;
2470 *(cd->mcodeptr++) = 0x12;
2471 emit_membase(cd, (basereg),(disp),(dreg));
2475 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2477 emit_rex(0,(reg),0,(basereg));
2478 *(cd->mcodeptr++) = 0x0f;
2479 *(cd->mcodeptr++) = 0x13;
2480 emit_membase(cd, (basereg),(disp),(reg));
2484 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2485 *(cd->mcodeptr++) = 0xf2;
2486 emit_rex(0,(dreg),0,(basereg));
2487 *(cd->mcodeptr++) = 0x0f;
2488 *(cd->mcodeptr++) = 0x10;
2489 emit_membase(cd, (basereg),(disp),(dreg));
2493 /* Always emit a REX byte, because the instruction size can be smaller when */
2494 /* all register indexes are smaller than 7. */
2495 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2496 *(cd->mcodeptr++) = 0xf2;
2497 emit_byte_rex((dreg),0,(basereg));
2498 *(cd->mcodeptr++) = 0x0f;
2499 *(cd->mcodeptr++) = 0x10;
2500 emit_membase32(cd, (basereg),(disp),(dreg));
2504 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2506 *(cd->mcodeptr++) = 0x66;
2507 emit_rex(0,(dreg),0,(basereg));
2508 *(cd->mcodeptr++) = 0x0f;
2509 *(cd->mcodeptr++) = 0x12;
2510 emit_membase(cd, (basereg),(disp),(dreg));
2514 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2516 *(cd->mcodeptr++) = 0x66;
2517 emit_rex(0,(reg),0,(basereg));
2518 *(cd->mcodeptr++) = 0x0f;
2519 *(cd->mcodeptr++) = 0x13;
2520 emit_membase(cd, (basereg),(disp),(reg));
2524 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2525 *(cd->mcodeptr++) = 0xf3;
2526 emit_rex(0,(reg),(indexreg),(basereg));
2527 *(cd->mcodeptr++) = 0x0f;
2528 *(cd->mcodeptr++) = 0x11;
2529 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2533 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2534 *(cd->mcodeptr++) = 0xf2;
2535 emit_rex(0,(reg),(indexreg),(basereg));
2536 *(cd->mcodeptr++) = 0x0f;
2537 *(cd->mcodeptr++) = 0x11;
2538 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2542 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2543 *(cd->mcodeptr++) = 0xf3;
2544 emit_rex(0,(dreg),(indexreg),(basereg));
2545 *(cd->mcodeptr++) = 0x0f;
2546 *(cd->mcodeptr++) = 0x10;
2547 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2551 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2552 *(cd->mcodeptr++) = 0xf2;
2553 emit_rex(0,(dreg),(indexreg),(basereg));
2554 *(cd->mcodeptr++) = 0x0f;
2555 *(cd->mcodeptr++) = 0x10;
2556 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2560 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2561 *(cd->mcodeptr++) = 0xf3;
2562 emit_rex(0,(dreg),0,(reg));
2563 *(cd->mcodeptr++) = 0x0f;
2564 *(cd->mcodeptr++) = 0x59;
2565 emit_reg((dreg),(reg));
2569 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2570 *(cd->mcodeptr++) = 0xf2;
2571 emit_rex(0,(dreg),0,(reg));
2572 *(cd->mcodeptr++) = 0x0f;
2573 *(cd->mcodeptr++) = 0x59;
2574 emit_reg((dreg),(reg));
2578 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2579 *(cd->mcodeptr++) = 0xf3;
2580 emit_rex(0,(dreg),0,(reg));
2581 *(cd->mcodeptr++) = 0x0f;
2582 *(cd->mcodeptr++) = 0x5c;
2583 emit_reg((dreg),(reg));
2587 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2588 *(cd->mcodeptr++) = 0xf2;
2589 emit_rex(0,(dreg),0,(reg));
2590 *(cd->mcodeptr++) = 0x0f;
2591 *(cd->mcodeptr++) = 0x5c;
2592 emit_reg((dreg),(reg));
2596 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2597 emit_rex(0,(dreg),0,(reg));
2598 *(cd->mcodeptr++) = 0x0f;
2599 *(cd->mcodeptr++) = 0x2e;
2600 emit_reg((dreg),(reg));
2604 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2605 *(cd->mcodeptr++) = 0x66;
2606 emit_rex(0,(dreg),0,(reg));
2607 *(cd->mcodeptr++) = 0x0f;
2608 *(cd->mcodeptr++) = 0x2e;
2609 emit_reg((dreg),(reg));
2613 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2614 emit_rex(0,(dreg),0,(reg));
2615 *(cd->mcodeptr++) = 0x0f;
2616 *(cd->mcodeptr++) = 0x57;
2617 emit_reg((dreg),(reg));
2621 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2622 emit_rex(0,(dreg),0,(basereg));
2623 *(cd->mcodeptr++) = 0x0f;
2624 *(cd->mcodeptr++) = 0x57;
2625 emit_membase(cd, (basereg),(disp),(dreg));
2629 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2630 *(cd->mcodeptr++) = 0x66;
2631 emit_rex(0,(dreg),0,(reg));
2632 *(cd->mcodeptr++) = 0x0f;
2633 *(cd->mcodeptr++) = 0x57;
2634 emit_reg((dreg),(reg));
2638 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2639 *(cd->mcodeptr++) = 0x66;
2640 emit_rex(0,(dreg),0,(basereg));
2641 *(cd->mcodeptr++) = 0x0f;
2642 *(cd->mcodeptr++) = 0x57;
2643 emit_membase(cd, (basereg),(disp),(dreg));
2647 /* system instructions ********************************************************/
2649 void emit_rdtsc(codegendata *cd)
2651 *(cd->mcodeptr++) = 0x0f;
2652 *(cd->mcodeptr++) = 0x31;
2655 void emit_mfence(codegendata *cd)
2657 *(cd->mcodeptr++) = 0x0f;
2658 *(cd->mcodeptr++) = 0xae;
2659 *(cd->mcodeptr++) = 0xf0;
2664 * These are local overrides for various environment variables in Emacs.
2665 * Please do not remove this and leave it at the end of the file, where
2666 * Emacs will automagically detect them.
2667 * ---------------------------------------------------------------------
2670 * indent-tabs-mode: t
2674 * vim:noexpandtab:sw=4:ts=4: