1 /* src/vm/jit/x86_64/codegen.h - code generation macros for x86_64
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Andreas Krall
32 $Id: codegen.h 5083 2006-07-06 14:19:04Z twisti $
46 #include "vm/jit/jit.h"
49 /* some defines ***************************************************************/
51 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
54 /* additional functions and macros to generate code ***************************/
56 #define CALCOFFSETBYTES(var, reg, val) \
57 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
58 else if ((s4) (val) != 0) (var) += 1; \
59 else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1;
62 #define CALCIMMEDIATEBYTES(var, val) \
63 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
67 /* gen_nullptr_check(objreg) */
69 #define gen_nullptr_check(objreg) \
73 codegen_add_nullpointerexception_ref(cd); \
77 #define gen_bound_check \
79 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));\
80 M_ICMP(REG_ITMP3, s2); \
82 codegen_add_arrayindexoutofboundsexception_ref(cd, s2); \
86 /* MCODECHECK(icnt) */
88 #define MCODECHECK(icnt) \
90 if ((cd->mcodeptr + (icnt)) > cd->mcodeend) \
91 codegen_increase(cd); \
95 #define ALIGNCODENOP \
96 if ((s4) (((ptrint) cd->mcodeptr) & 7)) { \
102 generates an integer-move from register a to b.
103 if a and b are the same int-register, no code will be generated.
106 #define M_INTMOVE(reg,dreg) \
108 if ((reg) != (dreg)) { \
115 generates a floating-point-move from register a to b.
116 if a and b are the same float-register, no code will be generated
119 #define M_FLTMOVE(reg,dreg) \
121 if ((reg) != (dreg)) { \
127 #define M_COPY(s,d) emit_copy(jd, iptr, (s), (d))
129 #define ICONST(r,c) \
131 if (iptr->val.i == 0) \
134 M_IMOV_IMM(iptr->val.i, d); \
137 /* M_IMOV_IMM(iptr->val.i, d); \ */
141 #define LCONST(r,c) \
143 if (iptr->val.l == 0) \
146 M_MOV_IMM(iptr->val.l, d); \
150 /* macros to create code ******************************************************/
152 #define M_MOV(a,b) emit_mov_reg_reg(cd, (a), (b))
153 #define M_MOV_IMM(a,b) emit_mov_imm_reg(cd, (u8) (a), (b))
155 #define M_IMOV(a,b) emit_movl_reg_reg(cd, (a), (b))
156 #define M_IMOV_IMM(a,b) emit_movl_imm_reg(cd, (u4) (a), (b))
158 #define M_FMOV(a,b) emit_movq_reg_reg(cd, (a), (b))
160 #define M_ILD(a,b,disp) emit_movl_membase_reg(cd, (b), (disp), (a))
161 #define M_LLD(a,b,disp) emit_mov_membase_reg(cd, (b), (disp), (a))
163 #define M_ILD32(a,b,disp) emit_movl_membase32_reg(cd, (b), (disp), (a))
164 #define M_LLD32(a,b,disp) emit_mov_membase32_reg(cd, (b), (disp), (a))
166 #define M_IST(a,b,disp) emit_movl_reg_membase(cd, (a), (b), (disp))
167 #define M_LST(a,b,disp) emit_mov_reg_membase(cd, (a), (b), (disp))
169 #define M_IST_IMM(a,b,disp) emit_movl_imm_membase(cd, (a), (b), (disp))
170 #define M_LST_IMM32(a,b,disp) emit_mov_imm_membase(cd, (a), (b), (disp))
172 #define M_IST32(a,b,disp) emit_movl_reg_membase32(cd, (a), (b), (disp))
173 #define M_LST32(a,b,disp) emit_mov_reg_membase32(cd, (a), (b), (disp))
175 #define M_IST32_IMM(a,b,disp) emit_movl_imm_membase32(cd, (a), (b), (disp))
176 #define M_LST32_IMM32(a,b,disp) emit_mov_imm_membase32(cd, (a), (b), (disp))
178 #define M_IADD(a,b) emit_alul_reg_reg(cd, ALU_ADD, (a), (b))
179 #define M_ISUB(a,b) emit_alul_reg_reg(cd, ALU_SUB, (a), (b))
180 #define M_IMUL(a,b) emit_imull_reg_reg(cd, (a), (b))
182 #define M_IADD_IMM(a,b) emit_alul_imm_reg(cd, ALU_ADD, (a), (b))
183 #define M_ISUB_IMM(a,b) emit_alul_imm_reg(cd, ALU_SUB, (a), (b))
184 #define M_IMUL_IMM(a,b,c) emit_imull_imm_reg_reg(cd, (b), (a), (c))
186 #define M_LADD(a,b) emit_alu_reg_reg(cd, ALU_ADD, (a), (b))
187 #define M_LSUB(a,b) emit_alu_reg_reg(cd, ALU_SUB, (a), (b))
188 #define M_LMUL(a,b) emit_imul_reg_reg(cd, (a), (b))
190 #define M_LADD_IMM(a,b) emit_alu_imm_reg(cd, ALU_ADD, (a), (b))
191 #define M_LSUB_IMM(a,b) emit_alu_imm_reg(cd, ALU_SUB, (a), (b))
192 #define M_LMUL_IMM(a,b,c) emit_imul_imm_reg_reg(cd, (b), (a), (c))
194 #define M_IINC(a) emit_incl_reg(cd, (a))
195 #define M_IDEC(a) emit_decl_reg(cd, (a))
197 #define M_ALD(a,b,disp) M_LLD(a,b,disp)
198 #define M_ALD32(a,b,disp) M_LLD32(a,b,disp)
200 #define M_AST(a,b,c) M_LST(a,b,c)
201 #define M_AST_IMM32(a,b,c) M_LST_IMM32(a,b,c)
203 #define M_AADD(a,b) M_LADD(a,b)
204 #define M_AADD_IMM(a,b) M_LADD_IMM(a,b)
205 #define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b)
207 #define M_LADD_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_ADD, (a), (b))
208 #define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b)
209 #define M_LSUB_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_SUB, (a), (b))
211 #define M_ILEA(a,b,c) emit_leal_membase_reg(cd, (a), (b), (c))
212 #define M_LLEA(a,b,c) emit_lea_membase_reg(cd, (a), (b), (c))
213 #define M_ALEA(a,b,c) M_LLEA(a,b,c)
215 #define M_INEG(a) emit_negl_reg(cd, (a))
216 #define M_LNEG(a) emit_neg_reg(cd, (a))
218 #define M_IAND(a,b) emit_alul_reg_reg(cd, ALU_AND, (a), (b))
219 #define M_IOR(a,b) emit_alul_reg_reg(cd, ALU_OR, (a), (b))
220 #define M_IXOR(a,b) emit_alul_reg_reg(cd, ALU_XOR, (a), (b))
222 #define M_IAND_IMM(a,b) emit_alul_imm_reg(cd, ALU_AND, (a), (b))
223 #define M_IOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_OR, (a), (b))
224 #define M_IXOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_XOR, (a), (b))
226 #define M_LAND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b))
227 #define M_LOR(a,b) emit_alu_reg_reg(cd, ALU_OR, (a), (b))
228 #define M_LXOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
230 #define M_LAND_IMM(a,b) emit_alu_imm_reg(cd, ALU_AND, (a), (b))
231 #define M_LOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_OR, (a), (b))
232 #define M_LXOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_XOR, (a), (b))
234 #define M_BSEXT(a,b) emit_movsbq_reg_reg(cd, (a), (b))
235 #define M_SSEXT(a,b) emit_movswq_reg_reg(cd, (a), (b))
236 #define M_ISEXT(a,b) emit_movslq_reg_reg(cd, (a), (b))
238 #define M_CZEXT(a,b) emit_movzwq_reg_reg(cd, (a), (b))
240 #define M_ISLL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHL, (a), (b))
241 #define M_ISRA_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SAR, (a), (b))
242 #define M_ISRL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHR, (a), (b))
244 #define M_LSLL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b))
245 #define M_LSRA_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b))
246 #define M_LSRL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b))
248 #define M_TEST(a) emit_test_reg_reg(cd, (a), (a))
249 #define M_ITEST(a) emit_testl_reg_reg(cd, (a), (a))
251 #define M_LCMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
252 #define M_LCMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
253 #define M_LCMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
254 #define M_LCMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
256 #define M_ICMP(a,b) emit_alul_reg_reg(cd, ALU_CMP, (a), (b))
257 #define M_ICMP_IMM(a,b) emit_alul_imm_reg(cd, ALU_CMP, (a), (b))
258 #define M_ICMP_IMM_MEMBASE(a,b,c) emit_alul_imm_membase(cd, ALU_CMP, (a), (b), (c))
259 #define M_ICMP_MEMBASE(a,b,c) emit_alul_membase_reg(cd, ALU_CMP, (a), (b), (c))
261 #define M_BEQ(disp) emit_jcc(cd, CC_E, (disp))
262 #define M_BNE(disp) emit_jcc(cd, CC_NE, (disp))
263 #define M_BLT(disp) emit_jcc(cd, CC_L, (disp))
264 #define M_BLE(disp) emit_jcc(cd, CC_LE, (disp))
265 #define M_BGE(disp) emit_jcc(cd, CC_GE, (disp))
266 #define M_BGT(disp) emit_jcc(cd, CC_G, (disp))
267 #define M_BAE(disp) emit_jcc(cd, CC_AE, (disp))
268 #define M_BA(disp) emit_jcc(cd, CC_A, (disp))
270 #define M_CMOVEQ(a,b) emit_cmovcc_reg_reg(cd, CC_E, (a), (b))
271 #define M_CMOVNE(a,b) emit_cmovcc_reg_reg(cd, CC_NE, (a), (b))
272 #define M_CMOVLT(a,b) emit_cmovcc_reg_reg(cd, CC_L, (a), (b))
273 #define M_CMOVLE(a,b) emit_cmovcc_reg_reg(cd, CC_LE, (a), (b))
274 #define M_CMOVGE(a,b) emit_cmovcc_reg_reg(cd, CC_GE, (a), (b))
275 #define M_CMOVGT(a,b) emit_cmovcc_reg_reg(cd, CC_G, (a), (b))
277 #define M_CMOVEQ_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_E, (a), (b))
278 #define M_CMOVNE_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_NE, (a), (b))
279 #define M_CMOVLT_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_L, (a), (b))
280 #define M_CMOVLE_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_LE, (a), (b))
281 #define M_CMOVGE_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_GE, (a), (b))
282 #define M_CMOVGT_MEMBASE(a,b,c) emit_cmovcc_reg_membase(cd, CC_G, (a), (b))
284 #define M_CMOVB(a,b) emit_cmovcc_reg_reg(cd, CC_B, (a), (b))
285 #define M_CMOVA(a,b) emit_cmovcc_reg_reg(cd, CC_A, (a), (b))
286 #define M_CMOVP(a,b) emit_cmovcc_reg_reg(cd, CC_P, (a), (b))
288 #define M_PUSH(a) emit_push_reg(cd, (a))
289 #define M_PUSH_IMM(a) emit_push_imm(cd, (a))
290 #define M_POP(a) emit_pop_reg(cd, (a))
292 #define M_JMP(a) emit_jmp_reg(cd, (a))
293 #define M_JMP_IMM(a) emit_jmp_imm(cd, (a))
294 #define M_CALL(a) emit_call_reg(cd, (a))
295 #define M_CALL_IMM(a) emit_call_imm(cd, (a))
296 #define M_RET emit_ret(cd)
298 #define M_NOP emit_nop(cd)
300 #define M_CLR(a) M_LXOR(a,a)
303 #define M_FLD(a,b,disp) emit_movss_membase_reg(cd, (b), (disp), (a))
304 #define M_DLD(a,b,disp) emit_movsd_membase_reg(cd, (b), (disp), (a))
306 #define M_FLD32(a,b,disp) emit_movss_membase32_reg(cd, (b), (disp), (a))
307 #define M_DLD32(a,b,disp) emit_movsd_membase32_reg(cd, (b), (disp), (a))
309 #define M_FST(a,b,disp) emit_movss_reg_membase(cd, (a), (b), (disp))
310 #define M_DST(a,b,disp) emit_movsd_reg_membase(cd, (a), (b), (disp))
312 #define M_FST32(a,b,disp) emit_movss_reg_membase32(cd, (a), (b), (disp))
313 #define M_DST32(a,b,disp) emit_movsd_reg_membase32(cd, (a), (b), (disp))
315 #define M_FADD(a,b) emit_addss_reg_reg(cd, (a), (b))
316 #define M_DADD(a,b) emit_addsd_reg_reg(cd, (a), (b))
317 #define M_FSUB(a,b) emit_subss_reg_reg(cd, (a), (b))
318 #define M_DSUB(a,b) emit_subsd_reg_reg(cd, (a), (b))
319 #define M_FMUL(a,b) emit_mulss_reg_reg(cd, (a), (b))
320 #define M_DMUL(a,b) emit_mulsd_reg_reg(cd, (a), (b))
321 #define M_FDIV(a,b) emit_divss_reg_reg(cd, (a), (b))
322 #define M_DDIV(a,b) emit_divsd_reg_reg(cd, (a), (b))
324 #define M_CVTIF(a,b) emit_cvtsi2ss_reg_reg(cd, (a), (b))
325 #define M_CVTID(a,b) emit_cvtsi2sd_reg_reg(cd, (a), (b))
326 #define M_CVTLF(a,b) emit_cvtsi2ssq_reg_reg(cd, (a), (b))
327 #define M_CVTLD(a,b) emit_cvtsi2sdq_reg_reg(cd, (a), (b))
328 #define M_CVTFI(a,b) emit_cvttss2si_reg_reg(cd, (a), (b))
329 #define M_CVTDI(a,b) emit_cvttsd2si_reg_reg(cd, (a), (b))
330 #define M_CVTFL(a,b) emit_cvttss2siq_reg_reg(cd, (a), (b))
331 #define M_CVTDL(a,b) emit_cvttsd2siq_reg_reg(cd, (a), (b))
333 #define M_CVTFD(a,b) emit_cvtss2sd_reg_reg(cd, (a), (b))
334 #define M_CVTDF(a,b) emit_cvtsd2ss_reg_reg(cd, (a), (b))
337 /* system instructions ********************************************************/
339 #define M_RDTSC emit_rdtsc(cd)
341 #define M_IINC_MEMBASE(a,b) emit_incl_membase(cd, (a), (b))
343 #define M_IADD_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADD, (a), (b), (c))
344 #define M_IADC_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_ADC, (a), (b), (c))
345 #define M_ISUB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SUB, (a), (b), (c))
346 #define M_ISBB_MEMBASE(a,b,c) emit_alul_reg_membase(cd, ALU_SBB, (a), (b), (c))
349 #define PROFILE_CYCLE_START \
351 if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) { \
355 M_MOV_IMM(code, REG_ITMP3); \
357 M_ISUB_MEMBASE(RAX, REG_ITMP3, OFFSET(codeinfo, cycles)); \
358 M_ISBB_MEMBASE(RDX, REG_ITMP3, OFFSET(codeinfo, cycles) + 4); \
365 #define PROFILE_CYCLE_STOP \
367 if (JITDATA_HAS_FLAG_INSTRUMENT(jd)) { \
371 M_MOV_IMM(code, REG_ITMP3); \
373 M_IADD_MEMBASE(RAX, REG_ITMP3, OFFSET(codeinfo, cycles)); \
374 M_IADC_MEMBASE(RDX, REG_ITMP3, OFFSET(codeinfo, cycles) + 4); \
382 /* function gen_resolvebranch **************************************************
384 backpatches a branch instruction
386 parameters: ip ... pointer to instruction after branch (void*)
387 so ... offset of instruction after branch (s8)
388 to ... offset of branch target (s8)
390 *******************************************************************************/
392 #define gen_resolvebranch(ip,so,to) \
393 *((s4*) ((ip) - 4)) = (s4) ((to) - (so));
395 #endif /* _CODEGEN_H */
399 * These are local overrides for various environment variables in Emacs.
400 * Please do not remove this and leave it at the end of the file, where
401 * Emacs will automagically detect them.
402 * ---------------------------------------------------------------------
405 * indent-tabs-mode: t