1 /* src/vm/jit/x86_64/codegen.h - code generation macros for x86_64
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Andreas Krall
32 $Id: codegen.h 4398 2006-01-31 23:43:08Z twisti $
46 #include "vm/jit/jit.h"
49 /* some defines ***************************************************************/
51 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
54 /* macros to create code ******************************************************/
56 /* immediate data union */
68 /* opcodes for alu instructions */
92 } X86_64_Shift_Opcode;
98 X86_64_CC_B = 2, X86_64_CC_C = 2, X86_64_CC_NAE = 2,
99 X86_64_CC_BE = 6, X86_64_CC_NA = 6,
100 X86_64_CC_AE = 3, X86_64_CC_NB = 3, X86_64_CC_NC = 3,
101 X86_64_CC_E = 4, X86_64_CC_Z = 4,
102 X86_64_CC_NE = 5, X86_64_CC_NZ = 5,
103 X86_64_CC_A = 7, X86_64_CC_NBE = 7,
104 X86_64_CC_S = 8, X86_64_CC_LZ = 8,
105 X86_64_CC_NS = 9, X86_64_CC_GEZ = 9,
106 X86_64_CC_P = 0x0a, X86_64_CC_PE = 0x0a,
107 X86_64_CC_NP = 0x0b, X86_64_CC_PO = 0x0b,
108 X86_64_CC_L = 0x0c, X86_64_CC_NGE = 0x0c,
109 X86_64_CC_GE = 0x0d, X86_64_CC_NL = 0x0d,
110 X86_64_CC_LE = 0x0e, X86_64_CC_NG = 0x0e,
111 X86_64_CC_G = 0x0f, X86_64_CC_NLE = 0x0f,
116 #define IS_IMM8(imm) \
117 (((long) (imm) >= -128) && ((long) (imm) <= 127))
120 #define IS_IMM32(imm) \
121 (((long) (imm) >= (-2147483647-1)) && ((long) (imm) <= 2147483647))
124 /* modrm and stuff */
126 #define x86_64_address_byte(mod,reg,rm) \
127 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | ((rm) & 0x07));
130 #define x86_64_emit_reg(reg,rm) \
131 x86_64_address_byte(3,(reg),(rm));
134 #define x86_64_emit_rex(size,reg,index,rm) \
135 if (((size) == 1) || ((reg) > 7) || ((index) > 7) || ((rm) > 7)) { \
136 *(cd->mcodeptr++) = (0x40 | (((size) & 0x01) << 3) | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01)); \
140 #define x86_64_emit_byte_rex(reg,index,rm) \
141 *(cd->mcodeptr++) = (0x40 | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01));
144 #define x86_64_emit_mem(r,disp) \
146 x86_64_address_byte(0,(r),5); \
147 x86_64_emit_imm32((disp)); \
151 #define x86_64_emit_membase(basereg,disp,dreg) \
153 if ((basereg) == REG_SP || (basereg) == R12) { \
155 x86_64_address_byte(0,(dreg),REG_SP); \
156 x86_64_address_byte(0,REG_SP,REG_SP); \
157 } else if (IS_IMM8((disp))) { \
158 x86_64_address_byte(1,(dreg),REG_SP); \
159 x86_64_address_byte(0,REG_SP,REG_SP); \
160 x86_64_emit_imm8((disp)); \
162 x86_64_address_byte(2,(dreg),REG_SP); \
163 x86_64_address_byte(0,REG_SP,REG_SP); \
164 x86_64_emit_imm32((disp)); \
168 if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
169 x86_64_address_byte(0,(dreg),(basereg)); \
173 if ((basereg) == RIP) { \
174 x86_64_address_byte(0,(dreg),RBP); \
175 x86_64_emit_imm32((disp)); \
179 if (IS_IMM8((disp))) { \
180 x86_64_address_byte(1,(dreg),(basereg)); \
181 x86_64_emit_imm8((disp)); \
183 x86_64_address_byte(2,(dreg),(basereg)); \
184 x86_64_emit_imm32((disp)); \
189 #define x86_64_emit_membase32(basereg,disp,dreg) \
191 if ((basereg) == REG_SP || (basereg) == R12) { \
192 x86_64_address_byte(2,(dreg),REG_SP); \
193 x86_64_address_byte(0,REG_SP,REG_SP); \
194 x86_64_emit_imm32((disp)); \
196 x86_64_address_byte(2,(dreg),(basereg)); \
197 x86_64_emit_imm32((disp)); \
202 #define x86_64_emit_memindex(reg,disp,basereg,indexreg,scale) \
204 if ((basereg) == -1) { \
205 x86_64_address_byte(0,(reg),4); \
206 x86_64_address_byte((scale),(indexreg),5); \
207 x86_64_emit_imm32((disp)); \
209 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
210 x86_64_address_byte(0,(reg),4); \
211 x86_64_address_byte((scale),(indexreg),(basereg)); \
213 } else if (IS_IMM8((disp))) { \
214 x86_64_address_byte(1,(reg),4); \
215 x86_64_address_byte((scale),(indexreg),(basereg)); \
216 x86_64_emit_imm8 ((disp)); \
219 x86_64_address_byte(2,(reg),4); \
220 x86_64_address_byte((scale),(indexreg),(basereg)); \
221 x86_64_emit_imm32((disp)); \
226 #define x86_64_emit_imm8(imm) \
227 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
230 #define x86_64_emit_imm16(imm) \
232 x86_64_imm_buf imb; \
233 imb.i = (s4) (imm); \
234 *(cd->mcodeptr++) = imb.b[0]; \
235 *(cd->mcodeptr++) = imb.b[1]; \
239 #define x86_64_emit_imm32(imm) \
241 x86_64_imm_buf imb; \
242 imb.i = (s4) (imm); \
243 *(cd->mcodeptr++) = imb.b[0]; \
244 *(cd->mcodeptr++) = imb.b[1]; \
245 *(cd->mcodeptr++) = imb.b[2]; \
246 *(cd->mcodeptr++) = imb.b[3]; \
250 #define x86_64_emit_imm64(imm) \
252 x86_64_imm_buf imb; \
253 imb.l = (s8) (imm); \
254 *(cd->mcodeptr++) = imb.b[0]; \
255 *(cd->mcodeptr++) = imb.b[1]; \
256 *(cd->mcodeptr++) = imb.b[2]; \
257 *(cd->mcodeptr++) = imb.b[3]; \
258 *(cd->mcodeptr++) = imb.b[4]; \
259 *(cd->mcodeptr++) = imb.b[5]; \
260 *(cd->mcodeptr++) = imb.b[6]; \
261 *(cd->mcodeptr++) = imb.b[7]; \
265 /* additional functions and macros to generate code ***************************/
267 #define CALCOFFSETBYTES(var, reg, val) \
268 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
269 else if ((s4) (val) != 0) (var) += 1; \
270 else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1;
273 #define CALCIMMEDIATEBYTES(var, val) \
274 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
278 /* gen_nullptr_check(objreg) */
280 #define gen_nullptr_check(objreg) \
282 x86_64_test_reg_reg(cd, (objreg), (objreg)); \
283 x86_64_jcc(cd, X86_64_CC_E, 0); \
284 codegen_addxnullrefs(cd, cd->mcodeptr); \
288 #define gen_bound_check \
290 x86_64_alul_membase_reg(cd, X86_64_CMP, s1, OFFSET(java_arrayheader, size), s2); \
291 x86_64_jcc(cd, X86_64_CC_AE, 0); \
292 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
296 #define gen_div_check(v) \
298 if ((v)->flags & INMEMORY) { \
299 x86_64_alu_imm_membase(cd, X86_64_CMP, 0, REG_SP, src->regoff * 8); \
301 x86_64_test_reg_reg(cd, src->regoff, src->regoff); \
303 x86_64_jcc(cd, X86_64_CC_E, 0); \
304 codegen_addxdivrefs(cd, cd->mcodeptr); \
308 /* MCODECHECK(icnt) */
310 #define MCODECHECK(icnt) \
311 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
312 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
315 generates an integer-move from register a to b.
316 if a and b are the same int-register, no code will be generated.
319 #define M_INTMOVE(reg,dreg) \
321 if ((reg) != (dreg)) { \
328 generates a floating-point-move from register a to b.
329 if a and b are the same float-register, no code will be generated
332 #define M_FLTMOVE(reg,dreg) \
334 if ((reg) != (dreg)) { \
341 this function generates code to fetch data from a pseudo-register
342 into a real register.
343 If the pseudo-register has actually been assigned to a real
344 register, no code will be emitted, since following operations
345 can use this register directly.
347 v: pseudoregister to be fetched from
348 tempregnum: temporary register to be used if v is actually spilled to ram
350 return: the register number, where the operand can be found after
351 fetching (this wil be either tempregnum or the register
352 number allready given to v)
355 #define var_to_reg_int(regnr,v,tempnr) \
356 if ((v)->flags & INMEMORY) { \
358 if ((v)->type == TYPE_INT) { \
359 x86_64_movl_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
361 x86_64_mov_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
365 regnr = (v)->regoff; \
370 #define var_to_reg_flt(regnr,v,tempnr) \
371 if ((v)->flags & INMEMORY) { \
373 if ((v)->type == TYPE_FLT) { \
374 x86_64_movlps_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
376 x86_64_movlpd_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
378 /* x86_64_movq_membase_reg(REG_SP, (v)->regoff * 8, tempnr);*/ \
381 regnr = (v)->regoff; \
385 /* store_reg_to_var_xxx:
386 This function generates the code to store the result of an operation
387 back into a spilled pseudo-variable.
388 If the pseudo-variable has not been spilled in the first place, this
389 function will generate nothing.
391 v ............ Pseudovariable
392 tempregnum ... Number of the temporary registers as returned by
396 #define store_reg_to_var_int(sptr, tempregnum) \
397 if ((sptr)->flags & INMEMORY) { \
399 x86_64_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
403 #define store_reg_to_var_flt(sptr, tempregnum) \
404 if ((sptr)->flags & INMEMORY) { \
406 x86_64_movq_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
410 #define M_COPY(from,to) \
411 d = reg_of_var(rd, to, REG_ITMP1); \
412 if ((from->regoff != to->regoff) || \
413 ((from->flags ^ to->flags) & INMEMORY)) { \
414 if (IS_FLT_DBL_TYPE(from->type)) { \
415 var_to_reg_flt(s1, from, d); \
417 store_reg_to_var_flt(to, d); \
419 var_to_reg_int(s1, from, d); \
421 store_reg_to_var_int(to, d); \
426 /* macros to create code ******************************************************/
428 #define M_MOV(a,b) x86_64_mov_reg_reg(cd, (a), (b))
429 #define M_MOV_IMM(a,b) x86_64_mov_imm_reg(cd, (a), (b))
431 #define M_FMOV(a,b) x86_64_movq_reg_reg(cd, (a), (b))
433 #define M_IMOV_IMM(a,b) x86_64_movl_imm_reg(cd, (a), (b))
435 #define M_ILD(a,b,disp) x86_64_movl_membase_reg(cd, (b), (disp), (a))
436 #define M_LLD(a,b,disp) x86_64_mov_membase_reg(cd, (b), (disp), (a))
437 #define M_DLD(a,b,disp) x86_64_movq_membase_reg(cd, (b), (disp), (a))
439 #define M_ILD32(a,b,disp) x86_64_movl_membase32_reg(cd, (b), (disp), (a))
440 #define M_LLD32(a,b,disp) x86_64_mov_membase32_reg(cd, (b), (disp), (a))
442 #define M_IST(a,b,disp) x86_64_movl_reg_membase(cd, (a), (b), (disp))
443 #define M_LST(a,b,disp) x86_64_mov_reg_membase(cd, (a), (b), (disp))
444 #define M_DST(a,b,disp) x86_64_movq_reg_membase(cd, (a), (b), (disp))
446 #define M_IST_IMM(a,b,disp) x86_64_movl_imm_membase(cd, (a), (b), (disp))
447 #define M_LST_IMM32(a,b,disp) x86_64_mov_imm_membase(cd, (a), (b), (disp))
449 #define M_IST32(a,b,disp) x86_64_movl_reg_membase32(cd, (a), (b), (disp))
450 #define M_LST32(a,b,disp) x86_64_mov_reg_membase32(cd, (a), (b), (disp))
452 #define M_IST32_IMM(a,b,disp) x86_64_movl_imm_membase32(cd, (a), (b), (disp))
453 #define M_LST32_IMM32(a,b,disp) x86_64_mov_imm_membase32(cd, (a), (b), (disp))
455 #define M_LADD(a,b) x86_64_alu_reg_reg(cd, X86_64_ADD, (a), (b))
456 #define M_LADD_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_ADD, (a), (b))
457 #define M_LSUB(a,b) x86_64_alu_reg_reg(cd, X86_64_SUB, (a), (b))
458 #define M_LSUB_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_SUB, (a), (b))
460 #define M_IINC_MEMBASE(a,b) x86_64_incl_membase(cd, (a), (b))
462 #define M_IADD_MEMBASE(a,b,c) x86_64_alul_reg_membase(cd, X86_64_ADD, (a), (b), (c))
463 #define M_IADC_MEMBASE(a,b,c) x86_64_alul_reg_membase(cd, X86_64_ADC, (a), (b), (c))
464 #define M_ISUB_MEMBASE(a,b,c) x86_64_alul_reg_membase(cd, X86_64_SUB, (a), (b), (c))
465 #define M_ISBB_MEMBASE(a,b,c) x86_64_alul_reg_membase(cd, X86_64_SBB, (a), (b), (c))
467 #define M_ALD(a,b,c) M_LLD(a,b,c)
468 #define M_AST(a,b,c) M_LST(a,b,c)
469 #define M_AST_IMM32(a,b,c) M_LST_IMM32(a,b,c)
470 #define M_AADD(a,b) M_LADD(a,b)
471 #define M_AADD_IMM(a,b) M_LADD_IMM(a,b)
472 #define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b)
474 #define M_LADD_IMM32(a,b) x86_64_alu_imm32_reg(cd, X86_64_ADD, (a), (b))
475 #define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b)
476 #define M_LSUB_IMM32(a,b) x86_64_alu_imm32_reg(cd, X86_64_SUB, (a), (b))
478 #define M_ILEA(a,b,c) x86_64_leal_membase_reg(cd, (a), (b), (c))
479 #define M_LLEA(a,b,c) x86_64_lea_membase_reg(cd, (a), (b), (c))
480 #define M_ALEA(a,b,c) M_LLEA(a,b,c)
482 #define M_AND(a,b) x86_64_alu_reg_reg(cd, X86_64_AND, (a), (b))
483 #define M_XOR(a,b) x86_64_alu_reg_reg(cd, X86_64_XOR, (a), (b))
485 #define M_IAND(a,b) x86_64_alul_reg_reg(cd, X86_64_AND, (a), (b))
486 #define M_IAND_IMM(a,b) x86_64_alul_imm_reg(cd, X86_64_AND, (a), (b))
487 #define M_IXOR(a,b) x86_64_alul_reg_reg(cd, X86_64_XOR, (a), (b))
489 #define M_TEST(a) x86_64_test_reg_reg(cd, (a), (a))
490 #define M_ITEST(a) x86_64_testl_reg_reg(cd, (a), (a))
492 #define M_CMP(a,b) x86_64_alu_reg_reg(cd, X86_64_CMP, (a), (b))
493 #define M_CMP_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_CMP, (a), (b))
494 #define M_CMP_IMM_MEMBASE(a,b,c) x86_64_alu_imm_membase(cd, X86_64_CMP, (a), (b), (c))
495 #define M_CMP_MEMBASE(a,b,c) x86_64_alu_membase_reg(cd, X86_64_CMP, (a), (b), (c))
497 #define M_ICMP(a,b) x86_64_alul_reg_reg(cd, X86_64_CMP, (a), (b))
498 #define M_ICMP_IMM(a,b) x86_64_alul_imm_reg(cd, X86_64_CMP, (a), (b))
499 #define M_ICMP_IMM_MEMBASE(a,b,c) x86_64_alul_imm_membase(cd, X86_64_CMP, (a), (b), (c))
501 #define M_BEQ(disp) x86_64_jcc(cd, X86_64_CC_E, (disp))
502 #define M_BNE(disp) x86_64_jcc(cd, X86_64_CC_NE, (disp))
503 #define M_BLE(disp) x86_64_jcc(cd, X86_64_CC_LE, (disp))
504 #define M_BA(disp) x86_64_jcc(cd, X86_64_CC_A, (disp))
506 #define M_CMOVEQ(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_E, (a), (b))
507 #define M_CMOVNE(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_NE, (a), (b))
508 #define M_CMOVLT(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_L, (a), (b))
509 #define M_CMOVLE(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_LE, (a), (b))
510 #define M_CMOVGE(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_GE, (a), (b))
511 #define M_CMOVGT(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_G, (a), (b))
513 #define M_CMOVB(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_B, (a), (b))
514 #define M_CMOVA(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_A, (a), (b))
515 #define M_CMOVP(a,b) x86_64_cmovcc_reg_reg(cd, X86_64_CC_P, (a), (b))
517 #define M_PUSH(a) x86_64_push_reg(cd, (a))
518 #define M_PUSH_IMM(a) x86_64_push_imm(cd, (a))
519 #define M_POP(a) x86_64_pop_reg(cd, (a))
521 #define M_JMP(a) x86_64_jmp_reg(cd, (a))
522 #define M_JMP_IMM(a) x86_64_jmp_imm(cd, (a))
523 #define M_CALL(a) x86_64_call_reg(cd, (a))
524 #define M_CALL_IMM(a) x86_64_call_imm(cd, (a))
525 #define M_RET x86_64_ret(cd)
527 #define M_NOP x86_64_nop(cd)
529 #define M_CLR(a) M_XOR(a,a)
532 /* system instructions ********************************************************/
534 #define M_RDTSC emit_rdtsc(cd)
536 #define PROFILE_CYCLE_START \
542 M_MOV_IMM((ptrint) m, REG_ITMP3); \
544 M_ISUB_MEMBASE(RAX, REG_ITMP3, OFFSET(methodinfo, cycles)); \
545 M_ISBB_MEMBASE(RDX, REG_ITMP3, OFFSET(methodinfo, cycles) + 4); \
552 #define PROFILE_CYCLE_STOP \
558 M_MOV_IMM((ptrint) m, REG_ITMP3); \
560 M_IADD_MEMBASE(RAX, REG_ITMP3, OFFSET(methodinfo, cycles)); \
561 M_IADC_MEMBASE(RDX, REG_ITMP3, OFFSET(methodinfo, cycles) + 4); \
569 /* function gen_resolvebranch **************************************************
571 backpatches a branch instruction
573 parameters: ip ... pointer to instruction after branch (void*)
574 so ... offset of instruction after branch (s8)
575 to ... offset of branch target (s8)
577 *******************************************************************************/
579 #define gen_resolvebranch(ip,so,to) \
580 *((s4*) ((ip) - 4)) = (s4) ((to) - (so));
582 #endif /* _CODEGEN_H */
586 * These are local overrides for various environment variables in Emacs.
587 * Please do not remove this and leave it at the end of the file, where
588 * Emacs will automagically detect them.
589 * ---------------------------------------------------------------------
592 * indent-tabs-mode: t