1 /* src/vm/jit/x86_64/codegen.h - code generation macros for x86_64
3 Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
4 R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
5 C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
6 Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
31 $Id: codegen.h 3620 2005-11-07 18:45:19Z twisti $
44 /* some defines ***************************************************************/
46 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
49 /* macros to create code ******************************************************/
51 /* immediate data union */
63 /* opcodes for alu instructions */
87 } X86_64_Shift_Opcode;
93 X86_64_CC_B = 2, X86_64_CC_C = 2, X86_64_CC_NAE = 2,
94 X86_64_CC_BE = 6, X86_64_CC_NA = 6,
95 X86_64_CC_AE = 3, X86_64_CC_NB = 3, X86_64_CC_NC = 3,
96 X86_64_CC_E = 4, X86_64_CC_Z = 4,
97 X86_64_CC_NE = 5, X86_64_CC_NZ = 5,
98 X86_64_CC_A = 7, X86_64_CC_NBE = 7,
99 X86_64_CC_S = 8, X86_64_CC_LZ = 8,
100 X86_64_CC_NS = 9, X86_64_CC_GEZ = 9,
101 X86_64_CC_P = 0x0a, X86_64_CC_PE = 0x0a,
102 X86_64_CC_NP = 0x0b, X86_64_CC_PO = 0x0b,
103 X86_64_CC_L = 0x0c, X86_64_CC_NGE = 0x0c,
104 X86_64_CC_GE = 0x0d, X86_64_CC_NL = 0x0d,
105 X86_64_CC_LE = 0x0e, X86_64_CC_NG = 0x0e,
106 X86_64_CC_G = 0x0f, X86_64_CC_NLE = 0x0f,
111 #define IS_IMM8(imm) \
112 (((long) (imm) >= -128) && ((long) (imm) <= 127))
115 #define IS_IMM32(imm) \
116 (((long) (imm) >= (-2147483647-1)) && ((long) (imm) <= 2147483647))
119 /* modrm and stuff */
121 #define x86_64_address_byte(mod,reg,rm) \
122 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | ((rm) & 0x07));
125 #define x86_64_emit_reg(reg,rm) \
126 x86_64_address_byte(3,(reg),(rm));
129 #define x86_64_emit_rex(size,reg,index,rm) \
130 if ((size) == 1 || (reg) > 7 || (index) > 7 || (rm) > 7) { \
131 *(cd->mcodeptr++) = (0x40 | (((size) & 0x01) << 3) | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01)); \
135 #define x86_64_emit_byte_rex(reg,index,rm) \
136 *(cd->mcodeptr++) = (0x40 | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01));
139 #define x86_64_emit_mem(r,disp) \
141 x86_64_address_byte(0,(r),5); \
142 x86_64_emit_imm32((disp)); \
146 #define x86_64_emit_membase(basereg,disp,dreg) \
148 if ((basereg) == REG_SP || (basereg) == R12) { \
150 x86_64_address_byte(0,(dreg),REG_SP); \
151 x86_64_address_byte(0,REG_SP,REG_SP); \
152 } else if (IS_IMM8((disp))) { \
153 x86_64_address_byte(1,(dreg),REG_SP); \
154 x86_64_address_byte(0,REG_SP,REG_SP); \
155 x86_64_emit_imm8((disp)); \
157 x86_64_address_byte(2,(dreg),REG_SP); \
158 x86_64_address_byte(0,REG_SP,REG_SP); \
159 x86_64_emit_imm32((disp)); \
163 if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
164 x86_64_address_byte(0,(dreg),(basereg)); \
168 if ((basereg) == RIP) { \
169 x86_64_address_byte(0,(dreg),RBP); \
170 x86_64_emit_imm32((disp)); \
174 if (IS_IMM8((disp))) { \
175 x86_64_address_byte(1,(dreg),(basereg)); \
176 x86_64_emit_imm8((disp)); \
178 x86_64_address_byte(2,(dreg),(basereg)); \
179 x86_64_emit_imm32((disp)); \
184 #define x86_64_emit_membase32(basereg,disp,dreg) \
186 if ((basereg) == REG_SP || (basereg) == R12) { \
187 x86_64_address_byte(2,(dreg),REG_SP); \
188 x86_64_address_byte(0,REG_SP,REG_SP); \
189 x86_64_emit_imm32((disp)); \
191 x86_64_address_byte(2,(dreg),(basereg)); \
192 x86_64_emit_imm32((disp)); \
197 #define x86_64_emit_memindex(reg,disp,basereg,indexreg,scale) \
199 if ((basereg) == -1) { \
200 x86_64_address_byte(0,(reg),4); \
201 x86_64_address_byte((scale),(indexreg),5); \
202 x86_64_emit_imm32((disp)); \
204 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
205 x86_64_address_byte(0,(reg),4); \
206 x86_64_address_byte((scale),(indexreg),(basereg)); \
208 } else if (IS_IMM8((disp))) { \
209 x86_64_address_byte(1,(reg),4); \
210 x86_64_address_byte((scale),(indexreg),(basereg)); \
211 x86_64_emit_imm8 ((disp)); \
214 x86_64_address_byte(2,(reg),4); \
215 x86_64_address_byte((scale),(indexreg),(basereg)); \
216 x86_64_emit_imm32((disp)); \
221 #define x86_64_emit_imm8(imm) \
222 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
225 #define x86_64_emit_imm16(imm) \
227 x86_64_imm_buf imb; \
228 imb.i = (s4) (imm); \
229 *(cd->mcodeptr++) = imb.b[0]; \
230 *(cd->mcodeptr++) = imb.b[1]; \
234 #define x86_64_emit_imm32(imm) \
236 x86_64_imm_buf imb; \
237 imb.i = (s4) (imm); \
238 *(cd->mcodeptr++) = imb.b[0]; \
239 *(cd->mcodeptr++) = imb.b[1]; \
240 *(cd->mcodeptr++) = imb.b[2]; \
241 *(cd->mcodeptr++) = imb.b[3]; \
245 #define x86_64_emit_imm64(imm) \
247 x86_64_imm_buf imb; \
248 imb.l = (s8) (imm); \
249 *(cd->mcodeptr++) = imb.b[0]; \
250 *(cd->mcodeptr++) = imb.b[1]; \
251 *(cd->mcodeptr++) = imb.b[2]; \
252 *(cd->mcodeptr++) = imb.b[3]; \
253 *(cd->mcodeptr++) = imb.b[4]; \
254 *(cd->mcodeptr++) = imb.b[5]; \
255 *(cd->mcodeptr++) = imb.b[6]; \
256 *(cd->mcodeptr++) = imb.b[7]; \
260 /* additional functions and macros to generate code ***************************/
263 #define COUNT_SPILLS count_spills++
269 #define CALCOFFSETBYTES(var, reg, val) \
270 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
271 else if ((s4) (val) != 0) (var) += 1; \
272 else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1;
275 #define CALCIMMEDIATEBYTES(var, val) \
276 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
280 /* gen_nullptr_check(objreg) */
282 #define gen_nullptr_check(objreg) \
284 x86_64_test_reg_reg(cd, (objreg), (objreg)); \
285 x86_64_jcc(cd, X86_64_CC_E, 0); \
286 codegen_addxnullrefs(cd, cd->mcodeptr); \
290 #define gen_bound_check \
292 x86_64_alul_membase_reg(cd, X86_64_CMP, s1, OFFSET(java_arrayheader, size), s2); \
293 x86_64_jcc(cd, X86_64_CC_AE, 0); \
294 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
298 #define gen_div_check(v) \
300 if ((v)->flags & INMEMORY) { \
301 x86_64_alu_imm_membase(cd, X86_64_CMP, 0, REG_SP, src->regoff * 8); \
303 x86_64_test_reg_reg(cd, src->regoff, src->regoff); \
305 x86_64_jcc(cd, X86_64_CC_E, 0); \
306 codegen_addxdivrefs(cd, cd->mcodeptr); \
310 /* MCODECHECK(icnt) */
312 #define MCODECHECK(icnt) \
313 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
314 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
317 generates an integer-move from register a to b.
318 if a and b are the same int-register, no code will be generated.
321 #define M_INTMOVE(reg,dreg) \
322 if ((reg) != (dreg)) { \
323 x86_64_mov_reg_reg(cd, (reg),(dreg)); \
328 generates a floating-point-move from register a to b.
329 if a and b are the same float-register, no code will be generated
332 #define M_FLTMOVE(reg,dreg) \
333 if ((reg) != (dreg)) { \
334 x86_64_movq_reg_reg(cd, (reg),(dreg)); \
339 this function generates code to fetch data from a pseudo-register
340 into a real register.
341 If the pseudo-register has actually been assigned to a real
342 register, no code will be emitted, since following operations
343 can use this register directly.
345 v: pseudoregister to be fetched from
346 tempregnum: temporary register to be used if v is actually spilled to ram
348 return: the register number, where the operand can be found after
349 fetching (this wil be either tempregnum or the register
350 number allready given to v)
353 #define var_to_reg_int(regnr,v,tempnr) \
354 if ((v)->flags & INMEMORY) { \
356 if ((v)->type == TYPE_INT) { \
357 x86_64_movl_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
359 x86_64_mov_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
363 regnr = (v)->regoff; \
368 #define var_to_reg_flt(regnr,v,tempnr) \
369 if ((v)->flags & INMEMORY) { \
371 if ((v)->type == TYPE_FLT) { \
372 x86_64_movlps_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
374 x86_64_movlpd_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
376 /* x86_64_movq_membase_reg(REG_SP, (v)->regoff * 8, tempnr);*/ \
379 regnr = (v)->regoff; \
383 /* store_reg_to_var_xxx:
384 This function generates the code to store the result of an operation
385 back into a spilled pseudo-variable.
386 If the pseudo-variable has not been spilled in the first place, this
387 function will generate nothing.
389 v ............ Pseudovariable
390 tempregnum ... Number of the temporary registers as returned by
394 #define store_reg_to_var_int(sptr, tempregnum) \
395 if ((sptr)->flags & INMEMORY) { \
397 x86_64_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
401 #define store_reg_to_var_flt(sptr, tempregnum) \
402 if ((sptr)->flags & INMEMORY) { \
404 x86_64_movq_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
408 #define M_COPY(from,to) \
409 d = reg_of_var(rd, to, REG_ITMP1); \
410 if ((from->regoff != to->regoff) || \
411 ((from->flags ^ to->flags) & INMEMORY)) { \
412 if (IS_FLT_DBL_TYPE(from->type)) { \
413 var_to_reg_flt(s1, from, d); \
415 store_reg_to_var_flt(to, d); \
417 var_to_reg_int(s1, from, d); \
419 store_reg_to_var_int(to, d); \
424 /* macros to create code ******************************************************/
426 #define M_MOV(a,b) x86_64_mov_reg_reg(cd, (a), (b))
427 #define M_MOV_IMM(a,b) x86_64_mov_imm_reg(cd, (a), (b))
429 #define M_IMOV_IMM(a,b) x86_64_movl_imm_reg(cd, (a), (b))
431 #define M_ILD(a,b,disp) x86_64_movl_membase_reg(cd, (b), (disp), (a))
432 #define M_LLD(a,b,disp) x86_64_mov_membase_reg(cd, (b), (disp), (a))
433 #define M_DLD(a,b,disp) x86_64_movq_membase_reg(cd, (b), (disp), (a))
435 #define M_IST(a,b,disp) x86_64_movl_reg_membase(cd, (a), (b), (disp))
436 #define M_LST(a,b,disp) x86_64_mov_reg_membase(cd, (a), (b), (disp))
437 #define M_DST(a,b,disp) x86_64_movq_reg_membase(cd, (a), (b), (disp))
439 #define M_LADD(a,b) x86_64_alu_reg_reg(cd, X86_64_ADD, (a), (b))
440 #define M_LADD_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_ADD, (a), (b))
441 #define M_LSUB(a,b) x86_64_alu_reg_reg(cd, X86_64_SUB, (a), (b))
442 #define M_LSUB_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_SUB, (a), (b))
444 #define M_ALD(a,b,c) M_LLD(a,b,c)
445 #define M_AST(a,b,c) M_LST(a,b,c)
446 #define M_AADD(a,b) M_LADD(a,b)
447 #define M_AADD_IMM(a,b) M_LADD_IMM(a,b)
448 #define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b)
450 #define M_LADD_IMM32(a,b) x86_64_alu_imm32_reg(cd, X86_64_ADD, (a), (b))
451 #define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b)
452 #define M_LSUB_IMM32(a,b) x86_64_alu_imm32_reg(cd, X86_64_SUB, (a), (b))
454 #define M_ILEA(a,b,c) x86_64_leal_membase_reg(cd, (a), (b), (c))
455 #define M_LLEA(a,b,c) x86_64_lea_membase_reg(cd, (a), (b), (c))
456 #define M_ALEA(a,b,c) M_LLEA(a,b,c)
458 #define M_AND(a,b) x86_64_alu_reg_reg(cd, X86_64_AND, (a), (b))
459 #define M_XOR(a,b) x86_64_alu_reg_reg(cd, X86_64_XOR, (a), (b))
461 #define M_IAND(a,b) x86_64_alul_reg_reg(cd, X86_64_AND, (a), (b))
462 #define M_IAND_IMM(a,b) x86_64_alul_imm_reg(cd, X86_64_AND, (a), (b))
463 #define M_IXOR(a,b) x86_64_alul_reg_reg(cd, X86_64_XOR, (a), (b))
465 #define M_TEST(a) x86_64_test_reg_reg(cd, (a), (a))
467 #define M_CMP(a,b) x86_64_alu_reg_reg(cd, X86_64_CMP, (a), (b))
468 #define M_CMP_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_CMP, (a), (b))
469 #define M_CMP_MEMBASE(a,b,c) x86_64_alu_membase_reg(cd, X86_64_CMP, (a), (b), (c))
471 #define M_BEQ(disp) x86_64_jcc(cd, X86_64_CC_E, (disp))
472 #define M_BNE(disp) x86_64_jcc(cd, X86_64_CC_NE, (disp))
473 #define M_BLE(disp) x86_64_jcc(cd, X86_64_CC_LE, (disp))
474 #define M_BA(disp) x86_64_jcc(cd, X86_64_CC_A, (disp))
476 #define M_PUSH(a) x86_64_push_reg(cd, (a))
477 #define M_PUSH_IMM(a) x86_64_push_imm(cd, (a))
478 #define M_POP(a) x86_64_pop_reg(cd, (a))
480 #define M_JMP(a) x86_64_jmp_reg(cd, (a))
481 #define M_JMP_IMM(a) x86_64_jmp_imm(cd, (a))
482 #define M_CALL(a) x86_64_call_reg(cd, (a))
483 #define M_CALL_IMM(a) x86_64_call_imm(cd, (a))
484 #define M_RET x86_64_ret(cd)
486 #define M_NOP x86_64_nop(cd)
489 /* function gen_resolvebranch **************************************************
491 backpatches a branch instruction
493 parameters: ip ... pointer to instruction after branch (void*)
494 so ... offset of instruction after branch (s8)
495 to ... offset of branch target (s8)
497 *******************************************************************************/
499 #define gen_resolvebranch(ip,so,to) \
500 *((s4*) ((ip) - 4)) = (s4) ((to) - (so));
502 #endif /* _CODEGEN_H */
506 * These are local overrides for various environment variables in Emacs.
507 * Please do not remove this and leave it at the end of the file, where
508 * Emacs will automagically detect them.
509 * ---------------------------------------------------------------------
512 * indent-tabs-mode: t