1 /* jit/x86_64/codegen.h - code generation macros and definitions for x86_64
3 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
4 R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser,
5 M. Probst, S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck,
6 P. Tomsich, J. Wenninger
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
30 $Id: codegen.h 1451 2004-11-05 14:14:15Z twisti $
38 #include <sys/ucontext.h>
42 /* x86_64 register numbers */
80 /* preallocated registers *****************************************************/
82 /* integer registers */
84 #define REG_RESULT RAX /* to deliver method results */
86 #define REG_ITMP1 RAX /* temporary register */
87 #define REG_ITMP2 R10 /* temporary register and method pointer */
88 #define REG_ITMP3 R11 /* temporary register */
90 #define REG_NULL -1 /* used for reg_of_var where d is not needed */
92 #define REG_ITMP1_XPTR RAX /* exception pointer = temporary register 1 */
93 #define REG_ITMP2_XPC R10 /* exception pc = temporary register 2 */
95 #define REG_SP RSP /* stack pointer */
97 /* floating point registers */
99 #define REG_FRESULT XMM0 /* to deliver floating point method results */
101 #define REG_FTMP1 XMM8 /* temporary floating point register */
102 #define REG_FTMP2 XMM9 /* temporary floating point register */
103 #define REG_FTMP3 XMM10 /* temporary floating point register */
106 #define INT_ARG_CNT 6 /* number of int argument registers */
107 #define INT_SAV_CNT 5 /* number of int callee saved registers */
109 #define FLT_ARG_CNT 4 /* number of flt argument registers */
110 #define FLT_SAV_CNT 0 /* number of flt callee saved registers */
113 /* macros to create code ******************************************************/
115 /* immediate data union */
127 /* opcodes for alu instructions */
151 } X86_64_Shift_Opcode;
157 X86_64_CC_B = 2, X86_64_CC_C = 2, X86_64_CC_NAE = 2,
158 X86_64_CC_BE = 6, X86_64_CC_NA = 6,
159 X86_64_CC_AE = 3, X86_64_CC_NB = 3, X86_64_CC_NC = 3,
160 X86_64_CC_E = 4, X86_64_CC_Z = 4,
161 X86_64_CC_NE = 5, X86_64_CC_NZ = 5,
162 X86_64_CC_A = 7, X86_64_CC_NBE = 7,
163 X86_64_CC_S = 8, X86_64_CC_LZ = 8,
164 X86_64_CC_NS = 9, X86_64_CC_GEZ = 9,
165 X86_64_CC_P = 0x0a, X86_64_CC_PE = 0x0a,
166 X86_64_CC_NP = 0x0b, X86_64_CC_PO = 0x0b,
167 X86_64_CC_L = 0x0c, X86_64_CC_NGE = 0x0c,
168 X86_64_CC_GE = 0x0d, X86_64_CC_NL = 0x0d,
169 X86_64_CC_LE = 0x0e, X86_64_CC_NG = 0x0e,
170 X86_64_CC_G = 0x0f, X86_64_CC_NLE = 0x0f,
175 /* modrm and stuff */
177 #define x86_64_address_byte(mod,reg,rm) \
178 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | ((rm) & 0x07));
181 #define x86_64_emit_reg(reg,rm) \
182 x86_64_address_byte(3,(reg),(rm));
185 #define x86_64_emit_rex(size,reg,index,rm) \
186 if ((size) == 1 || (reg) > 7 || (index) > 7 || (rm) > 7) { \
187 *(cd->mcodeptr++) = (0x40 | (((size) & 0x01) << 3) | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01)); \
191 #define x86_64_emit_mem(r,disp) \
193 x86_64_address_byte(0,(r),5); \
194 x86_64_emit_imm32((disp)); \
198 #define x86_64_emit_membase(basereg,disp,dreg) \
200 if ((basereg) == REG_SP || (basereg) == R12) { \
202 x86_64_address_byte(0,(dreg),REG_SP); \
203 x86_64_address_byte(0,REG_SP,REG_SP); \
204 } else if (x86_64_is_imm8((disp))) { \
205 x86_64_address_byte(1,(dreg),REG_SP); \
206 x86_64_address_byte(0,REG_SP,REG_SP); \
207 x86_64_emit_imm8((disp)); \
209 x86_64_address_byte(2,(dreg),REG_SP); \
210 x86_64_address_byte(0,REG_SP,REG_SP); \
211 x86_64_emit_imm32((disp)); \
215 if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
216 x86_64_address_byte(0,(dreg),(basereg)); \
220 if ((basereg) == RIP) { \
221 x86_64_address_byte(0,(dreg),RBP); \
222 x86_64_emit_imm32((disp)); \
226 if (x86_64_is_imm8((disp))) { \
227 x86_64_address_byte(1,(dreg),(basereg)); \
228 x86_64_emit_imm8((disp)); \
230 x86_64_address_byte(2,(dreg),(basereg)); \
231 x86_64_emit_imm32((disp)); \
236 #define x86_64_emit_memindex(reg,disp,basereg,indexreg,scale) \
238 if ((basereg) == -1) { \
239 x86_64_address_byte(0,(reg),4); \
240 x86_64_address_byte((scale),(indexreg),5); \
241 x86_64_emit_imm32((disp)); \
243 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
244 x86_64_address_byte(0,(reg),4); \
245 x86_64_address_byte((scale),(indexreg),(basereg)); \
247 } else if (x86_64_is_imm8((disp))) { \
248 x86_64_address_byte(1,(reg),4); \
249 x86_64_address_byte((scale),(indexreg),(basereg)); \
250 x86_64_emit_imm8 ((disp)); \
253 x86_64_address_byte(2,(reg),4); \
254 x86_64_address_byte((scale),(indexreg),(basereg)); \
255 x86_64_emit_imm32((disp)); \
260 #define x86_64_is_imm8(imm) \
261 (((long)(imm) >= -128 && (long)(imm) <= 127))
264 #define x86_64_is_imm32(imm) \
265 ((long)(imm) >= (-2147483647-1) && (long)(imm) <= 2147483647)
268 #define x86_64_emit_imm8(imm) \
269 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
272 #define x86_64_emit_imm16(imm) \
274 x86_64_imm_buf imb; \
275 imb.i = (s4) (imm); \
276 *(cd->mcodeptr++) = imb.b[0]; \
277 *(cd->mcodeptr++) = imb.b[1]; \
281 #define x86_64_emit_imm32(imm) \
283 x86_64_imm_buf imb; \
284 imb.i = (s4) (imm); \
285 *(cd->mcodeptr++) = imb.b[0]; \
286 *(cd->mcodeptr++) = imb.b[1]; \
287 *(cd->mcodeptr++) = imb.b[2]; \
288 *(cd->mcodeptr++) = imb.b[3]; \
292 #define x86_64_emit_imm64(imm) \
294 x86_64_imm_buf imb; \
295 imb.l = (s8) (imm); \
296 *(cd->mcodeptr++) = imb.b[0]; \
297 *(cd->mcodeptr++) = imb.b[1]; \
298 *(cd->mcodeptr++) = imb.b[2]; \
299 *(cd->mcodeptr++) = imb.b[3]; \
300 *(cd->mcodeptr++) = imb.b[4]; \
301 *(cd->mcodeptr++) = imb.b[5]; \
302 *(cd->mcodeptr++) = imb.b[6]; \
303 *(cd->mcodeptr++) = imb.b[7]; \
307 /* additional functions and macros to generate code ***************************/
309 #define BlockPtrOfPC(pc) ((basicblock *) iptr->target)
313 #define COUNT_SPILLS count_spills++
319 #define CALCOFFSETBYTES(var, reg, val) \
320 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
321 else if ((s4) (val) != 0) (var) += 1; \
322 else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1;
325 #define CALCIMMEDIATEBYTES(var, val) \
326 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
330 /* gen_nullptr_check(objreg) */
332 #define gen_nullptr_check(objreg) \
334 x86_64_test_reg_reg(cd, (objreg), (objreg)); \
335 x86_64_jcc(cd, X86_64_CC_E, 0); \
336 codegen_addxnullrefs(cd, cd->mcodeptr); \
340 #define gen_bound_check \
342 x86_64_alul_membase_reg(cd, X86_64_CMP, s1, OFFSET(java_arrayheader, size), s2); \
343 x86_64_jcc(cd, X86_64_CC_AE, 0); \
344 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
348 #define gen_div_check(v) \
350 if ((v)->flags & INMEMORY) { \
351 x86_64_alu_imm_membase(cd, X86_64_CMP, 0, REG_SP, src->regoff * 8); \
353 x86_64_test_reg_reg(cd, src->regoff, src->regoff); \
355 x86_64_jcc(cd, X86_64_CC_E, 0); \
356 codegen_addxdivrefs(cd, cd->mcodeptr); \
360 /* MCODECHECK(icnt) */
362 #define MCODECHECK(icnt) \
363 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
364 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
367 generates an integer-move from register a to b.
368 if a and b are the same int-register, no code will be generated.
371 #define M_INTMOVE(reg,dreg) \
372 if ((reg) != (dreg)) { \
373 x86_64_mov_reg_reg(cd, (reg),(dreg)); \
378 generates a floating-point-move from register a to b.
379 if a and b are the same float-register, no code will be generated
382 #define M_FLTMOVE(reg,dreg) \
383 if ((reg) != (dreg)) { \
384 x86_64_movq_reg_reg(cd, (reg),(dreg)); \
389 this function generates code to fetch data from a pseudo-register
390 into a real register.
391 If the pseudo-register has actually been assigned to a real
392 register, no code will be emitted, since following operations
393 can use this register directly.
395 v: pseudoregister to be fetched from
396 tempregnum: temporary register to be used if v is actually spilled to ram
398 return: the register number, where the operand can be found after
399 fetching (this wil be either tempregnum or the register
400 number allready given to v)
403 #define var_to_reg_int(regnr,v,tempnr) \
404 if ((v)->flags & INMEMORY) { \
406 if ((v)->type == TYPE_INT) { \
407 x86_64_movl_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
409 x86_64_mov_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
413 regnr = (v)->regoff; \
418 #define var_to_reg_flt(regnr,v,tempnr) \
419 if ((v)->flags & INMEMORY) { \
421 if ((v)->type == TYPE_FLT) { \
422 x86_64_movlps_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
424 x86_64_movlpd_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
426 /* x86_64_movq_membase_reg(REG_SP, (v)->regoff * 8, tempnr);*/ \
429 regnr = (v)->regoff; \
433 /* store_reg_to_var_xxx:
434 This function generates the code to store the result of an operation
435 back into a spilled pseudo-variable.
436 If the pseudo-variable has not been spilled in the first place, this
437 function will generate nothing.
439 v ............ Pseudovariable
440 tempregnum ... Number of the temporary registers as returned by
444 #define store_reg_to_var_int(sptr, tempregnum) \
445 if ((sptr)->flags & INMEMORY) { \
447 x86_64_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
451 #define store_reg_to_var_flt(sptr, tempregnum) \
452 if ((sptr)->flags & INMEMORY) { \
454 x86_64_movq_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
458 #define M_COPY(from,to) \
459 d = reg_of_var(rd, to, REG_ITMP1); \
460 if ((from->regoff != to->regoff) || \
461 ((from->flags ^ to->flags) & INMEMORY)) { \
462 if (IS_FLT_DBL_TYPE(from->type)) { \
463 var_to_reg_flt(s1, from, d); \
465 store_reg_to_var_flt(to, d); \
467 var_to_reg_int(s1, from, d); \
469 store_reg_to_var_int(to, d); \
474 /* #define ALIGNCODENOP {if((int)((long)mcodeptr&7)){M_NOP;}} */
475 #define ALIGNCODENOP do {} while (0)
478 /* function gen_resolvebranch **************************************************
480 backpatches a branch instruction
482 parameters: ip ... pointer to instruction after branch (void*)
483 so ... offset of instruction after branch (s8)
484 to ... offset of branch target (s8)
486 *******************************************************************************/
488 #define gen_resolvebranch(ip,so,to) \
489 *((s4*) ((ip) - 4)) = (s4) ((to) - (so));
492 /* function prototypes */
494 void thread_restartcriticalsection(ucontext_t *uc);
496 #endif /* _CODEGEN_H */
500 * These are local overrides for various environment variables in Emacs.
501 * Please do not remove this and leave it at the end of the file, where
502 * Emacs will automagically detect them.
503 * ---------------------------------------------------------------------
506 * indent-tabs-mode: t