1 /* jit/x86_64/codegen.h - code generation macros and definitions for x86_64
3 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
4 R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser,
5 M. Probst, S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck,
6 P. Tomsich, J. Wenninger
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
30 $Id: codegen.h 1284 2004-07-07 15:56:17Z twisti $
41 /* x86_64 register numbers */
79 /* preallocated registers *****************************************************/
81 /* integer registers */
83 #define REG_RESULT RAX /* to deliver method results */
85 #define REG_ITMP1 RAX /* temporary register */
86 #define REG_ITMP2 R10 /* temporary register and method pointer */
87 #define REG_ITMP3 R11 /* temporary register */
89 #define REG_NULL -1 /* used for reg_of_var where d is not needed */
91 #define REG_ITMP1_XPTR RAX /* exception pointer = temporary register 1 */
92 #define REG_ITMP2_XPC R10 /* exception pc = temporary register 2 */
94 #define REG_SP RSP /* stack pointer */
96 /* floating point registers */
98 #define REG_FRESULT XMM0 /* to deliver floating point method results */
100 #define REG_FTMP1 XMM8 /* temporary floating point register */
101 #define REG_FTMP2 XMM9 /* temporary floating point register */
102 #define REG_FTMP3 XMM10 /* temporary floating point register */
105 #define INT_ARG_CNT 6 /* number of int argument registers */
106 #define INT_SAV_CNT 5 /* number of int callee saved registers */
108 #define FLT_ARG_CNT 4 /* number of flt argument registers */
109 #define FLT_SAV_CNT 0 /* number of flt callee saved registers */
112 /* macros to create code ******************************************************/
114 /* immediate data union */
126 /* opcodes for alu instructions */
150 } X86_64_Shift_Opcode;
156 X86_64_CC_B = 2, X86_64_CC_C = 2, X86_64_CC_NAE = 2,
157 X86_64_CC_BE = 6, X86_64_CC_NA = 6,
158 X86_64_CC_AE = 3, X86_64_CC_NB = 3, X86_64_CC_NC = 3,
159 X86_64_CC_E = 4, X86_64_CC_Z = 4,
160 X86_64_CC_NE = 5, X86_64_CC_NZ = 5,
161 X86_64_CC_A = 7, X86_64_CC_NBE = 7,
162 X86_64_CC_S = 8, X86_64_CC_LZ = 8,
163 X86_64_CC_NS = 9, X86_64_CC_GEZ = 9,
164 X86_64_CC_P = 0x0a, X86_64_CC_PE = 0x0a,
165 X86_64_CC_NP = 0x0b, X86_64_CC_PO = 0x0b,
166 X86_64_CC_L = 0x0c, X86_64_CC_NGE = 0x0c,
167 X86_64_CC_GE = 0x0d, X86_64_CC_NL = 0x0d,
168 X86_64_CC_LE = 0x0e, X86_64_CC_NG = 0x0e,
169 X86_64_CC_G = 0x0f, X86_64_CC_NLE = 0x0f,
174 /* modrm and stuff */
176 #define x86_64_address_byte(mod,reg,rm) \
177 *(mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | ((rm) & 0x07));
180 #define x86_64_emit_reg(reg,rm) \
181 x86_64_address_byte(3,(reg),(rm));
184 #define x86_64_emit_rex(size,reg,index,rm) \
185 if ((size) == 1 || (reg) > 7 || (index) > 7 || (rm) > 7) { \
186 *(mcodeptr++) = (0x40 | (((size) & 0x01) << 3) | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01)); \
190 #define x86_64_emit_mem(r,disp) \
192 x86_64_address_byte(0,(r),5); \
193 x86_64_emit_imm32((disp)); \
197 #define x86_64_emit_membase(basereg,disp,dreg) \
199 if ((basereg) == REG_SP || (basereg) == R12) { \
201 x86_64_address_byte(0,(dreg),REG_SP); \
202 x86_64_address_byte(0,REG_SP,REG_SP); \
203 } else if (x86_64_is_imm8((disp))) { \
204 x86_64_address_byte(1,(dreg),REG_SP); \
205 x86_64_address_byte(0,REG_SP,REG_SP); \
206 x86_64_emit_imm8((disp)); \
208 x86_64_address_byte(2,(dreg),REG_SP); \
209 x86_64_address_byte(0,REG_SP,REG_SP); \
210 x86_64_emit_imm32((disp)); \
214 if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
215 x86_64_address_byte(0,(dreg),(basereg)); \
219 if ((basereg) == RIP) { \
220 x86_64_address_byte(0,(dreg),RBP); \
221 x86_64_emit_imm32((disp)); \
225 if (x86_64_is_imm8((disp))) { \
226 x86_64_address_byte(1,(dreg),(basereg)); \
227 x86_64_emit_imm8((disp)); \
229 x86_64_address_byte(2,(dreg),(basereg)); \
230 x86_64_emit_imm32((disp)); \
235 #define x86_64_emit_memindex(reg,disp,basereg,indexreg,scale) \
237 if ((basereg) == -1) { \
238 x86_64_address_byte(0,(reg),4); \
239 x86_64_address_byte((scale),(indexreg),5); \
240 x86_64_emit_imm32((disp)); \
242 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
243 x86_64_address_byte(0,(reg),4); \
244 x86_64_address_byte((scale),(indexreg),(basereg)); \
246 } else if (x86_64_is_imm8((disp))) { \
247 x86_64_address_byte(1,(reg),4); \
248 x86_64_address_byte((scale),(indexreg),(basereg)); \
249 x86_64_emit_imm8 ((disp)); \
252 x86_64_address_byte(2,(reg),4); \
253 x86_64_address_byte((scale),(indexreg),(basereg)); \
254 x86_64_emit_imm32((disp)); \
259 #define x86_64_is_imm8(imm) \
260 (((long)(imm) >= -128 && (long)(imm) <= 127))
263 #define x86_64_is_imm32(imm) \
264 ((long)(imm) >= (-2147483647-1) && (long)(imm) <= 2147483647)
267 #define x86_64_emit_imm8(imm) \
268 *(mcodeptr++) = (u1) ((imm) & 0xff);
271 #define x86_64_emit_imm16(imm) \
273 x86_64_imm_buf imb; \
274 imb.i = (s4) (imm); \
275 *(mcodeptr++) = imb.b[0]; \
276 *(mcodeptr++) = imb.b[1]; \
280 #define x86_64_emit_imm32(imm) \
282 x86_64_imm_buf imb; \
283 imb.i = (s4) (imm); \
284 *(mcodeptr++) = imb.b[0]; \
285 *(mcodeptr++) = imb.b[1]; \
286 *(mcodeptr++) = imb.b[2]; \
287 *(mcodeptr++) = imb.b[3]; \
291 #define x86_64_emit_imm64(imm) \
293 x86_64_imm_buf imb; \
294 imb.l = (s8) (imm); \
295 *(mcodeptr++) = imb.b[0]; \
296 *(mcodeptr++) = imb.b[1]; \
297 *(mcodeptr++) = imb.b[2]; \
298 *(mcodeptr++) = imb.b[3]; \
299 *(mcodeptr++) = imb.b[4]; \
300 *(mcodeptr++) = imb.b[5]; \
301 *(mcodeptr++) = imb.b[6]; \
302 *(mcodeptr++) = imb.b[7]; \
306 /* additional functions and macros to generate code ***************************/
308 #define BlockPtrOfPC(pc) ((basicblock *) iptr->target)
312 #define COUNT_SPILLS count_spills++
318 #define CALCOFFSETBYTES(var, reg, val) \
319 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
320 else if ((s4) (val) != 0) (var) += 1; \
321 else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1;
324 #define CALCIMMEDIATEBYTES(var, val) \
325 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
329 /* gen_nullptr_check(objreg) */
331 #define gen_nullptr_check(objreg) \
333 x86_64_test_reg_reg((objreg), (objreg)); \
334 x86_64_jcc(X86_64_CC_E, 0); \
335 codegen_addxnullrefs(mcodeptr); \
339 #define gen_bound_check \
341 x86_64_alul_membase_reg(X86_64_CMP, s1, OFFSET(java_arrayheader, size), s2); \
342 x86_64_jcc(X86_64_CC_AE, 0); \
343 codegen_addxboundrefs(mcodeptr, s2); \
347 #define gen_div_check(v) \
349 if ((v)->flags & INMEMORY) { \
350 x86_64_alu_imm_membase(X86_64_CMP, 0, REG_SP, src->regoff * 8); \
352 x86_64_test_reg_reg(src->regoff, src->regoff); \
354 x86_64_jcc(X86_64_CC_E, 0); \
355 codegen_addxdivrefs(mcodeptr); \
359 /* MCODECHECK(icnt) */
361 #define MCODECHECK(icnt) \
362 if ((mcodeptr + (icnt)) > (u1 *) mcodeend) \
363 mcodeptr = (u1 *) codegen_increase((u1 *) mcodeptr)
366 generates an integer-move from register a to b.
367 if a and b are the same int-register, no code will be generated.
370 #define M_INTMOVE(reg,dreg) \
371 if ((reg) != (dreg)) { \
372 x86_64_mov_reg_reg((reg),(dreg)); \
377 generates a floating-point-move from register a to b.
378 if a and b are the same float-register, no code will be generated
381 #define M_FLTMOVE(reg,dreg) \
382 if ((reg) != (dreg)) { \
383 x86_64_movq_reg_reg((reg),(dreg)); \
388 this function generates code to fetch data from a pseudo-register
389 into a real register.
390 If the pseudo-register has actually been assigned to a real
391 register, no code will be emitted, since following operations
392 can use this register directly.
394 v: pseudoregister to be fetched from
395 tempregnum: temporary register to be used if v is actually spilled to ram
397 return: the register number, where the operand can be found after
398 fetching (this wil be either tempregnum or the register
399 number allready given to v)
402 #define var_to_reg_int(regnr,v,tempnr) \
403 if ((v)->flags & INMEMORY) { \
405 if ((v)->type == TYPE_INT) { \
406 x86_64_movl_membase_reg(REG_SP, (v)->regoff * 8, tempnr); \
408 x86_64_mov_membase_reg(REG_SP, (v)->regoff * 8, tempnr); \
412 regnr = (v)->regoff; \
417 #define var_to_reg_flt(regnr,v,tempnr) \
418 if ((v)->flags & INMEMORY) { \
420 if ((v)->type == TYPE_FLT) { \
421 x86_64_movlps_membase_reg(REG_SP, (v)->regoff * 8, tempnr); \
423 x86_64_movlpd_membase_reg(REG_SP, (v)->regoff * 8, tempnr); \
425 /* x86_64_movq_membase_reg(REG_SP, (v)->regoff * 8, tempnr);*/ \
428 regnr = (v)->regoff; \
432 /* store_reg_to_var_xxx:
433 This function generates the code to store the result of an operation
434 back into a spilled pseudo-variable.
435 If the pseudo-variable has not been spilled in the first place, this
436 function will generate nothing.
438 v ............ Pseudovariable
439 tempregnum ... Number of the temporary registers as returned by
443 #define store_reg_to_var_int(sptr, tempregnum) \
444 if ((sptr)->flags & INMEMORY) { \
446 x86_64_mov_reg_membase(tempregnum, REG_SP, (sptr)->regoff * 8); \
450 #define store_reg_to_var_flt(sptr, tempregnum) \
451 if ((sptr)->flags & INMEMORY) { \
453 x86_64_movq_reg_membase(tempregnum, REG_SP, (sptr)->regoff * 8); \
457 /* function gen_resolvebranch **************************************************
459 backpatches a branch instruction
461 parameters: ip ... pointer to instruction after branch (void*)
462 so ... offset of instruction after branch (s8)
463 to ... offset of branch target (s8)
465 *******************************************************************************/
467 #define gen_resolvebranch(ip,so,to) \
468 *((s4*) ((ip) - 4)) = (s4) ((to) - (so));
471 /* function prototypes */
474 void init_exceptions();
476 void codegen_close();
477 void dseg_display(s4 *s4ptr);
479 void codegen_addreference(basicblock *target, void *branchptr);
481 #endif /* _CODEGEN_H */
485 * These are local overrides for various environment variables in Emacs.
486 * Please do not remove this and leave it at the end of the file, where
487 * Emacs will automagically detect them.
488 * ---------------------------------------------------------------------
491 * indent-tabs-mode: t