1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8123 2007-06-20 23:50:55Z michi $
38 #include "vm/jit/s390/codegen.h"
39 #include "vm/jit/s390/emit.h"
41 #if defined(ENABLE_THREADS)
42 # include "threads/native/lock.h"
45 #include "vm/builtin.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/replace.h"
52 #include "vm/jit/abi.h"
53 #include "vm/global.h"
54 #include "mm/memory.h"
55 #include "vm/exceptions.h"
59 /* emit_load *******************************************************************
61 Emits a possible load of an operand.
63 *******************************************************************************/
65 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
71 /* get required compiler data */
75 if (IS_INMEMORY(src->flags)) {
78 disp = src->vv.regoff;
80 if (IS_FLT_DBL_TYPE(src->type)) {
81 if (IS_2_WORD_TYPE(src->type))
82 M_DLD(tempreg, REG_SP, disp);
84 M_FLD(tempreg, REG_SP, disp);
87 if (IS_2_WORD_TYPE(src->type))
88 M_LLD(tempreg, REG_SP, disp);
90 M_ILD(tempreg, REG_SP, disp);
102 /* emit_store ******************************************************************
104 This function generates the code to store the result of an
105 operation back into a spilled pseudo-variable. If the
106 pseudo-variable has not been spilled in the first place, this
107 function will generate nothing.
109 *******************************************************************************/
111 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
115 /* get required compiler data */
119 if (IS_INMEMORY(dst->flags)) {
122 if (IS_FLT_DBL_TYPE(dst->type)) {
123 if (IS_2_WORD_TYPE(dst->type))
124 M_DST(d, REG_SP, dst->vv.regoff);
126 M_FST(d, REG_SP, dst->vv.regoff);
129 if (IS_2_WORD_TYPE(dst->type))
130 M_LST(d, REG_SP, dst->vv.regoff);
132 M_IST(d, REG_SP, dst->vv.regoff);
138 /* emit_copy *******************************************************************
140 Generates a register/memory to register/memory copy.
142 *******************************************************************************/
144 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr)
151 /* get required compiler data */
155 /* get source and destination variables */
157 src = VAROP(iptr->s1);
158 dst = VAROP(iptr->dst);
160 if ((src->vv.regoff != dst->vv.regoff) ||
161 ((src->flags ^ dst->flags) & INMEMORY)) {
163 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
164 /* emit nothing, as the value won't be used anyway */
168 /* If one of the variables resides in memory, we can eliminate
169 the register move from/to the temporary register with the
170 order of getting the destination register and the load. */
172 if (IS_INMEMORY(src->flags)) {
173 if (IS_FLT_DBL_TYPE(dst->type)) {
174 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
176 if (IS_2_WORD_TYPE(dst->type)) {
177 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
179 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
182 s1 = emit_load(jd, iptr, src, d);
185 if (IS_FLT_DBL_TYPE(src->type)) {
186 s1 = emit_load(jd, iptr, src, REG_FTMP1);
188 if (IS_2_WORD_TYPE(src->type)) {
189 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
191 s1 = emit_load(jd, iptr, src, REG_ITMP1);
194 d = codegen_reg_of_var(iptr->opc, dst, s1);
198 if (IS_FLT_DBL_TYPE(src->type)) {
201 if (IS_2_WORD_TYPE(src->type)) {
209 emit_store(jd, iptr, dst, d);
214 /* emit_patcher_stubs **********************************************************
216 Generates the code for the patcher stubs.
218 *******************************************************************************/
220 __PORTED__ void emit_patcher_stubs(jitdata *jd)
232 /* get required compiler data */
236 /* generate code patching stub call code */
240 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
241 /* check code segment size */
245 /* Get machine code which is patched back in later. The
246 call is 1 instruction word long. */
248 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
250 mcode = *((u4 *) tmpmcodeptr);
252 /* Patch in the call to call the following code (done at
255 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
256 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
258 disp = (savedmcodeptr) - (tmpmcodeptr);
260 if (! N_VALID_BRANCH(disp)) {
261 /* Displacement overflow */
263 /* If LONGBRANCHES is not set, the flag and the error flag */
265 if (! CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
266 cd->flags |= (CODEGENDATA_FLAG_ERROR |
267 CODEGENDATA_FLAG_LONGBRANCHES);
270 /* If error flag is set, do nothing. The method has to be recompiled. */
272 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
277 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
279 /* Generating long branches */
281 disp = dseg_add_s4(cd, savedmcodeptr - cd->mcodebase - N_PV_OFFSET);
283 M_ILD_DSEG(REG_ITMP3, disp);
284 M_AADD(REG_PV, REG_ITMP3);
286 /* Do the branch at the end of NOP sequence.
287 * This way the patch position is at a *fixed* offset
288 * (PATCHER_LONGBRANCHES_NOPS_SKIP) of the return address.
291 cd->mcodeptr = tmpmcodeptr + PATCHER_LONGBRANCHES_NOPS_SKIP - SZ_BASR;
292 M_JMP(REG_ITMP3, REG_ITMP3);
295 /* Generating short branches */
297 M_BSR(REG_ITMP3, disp);
300 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
302 /* create stack frame */
304 M_ASUB_IMM(6 * 4, REG_SP);
306 /* move return address onto stack */
308 M_AST(REG_ITMP3, REG_SP, 5 * 4);
310 /* move pointer to java_objectheader onto stack */
312 #if defined(ENABLE_THREADS)
313 /* create a virtual java_objectheader */
315 (void) dseg_add_unique_address(cd, NULL); /* flcword */
316 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
317 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
319 M_LDA_DSEG(REG_ITMP3, disp);
320 M_AST(REG_ITMP3, REG_SP, 4 * 4);
325 /* move machine code onto stack */
327 disp = dseg_add_s4(cd, mcode);
328 M_ILD_DSEG(REG_ITMP3, disp);
329 M_IST(REG_ITMP3, REG_SP, 3 * 4);
331 /* move class/method/field reference onto stack */
333 disp = dseg_add_address(cd, pref->ref);
334 M_ALD_DSEG(REG_ITMP3, disp);
335 M_AST(REG_ITMP3, REG_SP, 2 * 4);
337 /* move data segment displacement onto stack */
339 disp = dseg_add_s4(cd, pref->disp);
340 M_ILD_DSEG(REG_ITMP3, disp);
341 M_IST(REG_ITMP3, REG_SP, 1 * 4);
343 /* move patcher function pointer onto stack */
345 disp = dseg_add_functionptr(cd, pref->patcher);
346 M_ALD_DSEG(REG_ITMP3, disp);
347 M_AST(REG_ITMP3, REG_SP, 0 * 4);
349 if (targetdisp == 0) {
350 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
352 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
353 M_ALD_DSEG(REG_ITMP3, disp);
354 M_JMP(RN, REG_ITMP3);
357 disp = ((cd->mcodebase) + targetdisp) -
360 emit_branch(cd, disp, BRANCH_UNCONDITIONAL, RN, 0);
366 /* emit_replacement_stubs ******************************************************
368 Generates the code for the replacement stubs.
370 *******************************************************************************/
372 void emit_replacement_stubs(jitdata *jd)
381 /* get required compiler data */
386 rplp = code->rplpoints;
388 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
389 /* check code segment size */
393 /* note start of stub code */
395 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
397 /* make machine code for patching */
399 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
401 rplp->mcode = 0xe9 | ((u8) disp << 8);
403 /* push address of `rplpoint` struct */
405 M_MOV_IMM(rplp, REG_ITMP3);
408 /* jump to replacement function */
410 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
417 /* emit_verbosecall_enter ******************************************************
419 Generates the code for the call trace.
421 *******************************************************************************/
424 void emit_verbosecall_enter(jitdata *jd)
431 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
433 /* get required compiler data */
440 /* mark trace code */
445 (6 * 8) + /* s8 on stack parameters x 6 */
446 (1 * 4) + /* methodinfo on stack parameter */
451 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
453 /* save argument registers */
455 off = (6 * 8) + (1 * 4);
457 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
458 M_IST(abi_registers_integer_argument[i], REG_SP, off);
460 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
461 M_DST(abi_registers_float_argument[i], REG_SP, off);
463 /* save temporary registers for leaf methods */
465 if (jd->isleafmethod) {
466 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
467 M_LST(abi_registers_integer_temporary[i], REG_SP, off);
469 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
470 M_DST(abi_registers_float_temporary[i], REG_SP, off);
473 /* Load arguments to new locations */
475 /* First move all arguments to stack
480 * (s8) a1 \ Auxilliary stack frame
485 M_ASUB_IMM(2 * 8, REG_SP);
487 /* offset to where first integer arg is saved on stack */
488 off = (2 * 8) + (6 * 8) + (1 * 4);
489 /* offset to where first float arg is saved on stack */
490 foff = off + (INT_ARG_CNT * 8);
491 /* offset to where first argument is passed on stack */
492 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 4);
493 /* offset to destination on stack */
496 iargctr = fargctr = 0;
498 ICONST(REG_ITMP1, 0);
500 for (i = 0; i < md->paramcount && i < 8; i++) {
501 t = md->paramtypes[i].type;
503 M_IST(REG_ITMP1, REG_SP, doff);
504 M_IST(REG_ITMP1, REG_SP, doff + 4);
506 if (IS_FLT_DBL_TYPE(t)) {
507 if (fargctr < 2) { /* passed in register */
508 N_STD(abi_registers_float_argument[fargctr], doff, RN, REG_SP);
510 } else { /* passed on stack */
511 if (IS_2_WORD_TYPE(t)) {
512 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
515 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
520 if (IS_2_WORD_TYPE(t)) {
521 if (iargctr < 4) { /* passed in 2 registers */
522 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
524 } else { /* passed on stack */
525 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
529 if (iargctr < 5) { /* passed in register */
530 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
532 } else { /* passed on stack */
533 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
542 /* Now move a0 and a1 to registers
552 N_LM(REG_A0, REG_A1, 0, REG_SP);
553 N_LM(REG_A2, REG_A3, 8, REG_SP);
555 M_AADD_IMM(2 * 8, REG_SP);
557 /* Finally load methodinfo argument */
559 disp = dseg_add_address(cd, m);
560 M_ALD_DSEG(REG_ITMP2, disp);
561 M_AST(REG_ITMP2, REG_SP, 6 * 8);
563 /* Call builtin_verbosecall_enter */
565 disp = dseg_add_address(cd, builtin_verbosecall_enter);
566 M_ALD_DSEG(REG_ITMP2, disp);
567 M_ASUB_IMM(96, REG_SP);
569 M_AADD_IMM(96, REG_SP);
571 /* restore argument registers */
573 off = (6 * 8) + (1 * 4);
575 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
576 M_ILD(abi_registers_integer_argument[i], REG_SP, off);
578 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
579 M_DLD(abi_registers_float_argument[i], REG_SP, off);
581 /* restore temporary registers for leaf methods */
583 if (jd->isleafmethod) {
584 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
585 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
587 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
588 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
591 /* remove stackframe */
593 M_AADD_IMM(stackframesize, REG_SP);
595 /* mark trace code */
599 #endif /* !defined(NDEBUG) */
602 /* emit_verbosecall_exit *******************************************************
604 Generates the code for the call trace.
606 *******************************************************************************/
609 void emit_verbosecall_exit(jitdata *jd)
616 /* get required compiler data */
622 /* mark trace code */
626 M_ASUB_IMM(2 * 8, REG_SP);
628 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
629 M_DST(REG_FRESULT, REG_SP, 1 * 8);
631 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
632 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
634 M_INTMOVE(REG_RESULT, REG_A1);
638 disp = dseg_add_address(cd, m);
639 M_ALD_DSEG(REG_A2, disp);
641 /* REG_FRESULT is REG_FA0, so no need to move */
642 M_FLTMOVE(REG_FRESULT, REG_FA1);
644 disp = dseg_add_address(cd, builtin_verbosecall_exit);
645 M_ALD_DSEG(REG_ITMP1, disp);
646 M_ASUB_IMM(96, REG_SP);
648 M_AADD_IMM(96, REG_SP);
650 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
651 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
653 M_AADD_IMM(2 * 8, REG_SP);
655 /* mark trace code */
659 #endif /* !defined(NDEBUG) */
662 /* emit_load_high **************************************************************
664 Emits a possible load of the high 32-bits of an operand.
666 *******************************************************************************/
668 __PORTED__ s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
674 assert(src->type == TYPE_LNG);
676 /* get required compiler data */
680 if (IS_INMEMORY(src->flags)) {
683 disp = src->vv.regoff;
685 M_ILD(tempreg, REG_SP, disp);
690 reg = GET_HIGH_REG(src->vv.regoff);
695 /* emit_load_low ***************************************************************
697 Emits a possible load of the low 32-bits of an operand.
699 *******************************************************************************/
701 __PORTED__ s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
707 assert(src->type == TYPE_LNG);
709 /* get required compiler data */
713 if (IS_INMEMORY(src->flags)) {
716 disp = src->vv.regoff;
718 M_ILD(tempreg, REG_SP, disp + 4);
723 reg = GET_LOW_REG(src->vv.regoff);
728 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
729 codegendata *cd = jd->cd;
730 s4 reg = emit_load_s1(jd, iptr, tempreg);
739 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
740 codegendata *cd = jd->cd;
741 s4 reg = emit_load_s2(jd, iptr, tempreg);
743 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
744 M_FMOV(reg, tempreg);
754 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
755 codegendata *cd = jd->cd;
756 s4 reg = emit_load_s1(jd, iptr, tempreg);
758 if (IS_FLT_DBL_TYPE(VAROP(iptr->s1)->type)) {
759 M_FMOV(reg, tempreg);
769 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
770 codegendata *cd = jd->cd;
771 s4 reg = emit_load_s2(jd, iptr, tempreg);
773 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
774 M_FMOV(reg, tempreg);
784 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
795 * (r12, r13) Illegal, because r13 is PV
796 * (r14, r15) Illegal, because r15 is SP
800 dst = VAROP(iptr->dst);
802 if (IS_INMEMORY(dst->flags)) {
803 if (! IS_REG_ITMP(ltmpreg)) {
804 M_INTMOVE(ltmpreg, breg);
806 if (! IS_REG_ITMP(htmpreg)) {
807 M_INTMOVE(htmpreg, breg);
809 return PACK_REGS(ltmpreg, htmpreg);
811 hr = GET_HIGH_REG(dst->vv.regoff);
812 lr = GET_LOW_REG(dst->vv.regoff);
813 if (((hr % 2) == 0) && lr == (hr + 1)) {
814 /* the result is already in a even-odd pair */
815 return dst->vv.regoff;
816 } else if (((hr % 2) == 0) && (hr < R12)) {
817 /* the high register is at a even position */
818 M_INTMOVE(hr + 1, breg);
819 return PACK_REGS(hr + 1, hr);
820 } else if (((lr % 2) == 1) && (lr < R12)) {
821 /* the low register is at a odd position */
822 M_INTMOVE(lr - 1, breg);
823 return PACK_REGS(lr, lr - 1);
825 /* no way to create an even-odd pair by 1 copy operation,
826 * Use the temporary register pair.
828 if (! IS_REG_ITMP(ltmpreg)) {
829 M_INTMOVE(ltmpreg, breg);
831 if (! IS_REG_ITMP(htmpreg)) {
832 M_INTMOVE(htmpreg, breg);
834 return PACK_REGS(ltmpreg, htmpreg);
839 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
845 dst = VAROP(iptr->dst);
847 if (IS_INMEMORY(dst->flags)) {
848 if (! IS_REG_ITMP(ltmpreg)) {
849 M_INTMOVE(breg, ltmpreg);
851 if (! IS_REG_ITMP(htmpreg)) {
852 M_INTMOVE(breg, htmpreg);
855 hr = GET_HIGH_REG(dst->vv.regoff);
856 lr = GET_LOW_REG(dst->vv.regoff);
857 if (((hr % 2) == 0) && lr == (hr + 1)) {
859 } else if (((hr % 2) == 0) && (hr < R12)) {
860 M_INTMOVE(breg, hr + 1);
861 } else if (((lr % 2) == 1) && (lr < R12)) {
862 M_INTMOVE(breg, lr - 1);
864 if (! IS_REG_ITMP(ltmpreg)) {
865 M_INTMOVE(breg, ltmpreg);
867 if (! IS_REG_ITMP(htmpreg)) {
868 M_INTMOVE(breg, htmpreg);
874 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
878 dst = VAROP(iptr->dst);
879 if (! IS_INMEMORY(dst->flags)) {
880 if (dst->vv.regoff != dtmpreg) {
881 if (IS_FLT_DBL_TYPE(dst->type)) {
882 M_FLTMOVE(dtmpreg, dst->vv.regoff);
883 } else if (IS_2_WORD_TYPE(dst->type)) {
884 M_LNGMOVE(dtmpreg, dst->vv.regoff);
886 M_INTMOVE(dtmpreg, dst->vv.regoff);
892 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
894 s4 branchdisp = disp;
898 if (N_VALID_BRANCH(branchdisp)) {
900 /* valid displacement */
921 case BRANCH_UNCONDITIONAL:
925 vm_abort("emit_branch: unknown condition %d", condition);
929 /* If LONGBRANCHES is not set, the flag and the error flag */
931 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
932 cd->flags |= (CODEGENDATA_FLAG_ERROR |
933 CODEGENDATA_FLAG_LONGBRANCHES);
936 /* If error flag is set, do nothing. The method has to be recompiled. */
938 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
942 /* Patch the displacement to branch over the actual branch manually
943 * to not get yet more nops.
946 branchmpc = cd->mcodeptr - cd->mcodebase;
968 case BRANCH_UNCONDITIONAL:
969 /* fall through, no displacement to patch */
973 vm_abort("emit_branch: unknown condition %d", condition);
976 /* The actual long branch */
978 disp = dseg_add_s4(cd, branchmpc + disp - N_PV_OFFSET);
979 M_ILD_DSEG(REG_ITMP3, disp);
980 M_AADD(REG_PV, REG_ITMP3);
981 M_JMP(RN, REG_ITMP3);
983 /* Patch back the displacement */
986 *(u4 *)ref |= (u4)((cd->mcodeptr - ref) / 2);
991 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
992 if (INSTRUCTION_MUST_CHECK(iptr)) {
994 M_BNE(SZ_BRC + SZ_ILL);
995 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
999 /* emit_arrayindexoutofbounds_check ********************************************
1001 Emit a ArrayIndexOutOfBoundsException check.
1003 *******************************************************************************/
1005 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
1007 if (INSTRUCTION_MUST_CHECK(iptr)) {
1009 * Do unsigned comparison to catch negative indexes.
1011 N_CL(s2, OFFSET(java_arrayheader, size), RN, s1);
1012 M_BLT(SZ_BRC + SZ_ILL);
1013 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
1017 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
1018 if (INSTRUCTION_MUST_CHECK(iptr)) {
1022 switch (condition) {
1024 M_BGT(SZ_BRC + SZ_ILL);
1027 M_BNE(SZ_BRC + SZ_ILL);
1030 M_BLE(SZ_BRC + SZ_ILL);
1033 vm_abort("emit_classcast_check: unknown condition %d", condition);
1035 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
1039 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
1040 if (INSTRUCTION_MUST_CHECK(iptr)) {
1042 M_BNE(SZ_BRC + SZ_ILL);
1043 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
1047 void emit_exception_check(codegendata *cd, instruction *iptr) {
1048 if (INSTRUCTION_MUST_CHECK(iptr)) {
1050 M_BNE(SZ_BRC + SZ_ILL);
1051 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
1055 void emit_restore_pv(codegendata *cd) {
1056 s4 offset, offset_imm;
1060 disp = (s4) (cd->mcodeptr - cd->mcodebase);
1061 M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
1064 /* If the offset from the method start does not fit into an immediate
1065 * value, we can't put it into the data segment!
1068 /* Displacement from start of method to here */
1070 offset = (s4) (cd->mcodeptr - cd->mcodebase);
1071 offset_imm = -offset - SZ_BASR + N_PV_OFFSET;
1073 if (N_VALID_IMM(offset_imm)) {
1074 /* Get program counter */
1076 /* Substract displacement */
1077 M_AADD_IMM(offset_imm, REG_PV);
1079 /* Save program counter and jump over displacement in instruction flow */
1080 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
1081 /* Place displacement here */
1082 /* REG_PV points now exactly to this position */
1083 N_LONG(-offset - SZ_BRAS + N_PV_OFFSET);
1084 /* Substract *(REG_PV) from REG_PV */
1085 N_A(REG_PV, 0, RN, REG_PV);
1090 * These are local overrides for various environment variables in Emacs.
1091 * Please do not remove this and leave it at the end of the file, where
1092 * Emacs will automagically detect them.
1093 * ---------------------------------------------------------------------
1096 * indent-tabs-mode: t