1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8240 2007-07-29 20:36:47Z pm $
38 #include "vm/jit/s390/codegen.h"
39 #include "vm/jit/s390/emit.h"
41 #if defined(ENABLE_THREADS)
42 # include "threads/native/lock.h"
45 #include "vm/builtin.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/replace.h"
52 #include "vm/jit/abi.h"
53 #include "vm/global.h"
54 #include "mm/memory.h"
55 #include "vm/exceptions.h"
59 /* emit_load *******************************************************************
61 Emits a possible load of an operand.
63 *******************************************************************************/
65 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
71 /* get required compiler data */
75 if (IS_INMEMORY(src->flags)) {
78 disp = src->vv.regoff;
80 if (IS_FLT_DBL_TYPE(src->type)) {
81 if (IS_2_WORD_TYPE(src->type))
82 M_DLD(tempreg, REG_SP, disp);
84 M_FLD(tempreg, REG_SP, disp);
87 if (IS_2_WORD_TYPE(src->type))
88 M_LLD(tempreg, REG_SP, disp);
90 M_ILD(tempreg, REG_SP, disp);
102 /* emit_store ******************************************************************
104 This function generates the code to store the result of an
105 operation back into a spilled pseudo-variable. If the
106 pseudo-variable has not been spilled in the first place, this
107 function will generate nothing.
109 *******************************************************************************/
111 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
115 /* get required compiler data */
119 if (IS_INMEMORY(dst->flags)) {
122 if (IS_FLT_DBL_TYPE(dst->type)) {
123 if (IS_2_WORD_TYPE(dst->type))
124 M_DST(d, REG_SP, dst->vv.regoff);
126 M_FST(d, REG_SP, dst->vv.regoff);
129 if (IS_2_WORD_TYPE(dst->type))
130 M_LST(d, REG_SP, dst->vv.regoff);
132 M_IST(d, REG_SP, dst->vv.regoff);
138 /* emit_copy *******************************************************************
140 Generates a register/memory to register/memory copy.
142 *******************************************************************************/
144 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr)
151 /* get required compiler data */
155 /* get source and destination variables */
157 src = VAROP(iptr->s1);
158 dst = VAROP(iptr->dst);
160 if ((src->vv.regoff != dst->vv.regoff) ||
161 ((src->flags ^ dst->flags) & INMEMORY)) {
163 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
164 /* emit nothing, as the value won't be used anyway */
168 /* If one of the variables resides in memory, we can eliminate
169 the register move from/to the temporary register with the
170 order of getting the destination register and the load. */
172 if (IS_INMEMORY(src->flags)) {
173 if (IS_FLT_DBL_TYPE(dst->type)) {
174 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
176 if (IS_2_WORD_TYPE(dst->type)) {
177 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
179 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
182 s1 = emit_load(jd, iptr, src, d);
185 if (IS_FLT_DBL_TYPE(src->type)) {
186 s1 = emit_load(jd, iptr, src, REG_FTMP1);
188 if (IS_2_WORD_TYPE(src->type)) {
189 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
191 s1 = emit_load(jd, iptr, src, REG_ITMP1);
194 d = codegen_reg_of_var(iptr->opc, dst, s1);
198 if (IS_FLT_DBL_TYPE(src->type)) {
201 if (IS_2_WORD_TYPE(src->type)) {
209 emit_store(jd, iptr, dst, d);
214 /* emit_patcher_stubs **********************************************************
216 Generates the code for the patcher stubs.
218 *******************************************************************************/
220 __PORTED__ void emit_patcher_stubs(jitdata *jd)
232 /* get required compiler data */
236 /* generate code patching stub call code */
240 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
241 /* check code segment size */
245 /* Get machine code which is patched back in later. The
246 call is 1 instruction word long. */
248 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
250 mcode = *((u4 *) tmpmcodeptr);
252 /* Patch in the call to call the following code (done at
255 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
256 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
258 disp = (savedmcodeptr) - (tmpmcodeptr);
260 if (! N_VALID_BRANCH(disp)) {
261 /* Displacement overflow */
263 /* If LONGBRANCHES is not set, the flag and the error flag */
265 if (! CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
266 cd->flags |= (CODEGENDATA_FLAG_ERROR |
267 CODEGENDATA_FLAG_LONGBRANCHES);
270 /* If error flag is set, do nothing. The method has to be recompiled. */
272 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
277 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
279 /* Generating long branches */
281 disp = dseg_add_s4(cd, savedmcodeptr - cd->mcodebase - N_PV_OFFSET);
283 M_ILD_DSEG(REG_ITMP3, disp);
284 M_AADD(REG_PV, REG_ITMP3);
286 /* Do the branch at the end of NOP sequence.
287 * This way the patch position is at a *fixed* offset
288 * (PATCHER_LONGBRANCHES_NOPS_SKIP) of the return address.
291 cd->mcodeptr = tmpmcodeptr + PATCHER_LONGBRANCHES_NOPS_SKIP - SZ_BASR;
292 M_JMP(REG_ITMP3, REG_ITMP3);
295 /* Generating short branches */
297 M_BSR(REG_ITMP3, disp);
300 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
302 /* create stack frame */
304 M_ASUB_IMM(6 * 4, REG_SP);
306 /* move return address onto stack */
308 M_AST(REG_ITMP3, REG_SP, 5 * 4);
310 /* move pointer to java_objectheader onto stack */
312 #if defined(ENABLE_THREADS)
313 /* create a virtual java_objectheader */
315 (void) dseg_add_unique_address(cd, NULL); /* flcword */
316 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
317 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
319 M_LDA_DSEG(REG_ITMP3, disp);
320 M_AST(REG_ITMP3, REG_SP, 4 * 4);
325 /* move machine code onto stack */
327 disp = dseg_add_s4(cd, mcode);
328 M_ILD_DSEG(REG_ITMP3, disp);
329 M_IST(REG_ITMP3, REG_SP, 3 * 4);
331 /* move class/method/field reference onto stack */
333 disp = dseg_add_address(cd, pref->ref);
334 M_ALD_DSEG(REG_ITMP3, disp);
335 M_AST(REG_ITMP3, REG_SP, 2 * 4);
337 /* move data segment displacement onto stack */
339 disp = dseg_add_s4(cd, pref->disp);
340 M_ILD_DSEG(REG_ITMP3, disp);
341 M_IST(REG_ITMP3, REG_SP, 1 * 4);
343 /* move patcher function pointer onto stack */
345 disp = dseg_add_functionptr(cd, pref->patcher);
346 M_ALD_DSEG(REG_ITMP3, disp);
347 M_AST(REG_ITMP3, REG_SP, 0 * 4);
349 if (targetdisp == 0) {
350 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
352 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
353 M_ALD_DSEG(REG_ITMP3, disp);
354 M_JMP(RN, REG_ITMP3);
357 disp = ((cd->mcodebase) + targetdisp) -
360 emit_branch(cd, disp, BRANCH_UNCONDITIONAL, RN, 0);
366 /* emit_replacement_stubs ******************************************************
368 Generates the code for the replacement stubs.
370 *******************************************************************************/
371 #if defined(ENABLE_REPLACEMENT)
372 void emit_replacement_stubs(jitdata *jd)
381 /* get required compiler data */
386 rplp = code->rplpoints;
388 /* store beginning of replacement stubs */
390 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
392 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
393 /* do not generate stubs for non-trappable points */
395 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
398 /* check code segment size */
403 savedmcodeptr = cd->mcodeptr;
406 /* create stack frame - 8-byte aligned */
408 M_ASUB_IMM(REG_SP, 2 * 4);
410 /* push address of `rplpoint` struct, will be used in asm_replacement_out */
412 disp = dseg_add_address(cd, rplp);
413 M_ALD_DSEG(REG_ITMP3, disp);
414 M_AST(REG_ITMP3, REG_SP, 0 * 4);
416 /* jump to replacement function */
418 disp = dseg_add_functionptr(cd, asm_replacement_out);
419 M_ALD_DSEG(REG_ITMP3, disp);
420 M_JMP(RN, REG_ITMP3);
422 assert((cd->mcodeptr - savedmcodeptr) <= REPLACEMENT_STUB_SIZE);
426 for (remain = REPLACEMENT_STUB_SIZE - (cd->mcodeptr - savedmcodeptr); remain > 0;) {
436 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
441 /* emit_verbosecall_enter ******************************************************
443 Generates the code for the call trace.
445 *******************************************************************************/
448 void emit_verbosecall_enter(jitdata *jd)
455 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
457 /* get required compiler data */
464 /* mark trace code */
469 (6 * 8) + /* s8 on stack parameters x 6 */
470 (1 * 4) + /* methodinfo on stack parameter */
475 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
477 /* save argument registers */
479 off = (6 * 8) + (1 * 4);
481 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
482 M_IST(abi_registers_integer_argument[i], REG_SP, off);
484 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
485 M_DST(abi_registers_float_argument[i], REG_SP, off);
487 /* save temporary registers for leaf methods */
489 if (jd->isleafmethod) {
490 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
491 M_LST(abi_registers_integer_temporary[i], REG_SP, off);
493 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
494 M_DST(abi_registers_float_temporary[i], REG_SP, off);
497 /* Load arguments to new locations */
499 /* First move all arguments to stack
504 * (s8) a1 \ Auxilliary stack frame
509 M_ASUB_IMM(2 * 8, REG_SP);
511 /* offset to where first integer arg is saved on stack */
512 off = (2 * 8) + (6 * 8) + (1 * 4);
513 /* offset to where first float arg is saved on stack */
514 foff = off + (INT_ARG_CNT * 8);
515 /* offset to where first argument is passed on stack */
516 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 4);
517 /* offset to destination on stack */
520 iargctr = fargctr = 0;
522 ICONST(REG_ITMP1, 0);
524 for (i = 0; i < md->paramcount && i < 8; i++) {
525 t = md->paramtypes[i].type;
527 M_IST(REG_ITMP1, REG_SP, doff);
528 M_IST(REG_ITMP1, REG_SP, doff + 4);
530 if (IS_FLT_DBL_TYPE(t)) {
531 if (fargctr < 2) { /* passed in register */
532 N_STD(abi_registers_float_argument[fargctr], doff, RN, REG_SP);
534 } else { /* passed on stack */
535 if (IS_2_WORD_TYPE(t)) {
536 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
539 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
544 if (IS_2_WORD_TYPE(t)) {
545 if (iargctr < 4) { /* passed in 2 registers */
546 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
548 } else { /* passed on stack */
549 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
553 if (iargctr < 5) { /* passed in register */
554 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
556 } else { /* passed on stack */
557 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
566 /* Now move a0 and a1 to registers
576 N_LM(REG_A0, REG_A1, 0, REG_SP);
577 N_LM(REG_A2, REG_A3, 8, REG_SP);
579 M_AADD_IMM(2 * 8, REG_SP);
581 /* Finally load methodinfo argument */
583 disp = dseg_add_address(cd, m);
584 M_ALD_DSEG(REG_ITMP2, disp);
585 M_AST(REG_ITMP2, REG_SP, 6 * 8);
587 /* Call builtin_verbosecall_enter */
589 disp = dseg_add_address(cd, builtin_verbosecall_enter);
590 M_ALD_DSEG(REG_ITMP2, disp);
591 M_ASUB_IMM(96, REG_SP);
593 M_AADD_IMM(96, REG_SP);
595 /* restore argument registers */
597 off = (6 * 8) + (1 * 4);
599 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
600 M_ILD(abi_registers_integer_argument[i], REG_SP, off);
602 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
603 M_DLD(abi_registers_float_argument[i], REG_SP, off);
605 /* restore temporary registers for leaf methods */
607 if (jd->isleafmethod) {
608 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
609 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
611 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
612 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
615 /* remove stackframe */
617 M_AADD_IMM(stackframesize, REG_SP);
619 /* mark trace code */
623 #endif /* !defined(NDEBUG) */
626 /* emit_verbosecall_exit *******************************************************
628 Generates the code for the call trace.
630 *******************************************************************************/
633 void emit_verbosecall_exit(jitdata *jd)
640 /* get required compiler data */
646 /* mark trace code */
650 M_ASUB_IMM(2 * 8, REG_SP);
652 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
653 M_DST(REG_FRESULT, REG_SP, 1 * 8);
655 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
656 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
658 M_INTMOVE(REG_RESULT, REG_A1);
662 disp = dseg_add_address(cd, m);
663 M_ALD_DSEG(REG_A2, disp);
665 /* REG_FRESULT is REG_FA0, so no need to move */
666 M_FLTMOVE(REG_FRESULT, REG_FA1);
668 disp = dseg_add_address(cd, builtin_verbosecall_exit);
669 M_ALD_DSEG(REG_ITMP1, disp);
670 M_ASUB_IMM(96, REG_SP);
672 M_AADD_IMM(96, REG_SP);
674 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
675 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
677 M_AADD_IMM(2 * 8, REG_SP);
679 /* mark trace code */
683 #endif /* !defined(NDEBUG) */
686 /* emit_load_high **************************************************************
688 Emits a possible load of the high 32-bits of an operand.
690 *******************************************************************************/
692 __PORTED__ s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
698 assert(src->type == TYPE_LNG);
700 /* get required compiler data */
704 if (IS_INMEMORY(src->flags)) {
707 disp = src->vv.regoff;
709 M_ILD(tempreg, REG_SP, disp);
714 reg = GET_HIGH_REG(src->vv.regoff);
719 /* emit_load_low ***************************************************************
721 Emits a possible load of the low 32-bits of an operand.
723 *******************************************************************************/
725 __PORTED__ s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
731 assert(src->type == TYPE_LNG);
733 /* get required compiler data */
737 if (IS_INMEMORY(src->flags)) {
740 disp = src->vv.regoff;
742 M_ILD(tempreg, REG_SP, disp + 4);
747 reg = GET_LOW_REG(src->vv.regoff);
752 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
753 codegendata *cd = jd->cd;
754 s4 reg = emit_load_s1(jd, iptr, tempreg);
763 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
764 codegendata *cd = jd->cd;
765 s4 reg = emit_load_s2(jd, iptr, tempreg);
767 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
768 M_FMOV(reg, tempreg);
778 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
779 codegendata *cd = jd->cd;
780 s4 reg = emit_load_s1(jd, iptr, tempreg);
782 if (IS_FLT_DBL_TYPE(VAROP(iptr->s1)->type)) {
783 M_FMOV(reg, tempreg);
793 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
794 codegendata *cd = jd->cd;
795 s4 reg = emit_load_s2(jd, iptr, tempreg);
797 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
798 M_FMOV(reg, tempreg);
808 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
819 * (r12, r13) Illegal, because r13 is PV
820 * (r14, r15) Illegal, because r15 is SP
824 dst = VAROP(iptr->dst);
826 if (IS_INMEMORY(dst->flags)) {
827 if (! IS_REG_ITMP(ltmpreg)) {
828 M_INTMOVE(ltmpreg, breg);
830 if (! IS_REG_ITMP(htmpreg)) {
831 M_INTMOVE(htmpreg, breg);
833 return PACK_REGS(ltmpreg, htmpreg);
835 hr = GET_HIGH_REG(dst->vv.regoff);
836 lr = GET_LOW_REG(dst->vv.regoff);
837 if (((hr % 2) == 0) && lr == (hr + 1)) {
838 /* the result is already in a even-odd pair */
839 return dst->vv.regoff;
840 } else if (((hr % 2) == 0) && (hr < R12)) {
841 /* the high register is at a even position */
842 M_INTMOVE(hr + 1, breg);
843 return PACK_REGS(hr + 1, hr);
844 } else if (((lr % 2) == 1) && (lr < R12)) {
845 /* the low register is at a odd position */
846 M_INTMOVE(lr - 1, breg);
847 return PACK_REGS(lr, lr - 1);
849 /* no way to create an even-odd pair by 1 copy operation,
850 * Use the temporary register pair.
852 if (! IS_REG_ITMP(ltmpreg)) {
853 M_INTMOVE(ltmpreg, breg);
855 if (! IS_REG_ITMP(htmpreg)) {
856 M_INTMOVE(htmpreg, breg);
858 return PACK_REGS(ltmpreg, htmpreg);
863 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
869 dst = VAROP(iptr->dst);
871 if (IS_INMEMORY(dst->flags)) {
872 if (! IS_REG_ITMP(ltmpreg)) {
873 M_INTMOVE(breg, ltmpreg);
875 if (! IS_REG_ITMP(htmpreg)) {
876 M_INTMOVE(breg, htmpreg);
879 hr = GET_HIGH_REG(dst->vv.regoff);
880 lr = GET_LOW_REG(dst->vv.regoff);
881 if (((hr % 2) == 0) && lr == (hr + 1)) {
883 } else if (((hr % 2) == 0) && (hr < R12)) {
884 M_INTMOVE(breg, hr + 1);
885 } else if (((lr % 2) == 1) && (lr < R12)) {
886 M_INTMOVE(breg, lr - 1);
888 if (! IS_REG_ITMP(ltmpreg)) {
889 M_INTMOVE(breg, ltmpreg);
891 if (! IS_REG_ITMP(htmpreg)) {
892 M_INTMOVE(breg, htmpreg);
898 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
902 dst = VAROP(iptr->dst);
903 if (! IS_INMEMORY(dst->flags)) {
904 if (dst->vv.regoff != dtmpreg) {
905 if (IS_FLT_DBL_TYPE(dst->type)) {
906 M_FLTMOVE(dtmpreg, dst->vv.regoff);
907 } else if (IS_2_WORD_TYPE(dst->type)) {
908 M_LNGMOVE(dtmpreg, dst->vv.regoff);
910 M_INTMOVE(dtmpreg, dst->vv.regoff);
916 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
918 s4 branchdisp = disp;
922 if (N_VALID_BRANCH(branchdisp)) {
924 /* valid displacement */
945 case BRANCH_UNCONDITIONAL:
949 vm_abort("emit_branch: unknown condition %d", condition);
953 /* If LONGBRANCHES is not set, the flag and the error flag */
955 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
956 cd->flags |= (CODEGENDATA_FLAG_ERROR |
957 CODEGENDATA_FLAG_LONGBRANCHES);
960 /* If error flag is set, do nothing. The method has to be recompiled. */
962 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
966 /* Patch the displacement to branch over the actual branch manually
967 * to not get yet more nops.
970 branchmpc = cd->mcodeptr - cd->mcodebase;
992 case BRANCH_UNCONDITIONAL:
993 /* fall through, no displacement to patch */
997 vm_abort("emit_branch: unknown condition %d", condition);
1000 /* The actual long branch */
1002 disp = dseg_add_s4(cd, branchmpc + disp - N_PV_OFFSET);
1003 M_ILD_DSEG(REG_ITMP3, disp);
1004 M_AADD(REG_PV, REG_ITMP3);
1005 M_JMP(RN, REG_ITMP3);
1007 /* Patch back the displacement */
1010 *(u4 *)ref |= (u4)((cd->mcodeptr - ref) / 2);
1015 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
1016 if (INSTRUCTION_MUST_CHECK(iptr)) {
1018 M_BNE(SZ_BRC + SZ_ILL);
1019 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
1023 /* emit_arrayindexoutofbounds_check ********************************************
1025 Emit a ArrayIndexOutOfBoundsException check.
1027 *******************************************************************************/
1029 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
1031 if (INSTRUCTION_MUST_CHECK(iptr)) {
1033 * Do unsigned comparison to catch negative indexes.
1035 N_CL(s2, OFFSET(java_arrayheader, size), RN, s1);
1036 M_BLT(SZ_BRC + SZ_ILL);
1037 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
1041 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
1042 if (INSTRUCTION_MUST_CHECK(iptr)) {
1046 switch (condition) {
1048 M_BGT(SZ_BRC + SZ_ILL);
1051 M_BNE(SZ_BRC + SZ_ILL);
1054 M_BLE(SZ_BRC + SZ_ILL);
1057 vm_abort("emit_classcast_check: unknown condition %d", condition);
1059 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
1063 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
1064 if (INSTRUCTION_MUST_CHECK(iptr)) {
1066 M_BNE(SZ_BRC + SZ_ILL);
1067 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
1071 void emit_exception_check(codegendata *cd, instruction *iptr) {
1072 if (INSTRUCTION_MUST_CHECK(iptr)) {
1074 M_BNE(SZ_BRC + SZ_ILL);
1075 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
1079 void emit_restore_pv(codegendata *cd) {
1080 s4 offset, offset_imm;
1084 disp = (s4) (cd->mcodeptr - cd->mcodebase);
1085 M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
1088 /* If the offset from the method start does not fit into an immediate
1089 * value, we can't put it into the data segment!
1092 /* Displacement from start of method to here */
1094 offset = (s4) (cd->mcodeptr - cd->mcodebase);
1095 offset_imm = -offset - SZ_BASR + N_PV_OFFSET;
1097 if (N_VALID_IMM(offset_imm)) {
1098 /* Get program counter */
1100 /* Substract displacement */
1101 M_AADD_IMM(offset_imm, REG_PV);
1103 /* Save program counter and jump over displacement in instruction flow */
1104 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
1105 /* Place displacement here */
1106 /* REG_PV points now exactly to this position */
1107 N_LONG(-offset - SZ_BRAS + N_PV_OFFSET);
1108 /* Substract *(REG_PV) from REG_PV */
1109 N_A(REG_PV, 0, RN, REG_PV);
1114 * These are local overrides for various environment variables in Emacs.
1115 * Please do not remove this and leave it at the end of the file, where
1116 * Emacs will automagically detect them.
1117 * ---------------------------------------------------------------------
1120 * indent-tabs-mode: t