src/vm/jit/s390/emit.c

   1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
   2
   3    Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
   4    C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
   5    E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
   6    J. Wenninger, Institut f. Computersprachen - TU Wien
   7
   8    This file is part of CACAO.
   9
  10    This program is free software; you can redistribute it and/or
  11    modify it under the terms of the GNU General Public License as
  12    published by the Free Software Foundation; either version 2, or (at
  13    your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful, but
  16    WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18    General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  23    02110-1301, USA.
  24
  25 */
  26
  27 #include "config.h"
  28
  29 #include <assert.h>
  30 #include <stdint.h>
  31
  32 #include "mm/memory.h"
  33 #if defined(ENABLE_THREADS)
  34 # include "threads/native/lock.h"
  35 #endif
  36 #include "vm/builtin.h"
  37 #include "vm/exceptions.h"
  38 #include "vm/global.h"
  39 #include "vm/jit/abi.h"
  40 #include "vm/jit/abi-asm.h"
  41 #include "vm/jit/asmpart.h"
  42 #include "vm/jit/codegen-common.h"
  43 #include "vm/jit/emit-common.h"
  44 #include "vm/jit/jit.h"
  45 #include "vm/jit/patcher-common.h"
  46 #include "vm/jit/replace.h"
  47 #include "vm/jit/trace.h"
  48 #include "vm/jit/s390/codegen.h"
  49 #include "vm/jit/s390/emit.h"
  50 #include "vm/jit/s390/md-abi.h"
  51 #include "vm/types.h"
  52 #include "vmcore/options.h"
  53
  54 /* emit_load *******************************************************************
  55
  56    Emits a possible load of an operand.
  57
  58 *******************************************************************************/
  59
  60 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
  61 {
  62         codegendata *cd;
  63         s4           disp;
  64         s4           reg;
  65
  66         /* get required compiler data */
  67
  68         cd = jd->cd;
  69
  70         if (IS_INMEMORY(src->flags)) {
  71                 COUNT_SPILLS;
  72
  73                 disp = src->vv.regoff;
  74
  75                 if (IS_FLT_DBL_TYPE(src->type)) {
  76                         if (IS_2_WORD_TYPE(src->type))
  77                                 M_DLD(tempreg, REG_SP, disp);
  78                         else
  79                                 M_FLD(tempreg, REG_SP, disp);
  80                 }
  81                 else {
  82                         if (IS_2_WORD_TYPE(src->type))
  83                                 M_LLD(tempreg, REG_SP, disp);
  84                         else
  85                                 M_ILD(tempreg, REG_SP, disp);
  86                 }
  87
  88                 reg = tempreg;
  89         }
  90         else
  91                 reg = src->vv.regoff;
  92
  93         return reg;
  94 }
  95
  96
  97 /* emit_store ******************************************************************
  98
  99    This function generates the code to store the result of an
 100    operation back into a spilled pseudo-variable.  If the
 101    pseudo-variable has not been spilled in the first place, this
 102    function will generate nothing.
 103
 104 *******************************************************************************/
 105
 106 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
 107 {
 108         codegendata *cd;
 109
 110         /* get required compiler data */
 111
 112         cd = jd->cd;
 113
 114         if (IS_INMEMORY(dst->flags)) {
 115                 COUNT_SPILLS;
 116
 117                 if (IS_FLT_DBL_TYPE(dst->type)) {
 118                         if (IS_2_WORD_TYPE(dst->type))
 119                                 M_DST(d, REG_SP, dst->vv.regoff);
 120                         else
 121                                 M_FST(d, REG_SP, dst->vv.regoff);
 122                 }
 123                 else {
 124                         if (IS_2_WORD_TYPE(dst->type))
 125                                 M_LST(d, REG_SP, dst->vv.regoff);
 126                         else
 127                                 M_IST(d, REG_SP, dst->vv.regoff);
 128                 }
 129         }
 130 }
 131
 132
 133 /* emit_copy *******************************************************************
 134
 135    Generates a register/memory to register/memory copy.
 136
 137 *******************************************************************************/
 138
 139 void emit_copy(jitdata *jd, instruction *iptr)
 140 {
 141         codegendata *cd;
 142         varinfo     *src;
 143         varinfo     *dst;
 144         s4           s1, d;
 145
 146         /* get required compiler data */
 147
 148         cd = jd->cd;
 149
 150         /* get source and destination variables */
 151
 152         src = VAROP(iptr->s1);
 153         dst = VAROP(iptr->dst);
 154
 155         if ((src->vv.regoff != dst->vv.regoff) ||
 156                 ((src->flags ^ dst->flags) & INMEMORY)) {
 157
 158                 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
 159                         /* emit nothing, as the value won't be used anyway */
 160                         return;
 161                 }
 162
 163                 if (IS_INMEMORY(src->flags) && IS_INMEMORY(dst->flags)) {
 164                         if (IS_2_WORD_TYPE(src->type)) {
 165                                 N_MVC(dst->vv.regoff, 8, REG_SP, src->vv.regoff, REG_SP);
 166                         } else {
 167                                 N_MVC(dst->vv.regoff, 4, REG_SP, src->vv.regoff, REG_SP);
 168                         }
 169                 } else {
 170
 171                         /* If one of the variables resides in memory, we can eliminate
 172                            the register move from/to the temporary register with the
 173                            order of getting the destination register and the load. */
 174
 175                         if (IS_INMEMORY(src->flags)) {
 176                                 if (IS_FLT_DBL_TYPE(dst->type)) {
 177                                         d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
 178                                 } else {
 179                                         if (IS_2_WORD_TYPE(dst->type)) {
 180                                                 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
 181                                         } else {
 182                                                 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
 183                                         }
 184                                 }
 185                                 s1 = emit_load(jd, iptr, src, d);
 186                         }
 187                         else {
 188                                 if (IS_FLT_DBL_TYPE(src->type)) {
 189                                         s1 = emit_load(jd, iptr, src, REG_FTMP1);
 190                                 } else {
 191                                         if (IS_2_WORD_TYPE(src->type)) {
 192                                                 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
 193                                         } else {
 194                                                 s1 = emit_load(jd, iptr, src, REG_ITMP1);
 195                                         }
 196                                 }
 197                                 d = codegen_reg_of_var(iptr->opc, dst, s1);
 198                         }
 199
 200                         if (s1 != d) {
 201                                 if (IS_FLT_DBL_TYPE(src->type)) {
 202                                         M_FMOV(s1, d);
 203                                 } else {
 204                                         if (IS_2_WORD_TYPE(src->type)) {
 205                                                 M_LNGMOVE(s1, d);
 206                                         } else {
 207                                                 M_MOV(s1, d);
 208                                         }
 209                                 }
 210                         }
 211
 212                         emit_store(jd, iptr, dst, d);
 213                 }
 214         }
 215 }
 216
 217 /* emit_trap *******************************************************************
 218
 219    Emit a trap instruction and return the original machine code.
 220
 221 *******************************************************************************/
 222
 223 uint32_t emit_trap(codegendata *cd)
 224 {
 225         uint32_t mcode;
 226
 227         /* Get machine code which is patched back in later. The
 228            trap is 2 bytes long. */
 229
 230         mcode = *((u2 *) cd->mcodeptr);
 231
 232         M_ILL(EXCEPTION_HARDWARE_PATCHER);
 233
 234         return mcode;
 235 }
 236
 237
 238 /* emit_verbosecall_enter ******************************************************
 239
 240    Generates the code for the call trace.
 241
 242 *******************************************************************************/
 243
 244 #if !defined(NDEBUG)
 245 void emit_verbosecall_enter(jitdata *jd)
 246 {
 247         methodinfo   *m;
 248         codegendata  *cd;
 249         methoddesc   *md;
 250         s4            stackframesize;
 251         s4            i, off, disp, s;
 252
 253         m  = jd->m;
 254         cd = jd->cd;
 255         md = m->parseddesc;
 256
 257         /* mark trace code */
 258
 259         M_NOP;
 260
 261         /* allocate stack frame */
 262
 263         stackframesize = 96 + (md->paramcount * 8);
 264
 265         /* for leaf methods we need to store unused argument and temporary registers */
 266
 267         if (jd->isleafmethod) {
 268                 stackframesize += (ARG_CNT + TMP_CNT) * 8;
 269         }
 270
 271         /* allocate stack frame */
 272
 273         M_ASUB_IMM(stackframesize, REG_SP);
 274
 275         /* store argument registers in array */
 276
 277         off = 96;
 278
 279         for (i = 0; i < md->paramcount; i++) {
 280                 if (! md->params[i].inmemory) {
 281                         s = md->params[i].regoff;
 282                         switch (md->paramtypes[i].type) {
 283                                 case TYPE_INT:
 284                                 case TYPE_ADR:
 285                                         M_IST(s, REG_SP, off);
 286                                         break;
 287                                 case TYPE_LNG:
 288                                         M_LST(s, REG_SP, off);
 289                                         break;
 290                                 case TYPE_FLT:
 291                                         M_FST(s, REG_SP, off);
 292                                         break;
 293                                 case TYPE_DBL:
 294                                         M_DST(s, REG_SP, off);
 295                                         break;
 296                         }
 297                 }
 298                 off += 8;
 299         }
 300
 301         /* save unused (currently all) argument registers for leaf methods */
 302         /* save temporary registers for leaf methods */
 303
 304         if (jd->isleafmethod) {
 305
 306                 for (i = 0; i < INT_ARG_CNT; ++i, off += 8) {
 307                         M_IST(abi_registers_integer_argument[i], REG_SP, off);
 308                 }
 309
 310                 for (i = 0; i < FLT_ARG_CNT; ++i, off += 8) {
 311                         M_DST(abi_registers_float_argument[i], REG_SP, off);
 312                 }
 313
 314                 for (i = 0; i < INT_TMP_CNT; ++i, off += 8) {
 315                         M_IST(abi_registers_integer_temporary[i], REG_SP, off);
 316                 }
 317
 318                 for (i = 0; i < FLT_TMP_CNT; ++i, off += 8) {
 319                         M_DST(abi_registers_float_temporary[i], REG_SP, off);
 320                 }
 321         }
 322
 323         /* load arguments for trace_java_call_enter */
 324
 325         /* methodinfo */
 326
 327         disp = dseg_add_address(cd, m);
 328         M_ALD_DSEG(REG_A0, disp);
 329         /* pointer to argument registers array */
 330         M_LDA(REG_A1, REG_SP, 96);
 331         /* pointer to on stack arguments */
 332         M_LDA(REG_A2, REG_SP, stackframesize + (cd->stackframesize * 8));
 333
 334         /* call trace_java_call_enter */
 335
 336         disp = dseg_add_functionptr(cd, trace_java_call_enter);
 337         M_ALD_DSEG(REG_ITMP2, disp);
 338         M_CALL(REG_ITMP2);
 339
 340         /* restore used argument registers */
 341         /* for leaf methods restore all argument and temporary registers */
 342
 343         if (jd->isleafmethod) {
 344                 off = 96 + (8 * md->paramcount);
 345
 346                 for (i = 0; i < INT_ARG_CNT; ++i, off += 8) {
 347                         M_ILD(abi_registers_integer_argument[i], REG_SP, off);
 348                 }
 349
 350                 for (i = 0; i < FLT_ARG_CNT; ++i, off += 8) {
 351                         M_DLD(abi_registers_float_argument[i], REG_SP, off);
 352                 }
 353
 354                 for (i = 0; i < INT_TMP_CNT; ++i, off += 8) {
 355                         M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
 356                 }
 357
 358                 for (i = 0; i < FLT_TMP_CNT; ++i, off += 8) {
 359                         M_DLD(abi_registers_float_temporary[i], REG_SP, off);
 360                 }
 361         } else {
 362                 off = 96;
 363
 364                 for (i = 0; i < md->paramcount; i++) {
 365                         if (! md->params[i].inmemory) {
 366                                 s = md->params[i].regoff;
 367                                 switch (md->paramtypes[i].type) {
 368                                         case TYPE_INT:
 369                                         case TYPE_ADR:
 370                                                 M_ILD(s, REG_SP, off);
 371                                                 break;
 372                                         case TYPE_LNG:
 373                                                 M_LLD(s, REG_SP, off);
 374                                                 break;
 375                                         case TYPE_FLT:
 376                                                 M_FLD(s, REG_SP, off);
 377                                                 break;
 378                                         case TYPE_DBL:
 379                                                 M_DLD(s, REG_SP, off);
 380                                                 break;
 381                                 }
 382                         }
 383                         off += 8;
 384                 }
 385         }
 386
 387         /* remove stack frame */
 388
 389         M_AADD_IMM(stackframesize, REG_SP);
 390
 391         /* mark trace code */
 392
 393         M_NOP;
 394
 395 }
 396 #endif /* !defined(NDEBUG) */
 397
 398
 399 /* emit_verbosecall_exit *******************************************************
 400
 401    Generates the code for the call trace.
 402
 403 *******************************************************************************/
 404
 405 #if !defined(NDEBUG)
 406 void emit_verbosecall_exit(jitdata *jd)
 407 {
 408         methodinfo   *m;
 409         codegendata  *cd;
 410         s4            disp;
 411         s4            stackframesize;
 412         s4            off;
 413         s4            t;
 414
 415         m  = jd->m;
 416         cd = jd->cd;
 417         t = m->parseddesc->returntype.type;
 418
 419         /* mark trace code */
 420
 421         M_NOP;
 422
 423         /* allocate stackframe */
 424
 425         stackframesize = 96 + (1 * 8);
 426         M_ASUB_IMM(stackframesize, REG_SP);
 427
 428         off = 96;
 429
 430         /* store return values in array */
 431
 432         if (IS_INT_LNG_TYPE(t)) {
 433                 if (IS_2_WORD_TYPE(t)) {
 434                         M_LST(REG_RESULT_PACKED, REG_SP, off);
 435                 } else {
 436                         M_IST(REG_RESULT, REG_SP, off);
 437                 }
 438         } else {
 439                 M_DST(REG_FRESULT, REG_SP, off);
 440         }
 441
 442         /* call trace_java_call_exit */
 443
 444         disp = dseg_add_address(cd, m);
 445         M_ALD_DSEG(REG_A0, disp);
 446         M_LDA(REG_A1, REG_SP, off);
 447         disp = dseg_add_functionptr(cd, trace_java_call_exit);
 448         M_ALD_DSEG(REG_ITMP2, disp);
 449         M_CALL(REG_ITMP2);
 450
 451         /* restore return value */
 452
 453         if (IS_INT_LNG_TYPE(t)) {
 454                 if (IS_2_WORD_TYPE(t)) {
 455                         M_LLD(REG_RESULT_PACKED, REG_SP, off);
 456                 } else {
 457                         M_ILD(REG_RESULT, REG_SP, off);
 458                 }
 459         } else {
 460                 M_DLD(REG_FRESULT, REG_SP, off);
 461         }
 462
 463         /* remove stackframe */
 464
 465         M_AADD_IMM(stackframesize, REG_SP);
 466
 467         /* mark trace code */
 468
 469         M_NOP;
 470 }
 471 #endif /* !defined(NDEBUG) */
 472
 473
 474 /* emit_load_high **************************************************************
 475
 476    Emits a possible load of the high 32-bits of an operand.
 477
 478 *******************************************************************************/
 479
 480 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
 481 {
 482         codegendata  *cd;
 483         s4            disp;
 484         s4            reg;
 485
 486         assert(src->type == TYPE_LNG);
 487
 488         /* get required compiler data */
 489
 490         cd = jd->cd;
 491
 492         if (IS_INMEMORY(src->flags)) {
 493                 COUNT_SPILLS;
 494
 495                 disp = src->vv.regoff;
 496
 497                 M_ILD(tempreg, REG_SP, disp);
 498
 499                 reg = tempreg;
 500         }
 501         else
 502                 reg = GET_HIGH_REG(src->vv.regoff);
 503
 504         return reg;
 505 }
 506
 507 /* emit_load_low ***************************************************************
 508
 509    Emits a possible load of the low 32-bits of an operand.
 510
 511 *******************************************************************************/
 512
 513 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
 514 {
 515         codegendata  *cd;
 516         s4            disp;
 517         s4            reg;
 518
 519         assert(src->type == TYPE_LNG);
 520
 521         /* get required compiler data */
 522
 523         cd = jd->cd;
 524
 525         if (IS_INMEMORY(src->flags)) {
 526                 COUNT_SPILLS;
 527
 528                 disp = src->vv.regoff;
 529
 530                 M_ILD(tempreg, REG_SP, disp + 4);
 531
 532                 reg = tempreg;
 533         }
 534         else
 535                 reg = GET_LOW_REG(src->vv.regoff);
 536
 537         return reg;
 538 }
 539
 540 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
 541         codegendata *cd = jd->cd;
 542         s4 reg = emit_load_s1(jd, iptr, tempreg);
 543         if (reg == notreg) {
 544                 if (IS_FLT_DBL_TYPE(VAROP(iptr->s1)->type)) {
 545                         M_FMOV(reg, tempreg);
 546                 } else {
 547                         M_MOV(reg, tempreg);
 548                 }
 549                 return tempreg;
 550         } else {
 551                 return reg;
 552         }
 553 }
 554
 555 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
 556         codegendata *cd = jd->cd;
 557         s4 reg = emit_load_s2(jd, iptr, tempreg);
 558         if (reg == notreg) {
 559                 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
 560                         M_FMOV(reg, tempreg);
 561                 } else {
 562                         M_MOV(reg, tempreg);
 563                 }
 564                 return tempreg;
 565         } else {
 566                 return reg;
 567         }
 568 }
 569
 570 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
 571         codegendata *cd;
 572         varinfo *dst;
 573         cd = jd->cd;
 574         dst = VAROP(iptr->dst);
 575         if (! IS_INMEMORY(dst->flags)) {
 576                 if (dst->vv.regoff != dtmpreg) {
 577                         if (IS_FLT_DBL_TYPE(dst->type)) {
 578                                 M_FLTMOVE(dtmpreg, dst->vv.regoff);
 579                         } else if (IS_2_WORD_TYPE(dst->type)) {
 580                                 M_LNGMOVE(dtmpreg, dst->vv.regoff);
 581                         } else {
 582                                 M_INTMOVE(dtmpreg, dst->vv.regoff);
 583                         }
 584                 }
 585         }
 586 }
 587
 588 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
 589
 590         s4 branchdisp = disp;
 591         s4 branchmpc;
 592         u1 *ref;
 593
 594         if (N_VALID_BRANCH(branchdisp)) {
 595
 596                 /* valid displacement */
 597
 598                 switch (condition) {
 599                         case BRANCH_EQ:
 600                                 M_BEQ(branchdisp);
 601                                 break;
 602                         case BRANCH_NE:
 603                                 M_BNE(branchdisp);
 604                                 break;
 605                         case BRANCH_LT:
 606                                 M_BLT(branchdisp);
 607                                 break;
 608                         case BRANCH_GE:
 609                                 M_BGE(branchdisp);
 610                                 break;
 611                         case BRANCH_GT:
 612                                 M_BGT(branchdisp);
 613                                 break;
 614                         case BRANCH_LE:
 615                                 M_BLE(branchdisp);
 616                                 break;
 617                         case BRANCH_UNCONDITIONAL:
 618                                 M_BR(branchdisp);
 619                                 break;
 620                         default:
 621                                 vm_abort("emit_branch: unknown condition %d", condition);
 622                 }
 623         } else {
 624
 625                 /* If LONGBRANCHES is not set, the flag and the error flag */
 626
 627                 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
 628                         cd->flags |= (CODEGENDATA_FLAG_ERROR |
 629                                 CODEGENDATA_FLAG_LONGBRANCHES);
 630                 }
 631
 632                 /* If error flag is set, do nothing. The method has to be recompiled. */
 633
 634                 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
 635                         return;
 636                 }
 637
 638                 /* Patch the displacement to branch over the actual branch manually
 639                  * to not get yet more nops.
 640                  */
 641
 642                 branchmpc = cd->mcodeptr - cd->mcodebase;
 643                 ref = cd->mcodeptr;
 644
 645                 switch (condition) {
 646                         case BRANCH_EQ:
 647                                 M_BNE(0);
 648                                 break;
 649                         case BRANCH_NE:
 650                                 M_BEQ(0);
 651                                 break;
 652                         case BRANCH_LT:
 653                                 M_BGE(0);
 654                                 break;
 655                         case BRANCH_GE:
 656                                 M_BLT(0);
 657                                 break;
 658                         case BRANCH_GT:
 659                                 M_BLE(0);
 660                                 break;
 661                         case BRANCH_LE:
 662                                 M_BGT(0);
 663                                 break;
 664                         case BRANCH_UNCONDITIONAL:
 665                                 /* fall through, no displacement to patch */
 666                                 ref = NULL;
 667                                 break;
 668                         default:
 669                                 vm_abort("emit_branch: unknown condition %d", condition);
 670                 }
 671
 672                 /* The actual long branch */
 673
 674                 disp = dseg_add_s4(cd, branchmpc + disp - N_PV_OFFSET);
 675                 M_ILD_DSEG(REG_ITMP2, disp);
 676                 M_AADD(REG_PV, REG_ITMP2);
 677                 M_JMP(RN, REG_ITMP2);
 678
 679                 /* Patch back the displacement */
 680
 681                 N_BRC_BACK_PATCH(ref);
 682         }
 683 }
 684
 685 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
 686         if (INSTRUCTION_MUST_CHECK(iptr)) {
 687                 M_TEST(reg);
 688                 M_BNE(SZ_BRC + SZ_ILL);
 689                 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
 690         }
 691 }
 692
 693 /* emit_arrayindexoutofbounds_check ********************************************
 694
 695    Emit a ArrayIndexOutOfBoundsException check.
 696
 697 *******************************************************************************/
 698
 699 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
 700 {
 701         if (INSTRUCTION_MUST_CHECK(iptr)) {
 702                 /* Size is s4, >= 0
 703                  * Do unsigned comparison to catch negative indexes.
 704                  */
 705                 N_CL(s2, OFFSET(java_array_t, size), RN, s1);
 706         M_BLT(SZ_BRC + SZ_ILL);
 707                 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
 708         }
 709 }
 710
 711
 712 /* emit_arraystore_check *******************************************************
 713
 714    Emit an ArrayStoreException check.
 715
 716 *******************************************************************************/
 717
 718 void emit_arraystore_check(codegendata *cd, instruction *iptr)
 719 {
 720         if (INSTRUCTION_MUST_CHECK(iptr)) {
 721                 M_TEST(REG_RESULT);
 722                 M_BNE(SZ_BRC + SZ_ILL);
 723                 M_ILL(EXCEPTION_HARDWARE_ARRAYSTORE);
 724         }
 725 }
 726
 727
 728 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
 729         if (INSTRUCTION_MUST_CHECK(iptr)) {
 730                 if (reg != RN) {
 731                         M_TEST(reg);
 732                 }
 733                 switch (condition) {
 734                         case BRANCH_LE:
 735                                 M_BGT(SZ_BRC + SZ_ILL);
 736                                 break;
 737                         case BRANCH_EQ:
 738                                 M_BNE(SZ_BRC + SZ_ILL);
 739                                 break;
 740                         case BRANCH_GT:
 741                                 M_BLE(SZ_BRC + SZ_ILL);
 742                                 break;
 743                         default:
 744                                 vm_abort("emit_classcast_check: unknown condition %d", condition);
 745                 }
 746                 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
 747         }
 748 }
 749
 750 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
 751         if (INSTRUCTION_MUST_CHECK(iptr)) {
 752                 M_TEST(reg);
 753                 M_BNE(SZ_BRC + SZ_ILL);
 754                 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
 755         }
 756 }
 757
 758 void emit_exception_check(codegendata *cd, instruction *iptr) {
 759         if (INSTRUCTION_MUST_CHECK(iptr)) {
 760                 M_TEST(REG_RESULT);
 761                 M_BNE(SZ_BRC + SZ_ILL);
 762                 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
 763         }
 764 }
 765
 766 void emit_restore_pv(codegendata *cd) {
 767         s4 offset, offset_imm;
 768
 769         /*
 770         N_BASR(REG_PV, RN);
 771         disp = (s4) (cd->mcodeptr - cd->mcodebase);
 772         M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
 773         */
 774
 775         /* If the offset from the method start does not fit into an immediate
 776          * value, we can't put it into the data segment!
 777          */
 778
 779         /* Displacement from start of method to here */
 780
 781         offset = (s4) (cd->mcodeptr - cd->mcodebase);
 782         offset_imm = -offset - SZ_BASR + N_PV_OFFSET;
 783
 784         if (N_VALID_IMM(offset_imm)) {
 785                 /* Get program counter */
 786                 N_BASR(REG_PV, RN);
 787                 /* Substract displacement */
 788                 M_AADD_IMM(offset_imm, REG_PV);
 789         } else {
 790                 /* Save program counter and jump over displacement in instruction flow */
 791                 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
 792                 /* Place displacement here */
 793                 /* REG_PV points now exactly to this position */
 794                 N_LONG(-offset - SZ_BRAS + N_PV_OFFSET);
 795                 /* Substract *(REG_PV) from REG_PV */
 796                 N_A(REG_PV, 0, RN, REG_PV);
 797         }
 798 }
 799
 800 /*
 801  * These are local overrides for various environment variables in Emacs.
 802  * Please do not remove this and leave it at the end of the file, where
 803  * Emacs will automagically detect them.
 804  * ---------------------------------------------------------------------
 805  * Local variables:
 806  * mode: c
 807  * indent-tabs-mode: t
 808  * c-basic-offset: 4
 809  * tab-width: 4
 810  * End:
 811  */