1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Christian Thalinger
29 $Id: emit.c 7442 2007-03-02 23:28:37Z pm $
41 #include "vm/jit/s390/codegen.h"
42 #include "vm/jit/s390/emit.h"
44 #if defined(ENABLE_THREADS)
45 # include "threads/native/lock.h"
48 #include "vm/builtin.h"
49 #include "vm/jit/abi-asm.h"
50 #include "vm/jit/asmpart.h"
51 #include "vm/jit/codegen-common.h"
52 #include "vm/jit/emit-common.h"
53 #include "vm/jit/jit.h"
54 #include "vm/jit/replace.h"
55 #include "vm/global.h"
56 #include "mm/memory.h"
60 /* emit_load *******************************************************************
62 Emits a possible load of an operand.
64 *******************************************************************************/
66 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
72 /* get required compiler data */
76 if (IS_INMEMORY(src->flags)) {
79 disp = src->vv.regoff * 4;
81 if (IS_FLT_DBL_TYPE(src->type)) {
82 if (IS_2_WORD_TYPE(src->type))
83 M_DLD(tempreg, REG_SP, disp);
85 M_FLD(tempreg, REG_SP, disp);
88 if (IS_2_WORD_TYPE(src->type))
89 M_LLD(tempreg, REG_SP, disp);
91 M_ILD(tempreg, REG_SP, disp);
103 /* emit_store ******************************************************************
105 This function generates the code to store the result of an
106 operation back into a spilled pseudo-variable. If the
107 pseudo-variable has not been spilled in the first place, this
108 function will generate nothing.
110 *******************************************************************************/
112 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
116 /* get required compiler data */
120 if (IS_INMEMORY(dst->flags)) {
123 if (IS_FLT_DBL_TYPE(dst->type)) {
124 if (IS_2_WORD_TYPE(dst->type))
125 M_DST(d, REG_SP, dst->vv.regoff * 4);
127 M_FST(d, REG_SP, dst->vv.regoff * 4);
130 if (IS_2_WORD_TYPE(dst->type))
131 M_LST(d, REG_SP, dst->vv.regoff * 4);
133 M_IST(d, REG_SP, dst->vv.regoff * 4);
139 /* emit_copy *******************************************************************
141 Generates a register/memory to register/memory copy.
143 *******************************************************************************/
145 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
150 /* get required compiler data */
154 if ((src->vv.regoff != dst->vv.regoff) ||
155 ((src->flags ^ dst->flags) & INMEMORY)) {
157 /* If one of the variables resides in memory, we can eliminate
158 the register move from/to the temporary register with the
159 order of getting the destination register and the load. */
161 if (IS_INMEMORY(src->flags)) {
162 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
163 s1 = emit_load(jd, iptr, src, d);
166 s1 = emit_load(jd, iptr, src, REG_IFTMP);
167 d = codegen_reg_of_var(iptr->opc, dst, s1);
171 if (IS_FLT_DBL_TYPE(src->type))
177 emit_store(jd, iptr, dst, d);
182 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
185 switch (iptr->flags.fields.condition) {
209 /* emit_exception_stubs ********************************************************
211 Generates the code for the exception stubs.
213 *******************************************************************************/
215 void emit_exception_stubs(jitdata *jd)
225 /* get required compiler data */
230 /* generate exception stubs */
234 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
235 /* back-patch the branch to this exception code */
237 branchmpc = er->branchpos;
238 targetmpc = cd->mcodeptr - cd->mcodebase;
240 md_codegen_patch_branch(cd, branchmpc, targetmpc);
244 /* Check if the exception is an
245 ArrayIndexOutOfBoundsException. If so, move index register
249 M_MOV(er->reg, rd->argintregs[4]);
251 /* calcuate exception address */
253 M_MOV_IMM(0, rd->argintregs[3]);
255 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
257 /* move function to call into REG_ITMP3 */
259 M_MOV_IMM(er->function, REG_ITMP3);
261 if (targetdisp == 0) {
262 targetdisp = cd->mcodeptr - cd->mcodebase;
264 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
265 M_MOV(REG_SP, rd->argintregs[1]);
266 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
268 M_ASUB_IMM(2 * 8, REG_SP);
269 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
273 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
274 M_AADD_IMM(2 * 8, REG_SP);
276 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
280 M_JMP_IMM((cd->mcodebase + targetdisp) -
281 (cd->mcodeptr + PATCHER_CALL_SIZE));
288 /* emit_patcher_stubs **********************************************************
290 Generates the code for the patcher stubs.
292 *******************************************************************************/
294 __PORTED__ void emit_patcher_stubs(jitdata *jd)
305 /* get required compiler data */
309 /* generate code patching stub call code */
313 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
314 /* check code segment size */
318 /* Get machine code which is patched back in later. The
319 call is 1 instruction word long. */
321 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
323 mcode = *((u4 *) tmpmcodeptr);
325 /* Patch in the call to call the following code (done at
328 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
329 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
331 disp = (savedmcodeptr) - (tmpmcodeptr);
332 M_BSR(REG_ITMP3, disp);
334 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
336 /* create stack frame */
338 M_ASUB_IMM(6 * 4, REG_SP);
340 /* move return address onto stack */
342 M_AST(REG_ITMP3, REG_SP, 5 * 4);
344 /* move pointer to java_objectheader onto stack */
346 #if defined(ENABLE_THREADS)
347 /* create a virtual java_objectheader */
349 (void) dseg_add_unique_address(cd, NULL); /* flcword */
350 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
351 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
353 M_LDA(REG_ITMP3, REG_PV, disp);
354 M_AST(REG_ITMP3, REG_SP, 4 * 4);
359 /* move machine code onto stack */
361 disp = dseg_add_s4(cd, mcode);
362 M_ILD(REG_ITMP3, REG_PV, disp);
363 M_IST(REG_ITMP3, REG_SP, 3 * 4);
365 /* move class/method/field reference onto stack */
367 disp = dseg_add_address(cd, pref->ref);
368 M_ALD(REG_ITMP3, REG_PV, disp);
369 M_AST(REG_ITMP3, REG_SP, 2 * 4);
371 /* move data segment displacement onto stack */
373 disp = dseg_add_s4(cd, pref->disp);
374 M_ILD(REG_ITMP3, REG_PV, disp);
375 M_IST(REG_ITMP3, REG_SP, 1 * 4);
377 /* move patcher function pointer onto stack */
379 disp = dseg_add_functionptr(cd, pref->patcher);
380 M_ALD(REG_ITMP3, REG_PV, disp);
381 M_AST(REG_ITMP3, REG_SP, 0 * 4);
383 if (targetdisp == 0) {
384 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
386 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
387 M_ALD(REG_ITMP3, REG_PV, disp);
388 M_JMP(RN, REG_ITMP3);
391 disp = ((cd->mcodebase) + targetdisp) -
400 /* emit_replacement_stubs ******************************************************
402 Generates the code for the replacement stubs.
404 *******************************************************************************/
406 void emit_replacement_stubs(jitdata *jd)
415 /* get required compiler data */
420 rplp = code->rplpoints;
422 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
423 /* check code segment size */
427 /* note start of stub code */
429 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
431 /* make machine code for patching */
433 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
435 rplp->mcode = 0xe9 | ((u8) disp << 8);
437 /* push address of `rplpoint` struct */
439 M_MOV_IMM(rplp, REG_ITMP3);
442 /* jump to replacement function */
444 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
451 /* emit_verbosecall_enter ******************************************************
453 Generates the code for the call trace.
455 *******************************************************************************/
458 void emit_verbosecall_enter(jitdata *jd)
466 /* get required compiler data */
474 /* mark trace code */
478 /* additional +1 is for 16-byte stack alignment */
480 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
482 /* save argument registers */
484 for (i = 0; i < INT_ARG_CNT; i++)
485 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
487 for (i = 0; i < FLT_ARG_CNT; i++)
488 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
490 /* save temporary registers for leaf methods */
492 if (jd->isleafmethod) {
493 for (i = 0; i < INT_TMP_CNT; i++)
494 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
496 for (i = 0; i < FLT_TMP_CNT; i++)
497 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
500 /* show integer hex code for float arguments */
502 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
503 /* If the paramtype is a float, we have to right shift all
504 following integer registers. */
506 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
507 for (k = INT_ARG_CNT - 2; k >= i; k--)
508 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
510 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
515 M_MOV_IMM(m, REG_ITMP2);
516 M_AST(REG_ITMP2, REG_SP, 0 * 8);
517 M_MOV_IMM(builtin_trace_args, REG_ITMP1);
520 /* restore argument registers */
522 for (i = 0; i < INT_ARG_CNT; i++)
523 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
525 for (i = 0; i < FLT_ARG_CNT; i++)
526 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
528 /* restore temporary registers for leaf methods */
530 if (jd->isleafmethod) {
531 for (i = 0; i < INT_TMP_CNT; i++)
532 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
534 for (i = 0; i < FLT_TMP_CNT; i++)
535 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
538 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
540 /* mark trace code */
544 #endif /* !defined(NDEBUG) */
547 /* emit_verbosecall_exit *******************************************************
549 Generates the code for the call trace.
551 *******************************************************************************/
554 void emit_verbosecall_exit(jitdata *jd)
560 /* get required compiler data */
566 /* mark trace code */
570 M_ASUB_IMM(2 * 8, REG_SP);
572 M_LST(REG_RESULT, REG_SP, 0 * 8);
573 M_DST(REG_FRESULT, REG_SP, 1 * 8);
575 M_MOV_IMM(m, rd->argintregs[0]);
576 M_MOV(REG_RESULT, rd->argintregs[1]);
577 M_FLTMOVE(REG_FRESULT, rd->argfltregs[0]);
578 M_FLTMOVE(REG_FRESULT, rd->argfltregs[1]);
580 M_MOV_IMM(builtin_displaymethodstop, REG_ITMP1);
583 M_LLD(REG_RESULT, REG_SP, 0 * 8);
584 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
586 M_AADD_IMM(2 * 8, REG_SP);
588 /* mark trace code */
592 #endif /* !defined(NDEBUG) */
595 /* code generation functions **************************************************/
597 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
599 if ((basereg == REG_SP) || (basereg == R12)) {
601 emit_address_byte(0, dreg, REG_SP);
602 emit_address_byte(0, REG_SP, REG_SP);
604 } else if (IS_IMM8(disp)) {
605 emit_address_byte(1, dreg, REG_SP);
606 emit_address_byte(0, REG_SP, REG_SP);
610 emit_address_byte(2, dreg, REG_SP);
611 emit_address_byte(0, REG_SP, REG_SP);
615 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
616 emit_address_byte(0,(dreg),(basereg));
618 } else if ((basereg) == RIP) {
619 emit_address_byte(0, dreg, RBP);
624 emit_address_byte(1, dreg, basereg);
628 emit_address_byte(2, dreg, basereg);
635 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
637 if ((basereg == REG_SP) || (basereg == R12)) {
638 emit_address_byte(2, dreg, REG_SP);
639 emit_address_byte(0, REG_SP, REG_SP);
643 emit_address_byte(2, dreg, basereg);
649 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
652 emit_address_byte(0, reg, 4);
653 emit_address_byte(scale, indexreg, 5);
656 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
657 emit_address_byte(0, reg, 4);
658 emit_address_byte(scale, indexreg, basereg);
660 else if (IS_IMM8(disp)) {
661 emit_address_byte(1, reg, 4);
662 emit_address_byte(scale, indexreg, basereg);
666 emit_address_byte(2, reg, 4);
667 emit_address_byte(scale, indexreg, basereg);
673 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
676 varinfo *v_s1,*v_s2,*v_dst;
679 /* get required compiler data */
683 v_s1 = VAROP(iptr->s1);
684 v_s2 = VAROP(iptr->sx.s23.s2);
685 v_dst = VAROP(iptr->dst);
687 s1 = v_s1->vv.regoff;
688 s2 = v_s2->vv.regoff;
689 d = v_dst->vv.regoff;
691 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
693 if (IS_INMEMORY(v_dst->flags)) {
694 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
696 M_ILD(RCX, REG_SP, s2 * 8);
697 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
700 M_ILD(RCX, REG_SP, s2 * 8);
701 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
702 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
703 M_IST(REG_ITMP2, REG_SP, d * 8);
706 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
707 /* s1 may be equal to RCX */
710 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
711 M_IST(s1, REG_SP, d * 8);
712 M_INTMOVE(REG_ITMP1, RCX);
715 M_IST(s1, REG_SP, d * 8);
716 M_ILD(RCX, REG_SP, s2 * 8);
720 M_ILD(RCX, REG_SP, s2 * 8);
721 M_IST(s1, REG_SP, d * 8);
724 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
726 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
729 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
733 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
734 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
735 M_IST(REG_ITMP2, REG_SP, d * 8);
739 /* s1 may be equal to RCX */
740 M_IST(s1, REG_SP, d * 8);
742 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
745 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
753 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
754 M_ILD(RCX, REG_SP, s2 * 8);
755 M_ILD(d, REG_SP, s1 * 8);
756 emit_shiftl_reg(cd, shift_op, d);
758 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
759 /* s1 may be equal to RCX */
761 M_ILD(RCX, REG_SP, s2 * 8);
762 emit_shiftl_reg(cd, shift_op, d);
764 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
766 M_ILD(d, REG_SP, s1 * 8);
767 emit_shiftl_reg(cd, shift_op, d);
770 /* s1 may be equal to RCX */
773 /* d cannot be used to backup s1 since this would
775 M_INTMOVE(s1, REG_ITMP3);
777 M_INTMOVE(REG_ITMP3, d);
785 /* d may be equal to s2 */
789 emit_shiftl_reg(cd, shift_op, d);
793 M_INTMOVE(REG_ITMP3, RCX);
795 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
800 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
803 varinfo *v_s1,*v_s2,*v_dst;
806 /* get required compiler data */
810 v_s1 = VAROP(iptr->s1);
811 v_s2 = VAROP(iptr->sx.s23.s2);
812 v_dst = VAROP(iptr->dst);
814 s1 = v_s1->vv.regoff;
815 s2 = v_s2->vv.regoff;
816 d = v_dst->vv.regoff;
818 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
820 if (IS_INMEMORY(v_dst->flags)) {
821 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
823 M_ILD(RCX, REG_SP, s2 * 8);
824 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
827 M_ILD(RCX, REG_SP, s2 * 8);
828 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
829 emit_shift_reg(cd, shift_op, REG_ITMP2);
830 M_LST(REG_ITMP2, REG_SP, d * 8);
833 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
834 /* s1 may be equal to RCX */
837 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
838 M_LST(s1, REG_SP, d * 8);
839 M_INTMOVE(REG_ITMP1, RCX);
842 M_LST(s1, REG_SP, d * 8);
843 M_ILD(RCX, REG_SP, s2 * 8);
847 M_ILD(RCX, REG_SP, s2 * 8);
848 M_LST(s1, REG_SP, d * 8);
851 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
853 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
856 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
860 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
861 emit_shift_reg(cd, shift_op, REG_ITMP2);
862 M_LST(REG_ITMP2, REG_SP, d * 8);
866 /* s1 may be equal to RCX */
867 M_LST(s1, REG_SP, d * 8);
869 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
872 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
880 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
881 M_ILD(RCX, REG_SP, s2 * 8);
882 M_LLD(d, REG_SP, s1 * 8);
883 emit_shift_reg(cd, shift_op, d);
885 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
886 /* s1 may be equal to RCX */
888 M_ILD(RCX, REG_SP, s2 * 8);
889 emit_shift_reg(cd, shift_op, d);
891 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
893 M_LLD(d, REG_SP, s1 * 8);
894 emit_shift_reg(cd, shift_op, d);
897 /* s1 may be equal to RCX */
900 /* d cannot be used to backup s1 since this would
902 M_INTMOVE(s1, REG_ITMP3);
904 M_INTMOVE(REG_ITMP3, d);
912 /* d may be equal to s2 */
916 emit_shift_reg(cd, shift_op, d);
920 M_INTMOVE(REG_ITMP3, RCX);
922 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
927 /* low-level code emitter functions *******************************************/
929 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
931 emit_rex(1,(reg),0,(dreg));
932 *(cd->mcodeptr++) = 0x89;
933 emit_reg((reg),(dreg));
937 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
939 emit_rex(1,0,0,(reg));
940 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
945 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
947 emit_rex(0,(reg),0,(dreg));
948 *(cd->mcodeptr++) = 0x89;
949 emit_reg((reg),(dreg));
953 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
954 emit_rex(0,0,0,(reg));
955 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
960 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
961 emit_rex(1,(reg),0,(basereg));
962 *(cd->mcodeptr++) = 0x8b;
963 emit_membase(cd, (basereg),(disp),(reg));
968 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
969 * constant membase immediate length of 32bit
971 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
972 emit_rex(1,(reg),0,(basereg));
973 *(cd->mcodeptr++) = 0x8b;
974 emit_membase32(cd, (basereg),(disp),(reg));
978 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
980 emit_rex(0,(reg),0,(basereg));
981 *(cd->mcodeptr++) = 0x8b;
982 emit_membase(cd, (basereg),(disp),(reg));
986 /* ATTENTION: Always emit a REX byte, because the instruction size can
987 be smaller when all register indexes are smaller than 7. */
988 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
990 emit_byte_rex((reg),0,(basereg));
991 *(cd->mcodeptr++) = 0x8b;
992 emit_membase32(cd, (basereg),(disp),(reg));
996 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
997 emit_rex(1,(reg),0,(basereg));
998 *(cd->mcodeptr++) = 0x89;
999 emit_membase(cd, (basereg),(disp),(reg));
1003 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1004 emit_rex(1,(reg),0,(basereg));
1005 *(cd->mcodeptr++) = 0x89;
1006 emit_membase32(cd, (basereg),(disp),(reg));
1010 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1011 emit_rex(0,(reg),0,(basereg));
1012 *(cd->mcodeptr++) = 0x89;
1013 emit_membase(cd, (basereg),(disp),(reg));
1017 /* Always emit a REX byte, because the instruction size can be smaller when */
1018 /* all register indexes are smaller than 7. */
1019 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1020 emit_byte_rex((reg),0,(basereg));
1021 *(cd->mcodeptr++) = 0x89;
1022 emit_membase32(cd, (basereg),(disp),(reg));
1026 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1027 emit_rex(1,(reg),(indexreg),(basereg));
1028 *(cd->mcodeptr++) = 0x8b;
1029 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1033 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1034 emit_rex(0,(reg),(indexreg),(basereg));
1035 *(cd->mcodeptr++) = 0x8b;
1036 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1040 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1041 emit_rex(1,(reg),(indexreg),(basereg));
1042 *(cd->mcodeptr++) = 0x89;
1043 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1047 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1048 emit_rex(0,(reg),(indexreg),(basereg));
1049 *(cd->mcodeptr++) = 0x89;
1050 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1054 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1055 *(cd->mcodeptr++) = 0x66;
1056 emit_rex(0,(reg),(indexreg),(basereg));
1057 *(cd->mcodeptr++) = 0x89;
1058 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1062 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1063 emit_byte_rex((reg),(indexreg),(basereg));
1064 *(cd->mcodeptr++) = 0x88;
1065 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1069 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1070 emit_rex(1,0,0,(basereg));
1071 *(cd->mcodeptr++) = 0xc7;
1072 emit_membase(cd, (basereg),(disp),0);
1077 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1078 emit_rex(1,0,0,(basereg));
1079 *(cd->mcodeptr++) = 0xc7;
1080 emit_membase32(cd, (basereg),(disp),0);
1085 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1086 emit_rex(0,0,0,(basereg));
1087 *(cd->mcodeptr++) = 0xc7;
1088 emit_membase(cd, (basereg),(disp),0);
1093 /* Always emit a REX byte, because the instruction size can be smaller when */
1094 /* all register indexes are smaller than 7. */
1095 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1096 emit_byte_rex(0,0,(basereg));
1097 *(cd->mcodeptr++) = 0xc7;
1098 emit_membase32(cd, (basereg),(disp),0);
1103 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1105 emit_rex(1,(dreg),0,(reg));
1106 *(cd->mcodeptr++) = 0x0f;
1107 *(cd->mcodeptr++) = 0xbe;
1108 /* XXX: why do reg and dreg have to be exchanged */
1109 emit_reg((dreg),(reg));
1113 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1115 emit_rex(1,(dreg),0,(reg));
1116 *(cd->mcodeptr++) = 0x0f;
1117 *(cd->mcodeptr++) = 0xbf;
1118 /* XXX: why do reg and dreg have to be exchanged */
1119 emit_reg((dreg),(reg));
1123 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1125 emit_rex(1,(dreg),0,(reg));
1126 *(cd->mcodeptr++) = 0x63;
1127 /* XXX: why do reg and dreg have to be exchanged */
1128 emit_reg((dreg),(reg));
1132 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1134 emit_rex(1,(dreg),0,(reg));
1135 *(cd->mcodeptr++) = 0x0f;
1136 *(cd->mcodeptr++) = 0xb7;
1137 /* XXX: why do reg and dreg have to be exchanged */
1138 emit_reg((dreg),(reg));
1142 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1143 emit_rex(1,(reg),(indexreg),(basereg));
1144 *(cd->mcodeptr++) = 0x0f;
1145 *(cd->mcodeptr++) = 0xbf;
1146 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1150 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1151 emit_rex(1,(reg),(indexreg),(basereg));
1152 *(cd->mcodeptr++) = 0x0f;
1153 *(cd->mcodeptr++) = 0xbe;
1154 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1158 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1159 emit_rex(1,(reg),(indexreg),(basereg));
1160 *(cd->mcodeptr++) = 0x0f;
1161 *(cd->mcodeptr++) = 0xb7;
1162 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1166 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1168 emit_rex(1,0,(indexreg),(basereg));
1169 *(cd->mcodeptr++) = 0xc7;
1170 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1175 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1177 emit_rex(0,0,(indexreg),(basereg));
1178 *(cd->mcodeptr++) = 0xc7;
1179 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1184 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1186 *(cd->mcodeptr++) = 0x66;
1187 emit_rex(0,0,(indexreg),(basereg));
1188 *(cd->mcodeptr++) = 0xc7;
1189 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1194 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1196 emit_rex(0,0,(indexreg),(basereg));
1197 *(cd->mcodeptr++) = 0xc6;
1198 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1206 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1208 emit_rex(1,(reg),0,(dreg));
1209 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1210 emit_reg((reg),(dreg));
1214 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1216 emit_rex(0,(reg),0,(dreg));
1217 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1218 emit_reg((reg),(dreg));
1222 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1224 emit_rex(1,(reg),0,(basereg));
1225 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1226 emit_membase(cd, (basereg),(disp),(reg));
1230 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1232 emit_rex(0,(reg),0,(basereg));
1233 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1234 emit_membase(cd, (basereg),(disp),(reg));
1238 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1240 emit_rex(1,(reg),0,(basereg));
1241 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1242 emit_membase(cd, (basereg),(disp),(reg));
1246 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1248 emit_rex(0,(reg),0,(basereg));
1249 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1250 emit_membase(cd, (basereg),(disp),(reg));
1254 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1256 emit_rex(1,0,0,(dreg));
1257 *(cd->mcodeptr++) = 0x83;
1258 emit_reg((opc),(dreg));
1261 emit_rex(1,0,0,(dreg));
1262 *(cd->mcodeptr++) = 0x81;
1263 emit_reg((opc),(dreg));
1269 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1270 emit_rex(1,0,0,(dreg));
1271 *(cd->mcodeptr++) = 0x81;
1272 emit_reg((opc),(dreg));
1277 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1279 emit_rex(0,0,0,(dreg));
1280 *(cd->mcodeptr++) = 0x83;
1281 emit_reg((opc),(dreg));
1284 emit_rex(0,0,0,(dreg));
1285 *(cd->mcodeptr++) = 0x81;
1286 emit_reg((opc),(dreg));
1292 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1294 emit_rex(1,(basereg),0,0);
1295 *(cd->mcodeptr++) = 0x83;
1296 emit_membase(cd, (basereg),(disp),(opc));
1299 emit_rex(1,(basereg),0,0);
1300 *(cd->mcodeptr++) = 0x81;
1301 emit_membase(cd, (basereg),(disp),(opc));
1307 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1309 emit_rex(0,(basereg),0,0);
1310 *(cd->mcodeptr++) = 0x83;
1311 emit_membase(cd, (basereg),(disp),(opc));
1314 emit_rex(0,(basereg),0,0);
1315 *(cd->mcodeptr++) = 0x81;
1316 emit_membase(cd, (basereg),(disp),(opc));
1322 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1323 emit_rex(1,(reg),0,(dreg));
1324 *(cd->mcodeptr++) = 0x85;
1325 emit_reg((reg),(dreg));
1329 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1330 emit_rex(0,(reg),0,(dreg));
1331 *(cd->mcodeptr++) = 0x85;
1332 emit_reg((reg),(dreg));
1336 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1337 *(cd->mcodeptr++) = 0xf7;
1343 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1344 *(cd->mcodeptr++) = 0x66;
1345 *(cd->mcodeptr++) = 0xf7;
1351 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1352 *(cd->mcodeptr++) = 0xf6;
1358 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1359 emit_rex(1,(reg),0,(basereg));
1360 *(cd->mcodeptr++) = 0x8d;
1361 emit_membase(cd, (basereg),(disp),(reg));
1365 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1366 emit_rex(0,(reg),0,(basereg));
1367 *(cd->mcodeptr++) = 0x8d;
1368 emit_membase(cd, (basereg),(disp),(reg));
1373 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1375 emit_rex(0,0,0,(basereg));
1376 *(cd->mcodeptr++) = 0xff;
1377 emit_membase(cd, (basereg),(disp),0);
1382 void emit_cltd(codegendata *cd) {
1383 *(cd->mcodeptr++) = 0x99;
1387 void emit_cqto(codegendata *cd) {
1389 *(cd->mcodeptr++) = 0x99;
1394 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1395 emit_rex(1,(dreg),0,(reg));
1396 *(cd->mcodeptr++) = 0x0f;
1397 *(cd->mcodeptr++) = 0xaf;
1398 emit_reg((dreg),(reg));
1402 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1403 emit_rex(0,(dreg),0,(reg));
1404 *(cd->mcodeptr++) = 0x0f;
1405 *(cd->mcodeptr++) = 0xaf;
1406 emit_reg((dreg),(reg));
1410 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1411 emit_rex(1,(dreg),0,(basereg));
1412 *(cd->mcodeptr++) = 0x0f;
1413 *(cd->mcodeptr++) = 0xaf;
1414 emit_membase(cd, (basereg),(disp),(dreg));
1418 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1419 emit_rex(0,(dreg),0,(basereg));
1420 *(cd->mcodeptr++) = 0x0f;
1421 *(cd->mcodeptr++) = 0xaf;
1422 emit_membase(cd, (basereg),(disp),(dreg));
1426 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1427 if (IS_IMM8((imm))) {
1428 emit_rex(1,0,0,(dreg));
1429 *(cd->mcodeptr++) = 0x6b;
1433 emit_rex(1,0,0,(dreg));
1434 *(cd->mcodeptr++) = 0x69;
1441 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1442 if (IS_IMM8((imm))) {
1443 emit_rex(1,(dreg),0,(reg));
1444 *(cd->mcodeptr++) = 0x6b;
1445 emit_reg((dreg),(reg));
1448 emit_rex(1,(dreg),0,(reg));
1449 *(cd->mcodeptr++) = 0x69;
1450 emit_reg((dreg),(reg));
1456 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1457 if (IS_IMM8((imm))) {
1458 emit_rex(0,(dreg),0,(reg));
1459 *(cd->mcodeptr++) = 0x6b;
1460 emit_reg((dreg),(reg));
1463 emit_rex(0,(dreg),0,(reg));
1464 *(cd->mcodeptr++) = 0x69;
1465 emit_reg((dreg),(reg));
1471 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1472 if (IS_IMM8((imm))) {
1473 emit_rex(1,(dreg),0,(basereg));
1474 *(cd->mcodeptr++) = 0x6b;
1475 emit_membase(cd, (basereg),(disp),(dreg));
1478 emit_rex(1,(dreg),0,(basereg));
1479 *(cd->mcodeptr++) = 0x69;
1480 emit_membase(cd, (basereg),(disp),(dreg));
1486 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1487 if (IS_IMM8((imm))) {
1488 emit_rex(0,(dreg),0,(basereg));
1489 *(cd->mcodeptr++) = 0x6b;
1490 emit_membase(cd, (basereg),(disp),(dreg));
1493 emit_rex(0,(dreg),0,(basereg));
1494 *(cd->mcodeptr++) = 0x69;
1495 emit_membase(cd, (basereg),(disp),(dreg));
1501 void emit_idiv_reg(codegendata *cd, s8 reg) {
1502 emit_rex(1,0,0,(reg));
1503 *(cd->mcodeptr++) = 0xf7;
1508 void emit_idivl_reg(codegendata *cd, s8 reg) {
1509 emit_rex(0,0,0,(reg));
1510 *(cd->mcodeptr++) = 0xf7;
1516 void emit_ret(codegendata *cd) {
1517 *(cd->mcodeptr++) = 0xc3;
1525 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1526 emit_rex(1,0,0,(reg));
1527 *(cd->mcodeptr++) = 0xd3;
1528 emit_reg((opc),(reg));
1532 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1533 emit_rex(0,0,0,(reg));
1534 *(cd->mcodeptr++) = 0xd3;
1535 emit_reg((opc),(reg));
1539 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1540 emit_rex(1,0,0,(basereg));
1541 *(cd->mcodeptr++) = 0xd3;
1542 emit_membase(cd, (basereg),(disp),(opc));
1546 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1547 emit_rex(0,0,0,(basereg));
1548 *(cd->mcodeptr++) = 0xd3;
1549 emit_membase(cd, (basereg),(disp),(opc));
1553 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1555 emit_rex(1,0,0,(dreg));
1556 *(cd->mcodeptr++) = 0xd1;
1557 emit_reg((opc),(dreg));
1559 emit_rex(1,0,0,(dreg));
1560 *(cd->mcodeptr++) = 0xc1;
1561 emit_reg((opc),(dreg));
1567 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1569 emit_rex(0,0,0,(dreg));
1570 *(cd->mcodeptr++) = 0xd1;
1571 emit_reg((opc),(dreg));
1573 emit_rex(0,0,0,(dreg));
1574 *(cd->mcodeptr++) = 0xc1;
1575 emit_reg((opc),(dreg));
1581 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1583 emit_rex(1,0,0,(basereg));
1584 *(cd->mcodeptr++) = 0xd1;
1585 emit_membase(cd, (basereg),(disp),(opc));
1587 emit_rex(1,0,0,(basereg));
1588 *(cd->mcodeptr++) = 0xc1;
1589 emit_membase(cd, (basereg),(disp),(opc));
1595 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1597 emit_rex(0,0,0,(basereg));
1598 *(cd->mcodeptr++) = 0xd1;
1599 emit_membase(cd, (basereg),(disp),(opc));
1601 emit_rex(0,0,0,(basereg));
1602 *(cd->mcodeptr++) = 0xc1;
1603 emit_membase(cd, (basereg),(disp),(opc));
1613 void emit_jmp_imm(codegendata *cd, s8 imm) {
1614 *(cd->mcodeptr++) = 0xe9;
1619 void emit_jmp_reg(codegendata *cd, s8 reg) {
1620 emit_rex(0,0,0,(reg));
1621 *(cd->mcodeptr++) = 0xff;
1626 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1627 *(cd->mcodeptr++) = 0x0f;
1628 *(cd->mcodeptr++) = (0x80 + (opc));
1635 * conditional set and move operations
1638 /* we need the rex byte to get all low bytes */
1639 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1640 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1641 *(cd->mcodeptr++) = 0x0f;
1642 *(cd->mcodeptr++) = (0x90 + (opc));
1647 /* we need the rex byte to get all low bytes */
1648 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1649 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1650 *(cd->mcodeptr++) = 0x0f;
1651 *(cd->mcodeptr++) = (0x90 + (opc));
1652 emit_membase(cd, (basereg),(disp),0);
1656 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1658 emit_rex(1,(dreg),0,(reg));
1659 *(cd->mcodeptr++) = 0x0f;
1660 *(cd->mcodeptr++) = (0x40 + (opc));
1661 emit_reg((dreg),(reg));
1665 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1667 emit_rex(0,(dreg),0,(reg));
1668 *(cd->mcodeptr++) = 0x0f;
1669 *(cd->mcodeptr++) = (0x40 + (opc));
1670 emit_reg((dreg),(reg));
1675 void emit_neg_reg(codegendata *cd, s8 reg)
1677 emit_rex(1,0,0,(reg));
1678 *(cd->mcodeptr++) = 0xf7;
1683 void emit_negl_reg(codegendata *cd, s8 reg)
1685 emit_rex(0,0,0,(reg));
1686 *(cd->mcodeptr++) = 0xf7;
1691 void emit_push_reg(codegendata *cd, s8 reg) {
1692 emit_rex(0,0,0,(reg));
1693 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1697 void emit_push_imm(codegendata *cd, s8 imm) {
1698 *(cd->mcodeptr++) = 0x68;
1703 void emit_pop_reg(codegendata *cd, s8 reg) {
1704 emit_rex(0,0,0,(reg));
1705 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1709 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1710 emit_rex(1,(reg),0,(dreg));
1711 *(cd->mcodeptr++) = 0x87;
1712 emit_reg((reg),(dreg));
1716 void emit_nop(codegendata *cd) {
1717 *(cd->mcodeptr++) = 0x90;
1725 void emit_call_reg(codegendata *cd, s8 reg) {
1726 emit_rex(1,0,0,(reg));
1727 *(cd->mcodeptr++) = 0xff;
1732 void emit_call_imm(codegendata *cd, s8 imm) {
1733 *(cd->mcodeptr++) = 0xe8;
1738 void emit_call_mem(codegendata *cd, ptrint mem)
1740 *(cd->mcodeptr++) = 0xff;
1747 * floating point instructions (SSE2)
1749 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1750 *(cd->mcodeptr++) = 0xf2;
1751 emit_rex(0,(dreg),0,(reg));
1752 *(cd->mcodeptr++) = 0x0f;
1753 *(cd->mcodeptr++) = 0x58;
1754 emit_reg((dreg),(reg));
1758 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1759 *(cd->mcodeptr++) = 0xf3;
1760 emit_rex(0,(dreg),0,(reg));
1761 *(cd->mcodeptr++) = 0x0f;
1762 *(cd->mcodeptr++) = 0x58;
1763 emit_reg((dreg),(reg));
1767 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1768 *(cd->mcodeptr++) = 0xf3;
1769 emit_rex(1,(dreg),0,(reg));
1770 *(cd->mcodeptr++) = 0x0f;
1771 *(cd->mcodeptr++) = 0x2a;
1772 emit_reg((dreg),(reg));
1776 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1777 *(cd->mcodeptr++) = 0xf3;
1778 emit_rex(0,(dreg),0,(reg));
1779 *(cd->mcodeptr++) = 0x0f;
1780 *(cd->mcodeptr++) = 0x2a;
1781 emit_reg((dreg),(reg));
1785 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1786 *(cd->mcodeptr++) = 0xf2;
1787 emit_rex(1,(dreg),0,(reg));
1788 *(cd->mcodeptr++) = 0x0f;
1789 *(cd->mcodeptr++) = 0x2a;
1790 emit_reg((dreg),(reg));
1794 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1795 *(cd->mcodeptr++) = 0xf2;
1796 emit_rex(0,(dreg),0,(reg));
1797 *(cd->mcodeptr++) = 0x0f;
1798 *(cd->mcodeptr++) = 0x2a;
1799 emit_reg((dreg),(reg));
1803 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1804 *(cd->mcodeptr++) = 0xf3;
1805 emit_rex(0,(dreg),0,(reg));
1806 *(cd->mcodeptr++) = 0x0f;
1807 *(cd->mcodeptr++) = 0x5a;
1808 emit_reg((dreg),(reg));
1812 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1813 *(cd->mcodeptr++) = 0xf2;
1814 emit_rex(0,(dreg),0,(reg));
1815 *(cd->mcodeptr++) = 0x0f;
1816 *(cd->mcodeptr++) = 0x5a;
1817 emit_reg((dreg),(reg));
1821 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1822 *(cd->mcodeptr++) = 0xf3;
1823 emit_rex(1,(dreg),0,(reg));
1824 *(cd->mcodeptr++) = 0x0f;
1825 *(cd->mcodeptr++) = 0x2c;
1826 emit_reg((dreg),(reg));
1830 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1831 *(cd->mcodeptr++) = 0xf3;
1832 emit_rex(0,(dreg),0,(reg));
1833 *(cd->mcodeptr++) = 0x0f;
1834 *(cd->mcodeptr++) = 0x2c;
1835 emit_reg((dreg),(reg));
1839 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1840 *(cd->mcodeptr++) = 0xf2;
1841 emit_rex(1,(dreg),0,(reg));
1842 *(cd->mcodeptr++) = 0x0f;
1843 *(cd->mcodeptr++) = 0x2c;
1844 emit_reg((dreg),(reg));
1848 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1849 *(cd->mcodeptr++) = 0xf2;
1850 emit_rex(0,(dreg),0,(reg));
1851 *(cd->mcodeptr++) = 0x0f;
1852 *(cd->mcodeptr++) = 0x2c;
1853 emit_reg((dreg),(reg));
1857 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1858 *(cd->mcodeptr++) = 0xf3;
1859 emit_rex(0,(dreg),0,(reg));
1860 *(cd->mcodeptr++) = 0x0f;
1861 *(cd->mcodeptr++) = 0x5e;
1862 emit_reg((dreg),(reg));
1866 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1867 *(cd->mcodeptr++) = 0xf2;
1868 emit_rex(0,(dreg),0,(reg));
1869 *(cd->mcodeptr++) = 0x0f;
1870 *(cd->mcodeptr++) = 0x5e;
1871 emit_reg((dreg),(reg));
1875 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1876 *(cd->mcodeptr++) = 0x66;
1877 emit_rex(1,(freg),0,(reg));
1878 *(cd->mcodeptr++) = 0x0f;
1879 *(cd->mcodeptr++) = 0x6e;
1880 emit_reg((freg),(reg));
1884 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1885 *(cd->mcodeptr++) = 0x66;
1886 emit_rex(1,(freg),0,(reg));
1887 *(cd->mcodeptr++) = 0x0f;
1888 *(cd->mcodeptr++) = 0x7e;
1889 emit_reg((freg),(reg));
1893 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1894 *(cd->mcodeptr++) = 0x66;
1895 emit_rex(0,(reg),0,(basereg));
1896 *(cd->mcodeptr++) = 0x0f;
1897 *(cd->mcodeptr++) = 0x7e;
1898 emit_membase(cd, (basereg),(disp),(reg));
1902 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1903 *(cd->mcodeptr++) = 0x66;
1904 emit_rex(0,(reg),(indexreg),(basereg));
1905 *(cd->mcodeptr++) = 0x0f;
1906 *(cd->mcodeptr++) = 0x7e;
1907 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1911 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1912 *(cd->mcodeptr++) = 0x66;
1913 emit_rex(1,(dreg),0,(basereg));
1914 *(cd->mcodeptr++) = 0x0f;
1915 *(cd->mcodeptr++) = 0x6e;
1916 emit_membase(cd, (basereg),(disp),(dreg));
1920 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1921 *(cd->mcodeptr++) = 0x66;
1922 emit_rex(0,(dreg),0,(basereg));
1923 *(cd->mcodeptr++) = 0x0f;
1924 *(cd->mcodeptr++) = 0x6e;
1925 emit_membase(cd, (basereg),(disp),(dreg));
1929 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1930 *(cd->mcodeptr++) = 0x66;
1931 emit_rex(0,(dreg),(indexreg),(basereg));
1932 *(cd->mcodeptr++) = 0x0f;
1933 *(cd->mcodeptr++) = 0x6e;
1934 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
1938 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1939 *(cd->mcodeptr++) = 0xf3;
1940 emit_rex(0,(dreg),0,(reg));
1941 *(cd->mcodeptr++) = 0x0f;
1942 *(cd->mcodeptr++) = 0x7e;
1943 emit_reg((dreg),(reg));
1947 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1948 *(cd->mcodeptr++) = 0x66;
1949 emit_rex(0,(reg),0,(basereg));
1950 *(cd->mcodeptr++) = 0x0f;
1951 *(cd->mcodeptr++) = 0xd6;
1952 emit_membase(cd, (basereg),(disp),(reg));
1956 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1957 *(cd->mcodeptr++) = 0xf3;
1958 emit_rex(0,(dreg),0,(basereg));
1959 *(cd->mcodeptr++) = 0x0f;
1960 *(cd->mcodeptr++) = 0x7e;
1961 emit_membase(cd, (basereg),(disp),(dreg));
1965 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1966 *(cd->mcodeptr++) = 0xf3;
1967 emit_rex(0,(reg),0,(dreg));
1968 *(cd->mcodeptr++) = 0x0f;
1969 *(cd->mcodeptr++) = 0x10;
1970 emit_reg((reg),(dreg));
1974 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1975 *(cd->mcodeptr++) = 0xf2;
1976 emit_rex(0,(reg),0,(dreg));
1977 *(cd->mcodeptr++) = 0x0f;
1978 *(cd->mcodeptr++) = 0x10;
1979 emit_reg((reg),(dreg));
1983 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1984 *(cd->mcodeptr++) = 0xf3;
1985 emit_rex(0,(reg),0,(basereg));
1986 *(cd->mcodeptr++) = 0x0f;
1987 *(cd->mcodeptr++) = 0x11;
1988 emit_membase(cd, (basereg),(disp),(reg));
1992 /* Always emit a REX byte, because the instruction size can be smaller when */
1993 /* all register indexes are smaller than 7. */
1994 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1995 *(cd->mcodeptr++) = 0xf3;
1996 emit_byte_rex((reg),0,(basereg));
1997 *(cd->mcodeptr++) = 0x0f;
1998 *(cd->mcodeptr++) = 0x11;
1999 emit_membase32(cd, (basereg),(disp),(reg));
2003 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2004 *(cd->mcodeptr++) = 0xf2;
2005 emit_rex(0,(reg),0,(basereg));
2006 *(cd->mcodeptr++) = 0x0f;
2007 *(cd->mcodeptr++) = 0x11;
2008 emit_membase(cd, (basereg),(disp),(reg));
2012 /* Always emit a REX byte, because the instruction size can be smaller when */
2013 /* all register indexes are smaller than 7. */
2014 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2015 *(cd->mcodeptr++) = 0xf2;
2016 emit_byte_rex((reg),0,(basereg));
2017 *(cd->mcodeptr++) = 0x0f;
2018 *(cd->mcodeptr++) = 0x11;
2019 emit_membase32(cd, (basereg),(disp),(reg));
2023 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2024 *(cd->mcodeptr++) = 0xf3;
2025 emit_rex(0,(dreg),0,(basereg));
2026 *(cd->mcodeptr++) = 0x0f;
2027 *(cd->mcodeptr++) = 0x10;
2028 emit_membase(cd, (basereg),(disp),(dreg));
2032 /* Always emit a REX byte, because the instruction size can be smaller when */
2033 /* all register indexes are smaller than 7. */
2034 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2035 *(cd->mcodeptr++) = 0xf3;
2036 emit_byte_rex((dreg),0,(basereg));
2037 *(cd->mcodeptr++) = 0x0f;
2038 *(cd->mcodeptr++) = 0x10;
2039 emit_membase32(cd, (basereg),(disp),(dreg));
2043 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2045 emit_rex(0,(dreg),0,(basereg));
2046 *(cd->mcodeptr++) = 0x0f;
2047 *(cd->mcodeptr++) = 0x12;
2048 emit_membase(cd, (basereg),(disp),(dreg));
2052 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2054 emit_rex(0,(reg),0,(basereg));
2055 *(cd->mcodeptr++) = 0x0f;
2056 *(cd->mcodeptr++) = 0x13;
2057 emit_membase(cd, (basereg),(disp),(reg));
2061 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2062 *(cd->mcodeptr++) = 0xf2;
2063 emit_rex(0,(dreg),0,(basereg));
2064 *(cd->mcodeptr++) = 0x0f;
2065 *(cd->mcodeptr++) = 0x10;
2066 emit_membase(cd, (basereg),(disp),(dreg));
2070 /* Always emit a REX byte, because the instruction size can be smaller when */
2071 /* all register indexes are smaller than 7. */
2072 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2073 *(cd->mcodeptr++) = 0xf2;
2074 emit_byte_rex((dreg),0,(basereg));
2075 *(cd->mcodeptr++) = 0x0f;
2076 *(cd->mcodeptr++) = 0x10;
2077 emit_membase32(cd, (basereg),(disp),(dreg));
2081 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2083 *(cd->mcodeptr++) = 0x66;
2084 emit_rex(0,(dreg),0,(basereg));
2085 *(cd->mcodeptr++) = 0x0f;
2086 *(cd->mcodeptr++) = 0x12;
2087 emit_membase(cd, (basereg),(disp),(dreg));
2091 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2093 *(cd->mcodeptr++) = 0x66;
2094 emit_rex(0,(reg),0,(basereg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = 0x13;
2097 emit_membase(cd, (basereg),(disp),(reg));
2101 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2102 *(cd->mcodeptr++) = 0xf3;
2103 emit_rex(0,(reg),(indexreg),(basereg));
2104 *(cd->mcodeptr++) = 0x0f;
2105 *(cd->mcodeptr++) = 0x11;
2106 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2110 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2111 *(cd->mcodeptr++) = 0xf2;
2112 emit_rex(0,(reg),(indexreg),(basereg));
2113 *(cd->mcodeptr++) = 0x0f;
2114 *(cd->mcodeptr++) = 0x11;
2115 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2119 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2120 *(cd->mcodeptr++) = 0xf3;
2121 emit_rex(0,(dreg),(indexreg),(basereg));
2122 *(cd->mcodeptr++) = 0x0f;
2123 *(cd->mcodeptr++) = 0x10;
2124 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2128 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2129 *(cd->mcodeptr++) = 0xf2;
2130 emit_rex(0,(dreg),(indexreg),(basereg));
2131 *(cd->mcodeptr++) = 0x0f;
2132 *(cd->mcodeptr++) = 0x10;
2133 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2137 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2138 *(cd->mcodeptr++) = 0xf3;
2139 emit_rex(0,(dreg),0,(reg));
2140 *(cd->mcodeptr++) = 0x0f;
2141 *(cd->mcodeptr++) = 0x59;
2142 emit_reg((dreg),(reg));
2146 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2147 *(cd->mcodeptr++) = 0xf2;
2148 emit_rex(0,(dreg),0,(reg));
2149 *(cd->mcodeptr++) = 0x0f;
2150 *(cd->mcodeptr++) = 0x59;
2151 emit_reg((dreg),(reg));
2155 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2156 *(cd->mcodeptr++) = 0xf3;
2157 emit_rex(0,(dreg),0,(reg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x5c;
2160 emit_reg((dreg),(reg));
2164 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2165 *(cd->mcodeptr++) = 0xf2;
2166 emit_rex(0,(dreg),0,(reg));
2167 *(cd->mcodeptr++) = 0x0f;
2168 *(cd->mcodeptr++) = 0x5c;
2169 emit_reg((dreg),(reg));
2173 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2174 emit_rex(0,(dreg),0,(reg));
2175 *(cd->mcodeptr++) = 0x0f;
2176 *(cd->mcodeptr++) = 0x2e;
2177 emit_reg((dreg),(reg));
2181 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2182 *(cd->mcodeptr++) = 0x66;
2183 emit_rex(0,(dreg),0,(reg));
2184 *(cd->mcodeptr++) = 0x0f;
2185 *(cd->mcodeptr++) = 0x2e;
2186 emit_reg((dreg),(reg));
2190 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2191 emit_rex(0,(dreg),0,(reg));
2192 *(cd->mcodeptr++) = 0x0f;
2193 *(cd->mcodeptr++) = 0x57;
2194 emit_reg((dreg),(reg));
2198 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2199 emit_rex(0,(dreg),0,(basereg));
2200 *(cd->mcodeptr++) = 0x0f;
2201 *(cd->mcodeptr++) = 0x57;
2202 emit_membase(cd, (basereg),(disp),(dreg));
2206 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2207 *(cd->mcodeptr++) = 0x66;
2208 emit_rex(0,(dreg),0,(reg));
2209 *(cd->mcodeptr++) = 0x0f;
2210 *(cd->mcodeptr++) = 0x57;
2211 emit_reg((dreg),(reg));
2215 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2216 *(cd->mcodeptr++) = 0x66;
2217 emit_rex(0,(dreg),0,(basereg));
2218 *(cd->mcodeptr++) = 0x0f;
2219 *(cd->mcodeptr++) = 0x57;
2220 emit_membase(cd, (basereg),(disp),(dreg));
2224 /* system instructions ********************************************************/
2226 void emit_rdtsc(codegendata *cd)
2228 *(cd->mcodeptr++) = 0x0f;
2229 *(cd->mcodeptr++) = 0x31;
2232 /* emit_load_high **************************************************************
2234 Emits a possible load of the high 32-bits of an operand.
2236 *******************************************************************************/
2238 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2244 assert(src->type == TYPE_LNG);
2246 /* get required compiler data */
2250 if (IS_INMEMORY(src->flags)) {
2253 disp = src->vv.regoff * 4;
2255 M_ILD(tempreg, REG_SP, disp);
2260 reg = GET_HIGH_REG(src->vv.regoff);
2265 /* emit_load_low ***************************************************************
2267 Emits a possible load of the low 32-bits of an operand.
2269 *******************************************************************************/
2271 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2277 assert(src->type == TYPE_LNG);
2279 /* get required compiler data */
2283 if (IS_INMEMORY(src->flags)) {
2286 disp = src->vv.regoff * 4;
2288 M_ILD(tempreg, REG_SP, disp + 4);
2293 reg = GET_LOW_REG(src->vv.regoff);
2298 /* emit_nullpointer_check ******************************************************
2300 Emit a NullPointerException check.
2302 *******************************************************************************/
2304 __PORTED__ void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
2306 if (INSTRUCTION_MUST_CHECK(iptr)) {
2309 codegen_add_nullpointerexception_ref(cd);
2313 /* emit_arrayindexoutofbounds_check ********************************************
2315 Emit a ArrayIndexOutOfBoundsException check.
2317 *******************************************************************************/
2319 __PORTED__ void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
2321 if (INSTRUCTION_MUST_CHECK(iptr)) {
2322 N_C(s2, OFFSET(java_arrayheader, size), RN, s1);
2324 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
2330 * These are local overrides for various environment variables in Emacs.
2331 * Please do not remove this and leave it at the end of the file, where
2332 * Emacs will automagically detect them.
2333 * ---------------------------------------------------------------------
2336 * indent-tabs-mode: t