1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8400 2007-08-22 18:28:22Z pm $
34 #include "mm/memory.h"
35 #if defined(ENABLE_THREADS)
36 # include "threads/native/lock.h"
38 #include "vm/builtin.h"
39 #include "vm/exceptions.h"
40 #include "vm/global.h"
41 #include "vm/jit/abi.h"
42 #include "vm/jit/abi-asm.h"
43 #include "vm/jit/asmpart.h"
44 #include "vm/jit/codegen-common.h"
45 #include "vm/jit/emit-common.h"
46 #include "vm/jit/jit.h"
47 #include "vm/jit/patcher-common.h"
48 #include "vm/jit/replace.h"
49 #include "vm/jit/s390/codegen.h"
50 #include "vm/jit/s390/emit.h"
51 #include "vm/jit/s390/md-abi.h"
53 #include "vmcore/options.h"
55 /* emit_load *******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
76 if (IS_FLT_DBL_TYPE(src->type)) {
77 if (IS_2_WORD_TYPE(src->type))
78 M_DLD(tempreg, REG_SP, disp);
80 M_FLD(tempreg, REG_SP, disp);
83 if (IS_2_WORD_TYPE(src->type))
84 M_LLD(tempreg, REG_SP, disp);
86 M_ILD(tempreg, REG_SP, disp);
98 /* emit_store ******************************************************************
100 This function generates the code to store the result of an
101 operation back into a spilled pseudo-variable. If the
102 pseudo-variable has not been spilled in the first place, this
103 function will generate nothing.
105 *******************************************************************************/
107 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
111 /* get required compiler data */
115 if (IS_INMEMORY(dst->flags)) {
118 if (IS_FLT_DBL_TYPE(dst->type)) {
119 if (IS_2_WORD_TYPE(dst->type))
120 M_DST(d, REG_SP, dst->vv.regoff);
122 M_FST(d, REG_SP, dst->vv.regoff);
125 if (IS_2_WORD_TYPE(dst->type))
126 M_LST(d, REG_SP, dst->vv.regoff);
128 M_IST(d, REG_SP, dst->vv.regoff);
134 /* emit_copy *******************************************************************
136 Generates a register/memory to register/memory copy.
138 *******************************************************************************/
140 void emit_copy(jitdata *jd, instruction *iptr)
147 /* get required compiler data */
151 /* get source and destination variables */
153 src = VAROP(iptr->s1);
154 dst = VAROP(iptr->dst);
156 if ((src->vv.regoff != dst->vv.regoff) ||
157 ((src->flags ^ dst->flags) & INMEMORY)) {
159 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
160 /* emit nothing, as the value won't be used anyway */
164 if (IS_INMEMORY(src->flags) && IS_INMEMORY(dst->flags)) {
165 if (IS_2_WORD_TYPE(src->type)) {
166 N_MVC(dst->vv.regoff, 8, REG_SP, src->vv.regoff, REG_SP);
168 N_MVC(dst->vv.regoff, 4, REG_SP, src->vv.regoff, REG_SP);
172 /* If one of the variables resides in memory, we can eliminate
173 the register move from/to the temporary register with the
174 order of getting the destination register and the load. */
176 if (IS_INMEMORY(src->flags)) {
177 if (IS_FLT_DBL_TYPE(dst->type)) {
178 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
180 if (IS_2_WORD_TYPE(dst->type)) {
181 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
183 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
186 s1 = emit_load(jd, iptr, src, d);
189 if (IS_FLT_DBL_TYPE(src->type)) {
190 s1 = emit_load(jd, iptr, src, REG_FTMP1);
192 if (IS_2_WORD_TYPE(src->type)) {
193 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
195 s1 = emit_load(jd, iptr, src, REG_ITMP1);
198 d = codegen_reg_of_var(iptr->opc, dst, s1);
202 if (IS_FLT_DBL_TYPE(src->type)) {
205 if (IS_2_WORD_TYPE(src->type)) {
213 emit_store(jd, iptr, dst, d);
218 /* emit_trap****************************************************************
220 Emit a trap instruction and return the original machine code.
222 *******************************************************************************/
224 uint32_t emit_trap(codegendata *cd)
228 /* Get machine code which is patched back in later. The
229 trap is 2 bytes long. */
231 mcode = *((u2 *) cd->mcodeptr);
233 M_ILL(EXCEPTION_HARDWARE_PATCHER);
239 /* emit_verbosecall_enter ******************************************************
241 Generates the code for the call trace.
243 *******************************************************************************/
246 #include "vm/jit/trace.h"
247 void emit_verbosecall_enter(jitdata *jd)
258 /* mark trace code */
262 /* allocate stack frame */
264 stackframesize = 96 + (ARG_CNT * 8) + (TMP_CNT * 8);
265 M_ASUB_IMM(stackframesize, REG_SP);
267 /* store argument registers in array */
271 for (i = 0; i < INT_ARG_CNT; ++i, off += 8) {
272 M_IST(abi_registers_integer_argument[i], REG_SP, off + 4);
273 /* high bytes are sign extension */
274 M_SRA_IMM(31, abi_registers_integer_argument[i]);
275 M_IST(abi_registers_integer_argument[i], REG_SP, off);
278 for (i = 0; i < FLT_ARG_CNT; ++i, off += 8) {
279 M_DST(abi_registers_float_argument[i], REG_SP, off);
282 /* save temporary registers for leaf methods */
284 if (jd->isleafmethod) {
285 for (i = 0; i < INT_TMP_CNT; ++i, off += 8) {
286 M_IST(abi_registers_integer_temporary[i], REG_SP, off);
289 for (i = 0; i < FLT_TMP_CNT; ++i, off += 8) {
290 M_DST(abi_registers_float_temporary[i], REG_SP, off);
294 /* load arguments for trace_java_call_enter */
297 disp = dseg_add_address(cd, m);
298 M_ALD_DSEG(REG_A0, disp);
299 /* pointer to argument registers array */
300 M_LDA(REG_A1, REG_SP, 96);
301 /* pointer to on stack arguments */
302 M_LDA(REG_A2, REG_SP, stackframesize + (cd->stackframesize * 8));
304 /* call trace_java_call_enter */
306 disp = dseg_add_functionptr(cd, trace_java_call_enter);
307 M_ALD_DSEG(REG_ITMP3, disp);
310 /* restore argument registers */
314 for (i = 0; i < INT_ARG_CNT; ++i, off += 8) {
315 M_ILD(abi_registers_integer_argument[i], REG_SP, off + 4);
318 for (i = 0; i < FLT_ARG_CNT; ++i, off += 8) {
319 M_DLD(abi_registers_float_argument[i], REG_SP, off);
322 /* restore temporary registers for leaf methods */
324 if (jd->isleafmethod) {
325 for (i = 0; i < INT_TMP_CNT; ++i, off += 8) {
326 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
329 for (i = 0; i < FLT_TMP_CNT; ++i, off += 8) {
330 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
334 /* remove stack frame */
336 M_AADD_IMM(stackframesize, REG_SP);
338 /* mark trace code */
347 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
349 /* get required compiler data */
356 /* mark trace code */
361 (6 * 8) + /* s8 on stack parameters x 6 */
362 (1 * 4) + /* methodinfo on stack parameter */
367 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
369 /* save argument registers */
371 off = (6 * 8) + (1 * 4);
373 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
374 M_IST(abi_registers_integer_argument[i], REG_SP, off);
376 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
377 M_DST(abi_registers_float_argument[i], REG_SP, off);
379 /* save temporary registers for leaf methods */
381 if (jd->isleafmethod) {
382 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
383 M_LST(abi_registers_integer_temporary[i], REG_SP, off);
385 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
386 M_DST(abi_registers_float_temporary[i], REG_SP, off);
389 /* Load arguments to new locations */
391 /* First move all arguments to stack
396 * (s8) a1 \ Auxilliary stack frame
401 M_ASUB_IMM(2 * 8, REG_SP);
403 /* offset to where first integer arg is saved on stack */
404 off = (2 * 8) + (6 * 8) + (1 * 4);
405 /* offset to where first float arg is saved on stack */
406 foff = off + (INT_ARG_CNT * 8);
407 /* offset to where first argument is passed on stack */
408 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 8);
409 /* offset to destination on stack */
412 iargctr = fargctr = 0;
414 ICONST(REG_ITMP1, 0);
416 for (i = 0; i < md->paramcount && i < 8; i++) {
417 t = md->paramtypes[i].type;
419 M_IST(REG_ITMP1, REG_SP, doff);
420 M_IST(REG_ITMP1, REG_SP, doff + 4);
422 if (IS_FLT_DBL_TYPE(t)) {
423 if (fargctr < 2) { /* passed in register */
424 N_STD(abi_registers_float_argument[fargctr], doff, RN, REG_SP);
426 } else { /* passed on stack */
428 if (IS_2_WORD_TYPE(t)) {
429 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
431 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
434 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
438 if (IS_2_WORD_TYPE(t)) {
439 if (iargctr < 4) { /* passed in 2 registers */
440 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
442 } else { /* passed on stack */
443 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
447 if (iargctr < 5) { /* passed in register */
448 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
450 } else { /* passed on stack */
451 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
460 /* Now move a0 and a1 to registers
470 N_LM(REG_A0, REG_A1, 0, REG_SP);
471 N_LM(REG_A2, REG_A3, 8, REG_SP);
473 M_AADD_IMM(2 * 8, REG_SP);
475 /* Finally load methodinfo argument */
477 disp = dseg_add_address(cd, m);
478 M_ALD_DSEG(REG_ITMP2, disp);
479 M_AST(REG_ITMP2, REG_SP, 6 * 8);
481 /* Call builtin_verbosecall_enter */
483 disp = dseg_add_address(cd, builtin_verbosecall_enter);
484 M_ALD_DSEG(REG_ITMP2, disp);
485 M_ASUB_IMM(96, REG_SP);
487 M_AADD_IMM(96, REG_SP);
489 /* restore argument registers */
491 off = (6 * 8) + (1 * 4);
493 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
494 M_ILD(abi_registers_integer_argument[i], REG_SP, off);
496 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
497 M_DLD(abi_registers_float_argument[i], REG_SP, off);
499 /* restore temporary registers for leaf methods */
501 if (jd->isleafmethod) {
502 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
503 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
505 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
506 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
509 /* remove stackframe */
511 M_AADD_IMM(stackframesize, REG_SP);
513 /* mark trace code */
518 #endif /* !defined(NDEBUG) */
521 /* emit_verbosecall_exit *******************************************************
523 Generates the code for the call trace.
525 *******************************************************************************/
528 void emit_verbosecall_exit(jitdata *jd)
539 /* mark trace code */
543 /* allocate stackframe */
545 stackframesize = 96 + (3 * 8);
546 M_ASUB_IMM(stackframesize, REG_SP);
548 /* store return values in array and sign extend them */
550 M_IST(REG_RESULT, REG_SP, 96 + (0 * 8) + 4);
551 M_SRA_IMM(31, REG_RESULT);
552 M_IST(REG_RESULT, REG_SP, 96 + (0 * 8));
554 M_IST(REG_RESULT2, REG_SP, 96 + (1 * 8) + 4);
555 M_SRA_IMM(31, REG_RESULT2);
556 M_IST(REG_RESULT2, REG_SP, 96 + (1 * 8));
558 M_DST(REG_FRESULT, REG_SP, 96 + (2 * 8));
560 /* call trace_java_call_exit */
562 disp = dseg_add_address(cd, m);
563 M_ALD_DSEG(REG_A0, disp);
564 M_LDA(REG_A1, REG_SP, 96);
565 disp = dseg_add_functionptr(cd, trace_java_call_exit);
566 M_ALD_DSEG(REG_ITMP3, disp);
569 /* restore return values */
571 M_ILD(REG_RESULT, REG_SP, 96 + (0 * 8) + 4);
572 M_ILD(REG_RESULT2, REG_SP, 96 + (1 * 8) + 4);
573 M_DLD(REG_FRESULT, REG_SP, 96 + (2 * 8));
575 /* remove stackframe */
577 M_AADD_IMM(stackframesize, REG_SP);
579 /* mark trace code */
590 /* get required compiler data */
596 /* mark trace code */
600 M_ASUB_IMM(2 * 8, REG_SP);
602 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
603 M_DST(REG_FRESULT, REG_SP, 1 * 8);
605 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
606 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
608 M_INTMOVE(REG_RESULT, REG_A1);
612 disp = dseg_add_address(cd, m);
613 M_ALD_DSEG(REG_A2, disp);
615 /* REG_FRESULT is REG_FA0, so no need to move */
616 M_FLTMOVE(REG_FRESULT, REG_FA1);
618 disp = dseg_add_address(cd, builtin_verbosecall_exit);
619 M_ALD_DSEG(REG_ITMP1, disp);
620 M_ASUB_IMM(96, REG_SP);
622 M_AADD_IMM(96, REG_SP);
624 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
625 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
627 M_AADD_IMM(2 * 8, REG_SP);
629 /* mark trace code */
634 #endif /* !defined(NDEBUG) */
637 /* emit_load_high **************************************************************
639 Emits a possible load of the high 32-bits of an operand.
641 *******************************************************************************/
643 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
649 assert(src->type == TYPE_LNG);
651 /* get required compiler data */
655 if (IS_INMEMORY(src->flags)) {
658 disp = src->vv.regoff;
660 M_ILD(tempreg, REG_SP, disp);
665 reg = GET_HIGH_REG(src->vv.regoff);
670 /* emit_load_low ***************************************************************
672 Emits a possible load of the low 32-bits of an operand.
674 *******************************************************************************/
676 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
682 assert(src->type == TYPE_LNG);
684 /* get required compiler data */
688 if (IS_INMEMORY(src->flags)) {
691 disp = src->vv.regoff;
693 M_ILD(tempreg, REG_SP, disp + 4);
698 reg = GET_LOW_REG(src->vv.regoff);
703 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
704 codegendata *cd = jd->cd;
705 s4 reg = emit_load_s1(jd, iptr, tempreg);
714 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
715 codegendata *cd = jd->cd;
716 s4 reg = emit_load_s2(jd, iptr, tempreg);
718 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
719 M_FMOV(reg, tempreg);
729 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
730 codegendata *cd = jd->cd;
731 s4 reg = emit_load_s1(jd, iptr, tempreg);
733 if (IS_FLT_DBL_TYPE(VAROP(iptr->s1)->type)) {
734 M_FMOV(reg, tempreg);
744 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
745 codegendata *cd = jd->cd;
746 s4 reg = emit_load_s2(jd, iptr, tempreg);
748 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
749 M_FMOV(reg, tempreg);
759 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
770 * (r12, r13) Illegal, because r13 is PV
771 * (r14, r15) Illegal, because r15 is SP
775 dst = VAROP(iptr->dst);
777 if (IS_INMEMORY(dst->flags)) {
778 if (! IS_REG_ITMP(ltmpreg)) {
779 M_INTMOVE(ltmpreg, breg);
781 if (! IS_REG_ITMP(htmpreg)) {
782 M_INTMOVE(htmpreg, breg);
784 return PACK_REGS(ltmpreg, htmpreg);
786 hr = GET_HIGH_REG(dst->vv.regoff);
787 lr = GET_LOW_REG(dst->vv.regoff);
788 if (((hr % 2) == 0) && lr == (hr + 1)) {
789 /* the result is already in a even-odd pair */
790 return dst->vv.regoff;
791 } else if (((hr % 2) == 0) && (hr < R12)) {
792 /* the high register is at a even position */
793 M_INTMOVE(hr + 1, breg);
794 return PACK_REGS(hr + 1, hr);
795 } else if (((lr % 2) == 1) && (lr < R12)) {
796 /* the low register is at a odd position */
797 M_INTMOVE(lr - 1, breg);
798 return PACK_REGS(lr, lr - 1);
800 /* no way to create an even-odd pair by 1 copy operation,
801 * Use the temporary register pair.
803 if (! IS_REG_ITMP(ltmpreg)) {
804 M_INTMOVE(ltmpreg, breg);
806 if (! IS_REG_ITMP(htmpreg)) {
807 M_INTMOVE(htmpreg, breg);
809 return PACK_REGS(ltmpreg, htmpreg);
814 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
820 dst = VAROP(iptr->dst);
822 if (IS_INMEMORY(dst->flags)) {
823 if (! IS_REG_ITMP(ltmpreg)) {
824 M_INTMOVE(breg, ltmpreg);
826 if (! IS_REG_ITMP(htmpreg)) {
827 M_INTMOVE(breg, htmpreg);
830 hr = GET_HIGH_REG(dst->vv.regoff);
831 lr = GET_LOW_REG(dst->vv.regoff);
832 if (((hr % 2) == 0) && lr == (hr + 1)) {
834 } else if (((hr % 2) == 0) && (hr < R12)) {
835 M_INTMOVE(breg, hr + 1);
836 } else if (((lr % 2) == 1) && (lr < R12)) {
837 M_INTMOVE(breg, lr - 1);
839 if (! IS_REG_ITMP(ltmpreg)) {
840 M_INTMOVE(breg, ltmpreg);
842 if (! IS_REG_ITMP(htmpreg)) {
843 M_INTMOVE(breg, htmpreg);
849 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
853 dst = VAROP(iptr->dst);
854 if (! IS_INMEMORY(dst->flags)) {
855 if (dst->vv.regoff != dtmpreg) {
856 if (IS_FLT_DBL_TYPE(dst->type)) {
857 M_FLTMOVE(dtmpreg, dst->vv.regoff);
858 } else if (IS_2_WORD_TYPE(dst->type)) {
859 M_LNGMOVE(dtmpreg, dst->vv.regoff);
861 M_INTMOVE(dtmpreg, dst->vv.regoff);
867 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
869 s4 branchdisp = disp;
873 if (N_VALID_BRANCH(branchdisp)) {
875 /* valid displacement */
896 case BRANCH_UNCONDITIONAL:
900 vm_abort("emit_branch: unknown condition %d", condition);
904 /* If LONGBRANCHES is not set, the flag and the error flag */
906 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
907 cd->flags |= (CODEGENDATA_FLAG_ERROR |
908 CODEGENDATA_FLAG_LONGBRANCHES);
911 /* If error flag is set, do nothing. The method has to be recompiled. */
913 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
917 /* Patch the displacement to branch over the actual branch manually
918 * to not get yet more nops.
921 branchmpc = cd->mcodeptr - cd->mcodebase;
943 case BRANCH_UNCONDITIONAL:
944 /* fall through, no displacement to patch */
948 vm_abort("emit_branch: unknown condition %d", condition);
951 /* The actual long branch */
953 disp = dseg_add_s4(cd, branchmpc + disp - N_PV_OFFSET);
954 M_ILD_DSEG(REG_ITMP3, disp);
955 M_AADD(REG_PV, REG_ITMP3);
956 M_JMP(RN, REG_ITMP3);
958 /* Patch back the displacement */
961 *(u4 *)ref |= (u4)((cd->mcodeptr - ref) / 2);
966 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
967 if (INSTRUCTION_MUST_CHECK(iptr)) {
969 M_BNE(SZ_BRC + SZ_ILL);
970 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
974 /* emit_arrayindexoutofbounds_check ********************************************
976 Emit a ArrayIndexOutOfBoundsException check.
978 *******************************************************************************/
980 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
982 if (INSTRUCTION_MUST_CHECK(iptr)) {
984 * Do unsigned comparison to catch negative indexes.
986 N_CL(s2, OFFSET(java_array_t, size), RN, s1);
987 M_BLT(SZ_BRC + SZ_ILL);
988 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
992 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
993 if (INSTRUCTION_MUST_CHECK(iptr)) {
999 M_BGT(SZ_BRC + SZ_ILL);
1002 M_BNE(SZ_BRC + SZ_ILL);
1005 M_BLE(SZ_BRC + SZ_ILL);
1008 vm_abort("emit_classcast_check: unknown condition %d", condition);
1010 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
1014 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
1015 if (INSTRUCTION_MUST_CHECK(iptr)) {
1017 M_BNE(SZ_BRC + SZ_ILL);
1018 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
1022 void emit_exception_check(codegendata *cd, instruction *iptr) {
1023 if (INSTRUCTION_MUST_CHECK(iptr)) {
1025 M_BNE(SZ_BRC + SZ_ILL);
1026 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
1030 void emit_restore_pv(codegendata *cd) {
1031 s4 offset, offset_imm;
1035 disp = (s4) (cd->mcodeptr - cd->mcodebase);
1036 M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
1039 /* If the offset from the method start does not fit into an immediate
1040 * value, we can't put it into the data segment!
1043 /* Displacement from start of method to here */
1045 offset = (s4) (cd->mcodeptr - cd->mcodebase);
1046 offset_imm = -offset - SZ_BASR + N_PV_OFFSET;
1048 if (N_VALID_IMM(offset_imm)) {
1049 /* Get program counter */
1051 /* Substract displacement */
1052 M_AADD_IMM(offset_imm, REG_PV);
1054 /* Save program counter and jump over displacement in instruction flow */
1055 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
1056 /* Place displacement here */
1057 /* REG_PV points now exactly to this position */
1058 N_LONG(-offset - SZ_BRAS + N_PV_OFFSET);
1059 /* Substract *(REG_PV) from REG_PV */
1060 N_A(REG_PV, 0, RN, REG_PV);
1065 * These are local overrides for various environment variables in Emacs.
1066 * Please do not remove this and leave it at the end of the file, where
1067 * Emacs will automagically detect them.
1068 * ---------------------------------------------------------------------
1071 * indent-tabs-mode: t