src/vm/jit/powerpc/emit.c

   1 /* src/vm/jit/powerpc/emit.c - PowerPC code emitter functions
   2
   3    Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
   4    C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
   5    E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
   6    J. Wenninger, Institut f. Computersprachen - TU Wien
   7
   8    This file is part of CACAO.
   9
  10    This program is free software; you can redistribute it and/or
  11    modify it under the terms of the GNU General Public License as
  12    published by the Free Software Foundation; either version 2, or (at
  13    your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful, but
  16    WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18    General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  23    02110-1301, USA.
  24
  25 */
  26
  27
  28 #include "config.h"
  29
  30 #include <assert.h>
  31 #include <stdint.h>
  32
  33 #include "vm/types.h"
  34
  35 #include "md-abi.h"
  36
  37 #include "vm/jit/powerpc/codegen.h"
  38
  39 #include "mm/memory.h"
  40
  41 #include "threads/lock-common.h"
  42
  43 #include "vm/builtin.h"
  44 #include "vm/exceptions.h"
  45
  46 #include "vm/jit/abi.h"
  47 #include "vm/jit/asmpart.h"
  48 #include "vm/jit/codegen-common.h"
  49 #include "vm/jit/dseg.h"
  50 #include "vm/jit/emit-common.h"
  51 #include "vm/jit/jit.h"
  52 #include "vm/jit/replace.h"
  53
  54 #include "vmcore/options.h"
  55
  56
  57 /* emit_load *******************************************************************
  58
  59    Emits a possible load of an operand.
  60
  61 *******************************************************************************/
  62
  63 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
  64 {
  65         codegendata *cd;
  66         s4           disp;
  67         s4           reg;
  68
  69         /* get required compiler data */
  70
  71         cd = jd->cd;
  72
  73         if (IS_INMEMORY(src->flags)) {
  74                 COUNT_SPILLS;
  75
  76                 disp = src->vv.regoff;
  77
  78                 switch (src->type) {
  79                 case TYPE_INT:
  80                 case TYPE_ADR:
  81                         M_ILD(tempreg, REG_SP, disp);
  82                         break;
  83                 case TYPE_LNG:
  84                         M_LLD(tempreg, REG_SP, disp);
  85                         break;
  86                 case TYPE_FLT:
  87                 case TYPE_DBL:
  88                         M_DLD(tempreg, REG_SP, disp);
  89                         break;
  90                 default:
  91                         vm_abort("emit_load: unknown type %d", src->type);
  92                 }
  93
  94                 reg = tempreg;
  95         }
  96         else
  97                 reg = src->vv.regoff;
  98
  99         return reg;
 100 }
 101
 102
 103 /* emit_load_low ***************************************************************
 104
 105    Emits a possible load of the low 32-bits of an operand.
 106
 107 *******************************************************************************/
 108
 109 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
 110 {
 111         codegendata  *cd;
 112         s4            disp;
 113         s4            reg;
 114
 115         assert(src->type == TYPE_LNG);
 116
 117         /* get required compiler data */
 118
 119         cd = jd->cd;
 120
 121         if (IS_INMEMORY(src->flags)) {
 122                 COUNT_SPILLS;
 123
 124                 disp = src->vv.regoff;
 125
 126                 M_ILD(tempreg, REG_SP, disp + 4);
 127
 128                 reg = tempreg;
 129         }
 130         else
 131                 reg = GET_LOW_REG(src->vv.regoff);
 132
 133         return reg;
 134 }
 135
 136
 137 /* emit_load_high **************************************************************
 138
 139    Emits a possible load of the high 32-bits of an operand.
 140
 141 *******************************************************************************/
 142
 143 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
 144 {
 145         codegendata  *cd;
 146         s4            disp;
 147         s4            reg;
 148
 149         assert(src->type == TYPE_LNG);
 150
 151         /* get required compiler data */
 152
 153         cd = jd->cd;
 154
 155         if (IS_INMEMORY(src->flags)) {
 156                 COUNT_SPILLS;
 157
 158                 disp = src->vv.regoff;
 159
 160                 M_ILD(tempreg, REG_SP, disp);
 161
 162                 reg = tempreg;
 163         }
 164         else
 165                 reg = GET_HIGH_REG(src->vv.regoff);
 166
 167         return reg;
 168 }
 169
 170
 171 /* emit_store ******************************************************************
 172
 173    Emit a possible store for the given variable.
 174
 175 *******************************************************************************/
 176
 177 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
 178 {
 179         codegendata *cd;
 180         s4           disp;
 181
 182         /* get required compiler data */
 183
 184         cd = jd->cd;
 185
 186         if (IS_INMEMORY(dst->flags)) {
 187                 COUNT_SPILLS;
 188
 189                 disp = dst->vv.regoff;
 190
 191                 switch (dst->type) {
 192                 case TYPE_INT:
 193                 case TYPE_ADR:
 194                         M_IST(d, REG_SP, disp);
 195                         break;
 196                 case TYPE_LNG:
 197                         M_LST(d, REG_SP, disp);
 198                         break;
 199                 case TYPE_FLT:
 200                 case TYPE_DBL:
 201                         M_DST(d, REG_SP, disp);
 202                         break;
 203                 default:
 204                         vm_abort("emit_store: unknown type %d", dst->type);
 205                 }
 206         }
 207 }
 208
 209
 210 /* emit_copy *******************************************************************
 211
 212    Generates a register/memory to register/memory copy.
 213
 214 *******************************************************************************/
 215
 216 void emit_copy(jitdata *jd, instruction *iptr)
 217 {
 218         codegendata *cd;
 219         varinfo     *src;
 220         varinfo     *dst;
 221         s4           s1, d;
 222
 223         /* get required compiler data */
 224
 225         cd = jd->cd;
 226
 227         /* get source and destination variables */
 228
 229         src = VAROP(iptr->s1);
 230         dst = VAROP(iptr->dst);
 231
 232         if ((src->vv.regoff != dst->vv.regoff) ||
 233                 (IS_INMEMORY(src->flags ^ dst->flags))) {
 234
 235                 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
 236                         /* emit nothing, as the value won't be used anyway */
 237                         return;
 238                 }
 239
 240                 /* If one of the variables resides in memory, we can eliminate
 241                    the register move from/to the temporary register with the
 242                    order of getting the destination register and the load. */
 243
 244                 if (IS_INMEMORY(src->flags)) {
 245                         if (IS_LNG_TYPE(src->type))
 246                                 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
 247                         else
 248                                 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
 249
 250                         s1 = emit_load(jd, iptr, src, d);
 251                 }
 252                 else {
 253                         if (IS_LNG_TYPE(src->type))
 254                                 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
 255                         else
 256                                 s1 = emit_load(jd, iptr, src, REG_IFTMP);
 257
 258                         d = codegen_reg_of_var(iptr->opc, dst, s1);
 259                 }
 260
 261                 if (s1 != d) {
 262                         switch (src->type) {
 263                         case TYPE_INT:
 264                         case TYPE_ADR:
 265                                 M_MOV(s1, d);
 266                                 break;
 267                         case TYPE_LNG:
 268                                 M_MOV(GET_LOW_REG(s1), GET_LOW_REG(d));
 269                                 M_MOV(GET_HIGH_REG(s1), GET_HIGH_REG(d));
 270                                 break;
 271                         case TYPE_FLT:
 272                         case TYPE_DBL:
 273                                 M_FMOV(s1, d);
 274                                 break;
 275                         default:
 276                                 vm_abort("emit_copy: unknown type %d", src->type);
 277                         }
 278                 }
 279
 280                 emit_store(jd, iptr, dst, d);
 281         }
 282 }
 283
 284
 285 /* emit_iconst *****************************************************************
 286
 287    XXX
 288
 289 *******************************************************************************/
 290
 291 void emit_iconst(codegendata *cd, s4 d, s4 value)
 292 {
 293         s4 disp;
 294
 295         if ((value >= -32768) && (value <= 32767))
 296                 M_LDA_INTERN(d, REG_ZERO, value);
 297         else {
 298                 disp = dseg_add_s4(cd, value);
 299                 M_ILD(d, REG_PV, disp);
 300         }
 301 }
 302
 303
 304 /* emit_branch *****************************************************************
 305
 306    Emits the code for conditional and unconditional branchs.
 307
 308 *******************************************************************************/
 309
 310 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt)
 311 {
 312         s4 checkdisp;
 313         s4 branchdisp;
 314
 315         /* calculate the different displacements */
 316
 317         checkdisp  =  disp + 4;
 318         branchdisp = (disp - 4) >> 2;
 319
 320         /* check which branch to generate */
 321
 322         if (condition == BRANCH_UNCONDITIONAL) {
 323                 /* check displacement for overflow */
 324
 325                 if ((checkdisp < (s4) 0xfe000000) || (checkdisp > (s4) 0x01fffffc)) {
 326                         /* if the long-branches flag isn't set yet, do it */
 327
 328                         if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
 329                                 cd->flags |= (CODEGENDATA_FLAG_ERROR |
 330                                                           CODEGENDATA_FLAG_LONGBRANCHES);
 331                         }
 332
 333                         vm_abort("emit_branch: emit unconditional long-branch code");
 334                 }
 335                 else {
 336                         M_BR(branchdisp);
 337                 }
 338         }
 339         else {
 340                 /* and displacement for overflow */
 341
 342                 if ((checkdisp < (s4) 0xffff8000) || (checkdisp > (s4) 0x00007fff)) {
 343                         /* if the long-branches flag isn't set yet, do it */
 344
 345                         if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
 346                                 cd->flags |= (CODEGENDATA_FLAG_ERROR |
 347                                                           CODEGENDATA_FLAG_LONGBRANCHES);
 348                         }
 349
 350                         switch (condition) {
 351                         case BRANCH_EQ:
 352                                 M_BNE(1);
 353                                 M_BR(branchdisp);
 354                                 break;
 355                         case BRANCH_NE:
 356                                 M_BEQ(1);
 357                                 M_BR(branchdisp);
 358                                 break;
 359                         case BRANCH_LT:
 360                                 M_BGE(1);
 361                                 M_BR(branchdisp);
 362                                 break;
 363                         case BRANCH_GE:
 364                                 M_BLT(1);
 365                                 M_BR(branchdisp);
 366                                 break;
 367                         case BRANCH_GT:
 368                                 M_BLE(1);
 369                                 M_BR(branchdisp);
 370                                 break;
 371                         case BRANCH_LE:
 372                                 M_BGT(1);
 373                                 M_BR(branchdisp);
 374                                 break;
 375                         case BRANCH_NAN:
 376                                 vm_abort("emit_branch: long BRANCH_NAN");
 377                                 break;
 378                         default:
 379                                 vm_abort("emit_branch: unknown condition %d", condition);
 380                         }
 381                 }
 382                 else {
 383                         switch (condition) {
 384                         case BRANCH_EQ:
 385                                 M_BEQ(branchdisp);
 386                                 break;
 387                         case BRANCH_NE:
 388                                 M_BNE(branchdisp);
 389                                 break;
 390                         case BRANCH_LT:
 391                                 M_BLT(branchdisp);
 392                                 break;
 393                         case BRANCH_GE:
 394                                 M_BGE(branchdisp);
 395                                 break;
 396                         case BRANCH_GT:
 397                                 M_BGT(branchdisp);
 398                                 break;
 399                         case BRANCH_LE:
 400                                 M_BLE(branchdisp);
 401                                 break;
 402                         case BRANCH_NAN:
 403                                 M_BNAN(branchdisp);
 404                                 break;
 405                         default:
 406                                 vm_abort("emit_branch: unknown condition %d", condition);
 407                         }
 408                 }
 409         }
 410 }
 411
 412
 413 /* emit_arithmetic_check *******************************************************
 414
 415    Emit an ArithmeticException check.
 416
 417 *******************************************************************************/
 418
 419 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
 420 {
 421         if (INSTRUCTION_MUST_CHECK(iptr)) {
 422                 M_TST(reg);
 423                 M_BNE(1);
 424                 M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_ARITHMETIC);
 425         }
 426 }
 427
 428
 429 /* emit_arrayindexoutofbounds_check ********************************************
 430
 431    Emit a ArrayIndexOutOfBoundsException check.
 432
 433 *******************************************************************************/
 434
 435 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
 436 {
 437         if (INSTRUCTION_MUST_CHECK(iptr)) {
 438                 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
 439                 M_TRAPGEU(s2, REG_ITMP3);
 440         }
 441 }
 442
 443
 444 /* emit_classcast_check ********************************************************
 445
 446    Emit a ClassCastException check.
 447
 448 *******************************************************************************/
 449
 450 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
 451 {
 452         if (INSTRUCTION_MUST_CHECK(iptr)) {
 453                 switch (condition) {
 454                 case BRANCH_LE:
 455                         M_BGT(1);
 456                         break;
 457                 case BRANCH_EQ:
 458                         M_BNE(1);
 459                         break;
 460                 case BRANCH_GT:
 461                         M_BLE(1);
 462                         break;
 463                 default:
 464                         vm_abort("emit_classcast_check: unknown condition %d", condition);
 465                 }
 466                 M_ALD_INTERN(s1, REG_ZERO, EXCEPTION_HARDWARE_CLASSCAST);
 467         }
 468 }
 469
 470
 471 /* emit_nullpointer_check ******************************************************
 472
 473    Emit a NullPointerException check.
 474
 475 *******************************************************************************/
 476
 477 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
 478 {
 479         if (INSTRUCTION_MUST_CHECK(iptr)) {
 480                 M_TST(reg);
 481                 M_BNE(1);
 482                 M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_NULLPOINTER);
 483         }
 484 }
 485
 486
 487 /* emit_exception_check ********************************************************
 488
 489    Emit an Exception check.
 490
 491 *******************************************************************************/
 492
 493 void emit_exception_check(codegendata *cd, instruction *iptr)
 494 {
 495         if (INSTRUCTION_MUST_CHECK(iptr)) {
 496                 M_TST(REG_RESULT);
 497                 M_BNE(1);
 498                 M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_EXCEPTION);
 499         }
 500 }
 501
 502
 503 /* emit_trap *******************************************************************
 504
 505    Emit a trap instruction and return the original machine code.
 506
 507 *******************************************************************************/
 508
 509 uint32_t emit_trap(codegendata *cd)
 510 {
 511         uint32_t mcode;
 512
 513         /* Get machine code which is patched back in later. The
 514            trap is 1 instruction word long. */
 515
 516         mcode = *((u4 *) cd->mcodeptr);
 517
 518         M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_PATCHER);
 519
 520         return mcode;
 521 }
 522
 523
 524 /* emit_verbosecall_enter ******************************************************
 525
 526    Generates the code for the call trace.
 527
 528 *******************************************************************************/
 529
 530 void emit_verbosecall_enter(jitdata *jd)
 531 {
 532 #if !defined(NDEBUG)
 533         methodinfo   *m;
 534         codegendata  *cd;
 535         registerdata *rd;
 536         methoddesc   *md;
 537         int32_t       disp;
 538         int32_t       i;
 539         int32_t       s, d;
 540         int32_t       x;
 541
 542         if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
 543                 return;
 544
 545         /* get required compiler data */
 546
 547         m  = jd->m;
 548         cd = jd->cd;
 549         rd = jd->rd;
 550
 551         md = m->parseddesc;
 552
 553         /* mark trace code */
 554
 555         M_NOP;
 556
 557         M_MFLR(REG_ZERO);
 558         M_AST(REG_ZERO, REG_SP, LA_LR_OFFSET);
 559         M_STWU(REG_SP, REG_SP, -(LA_SIZE + (1 + ARG_CNT + TMP_CNT) * 8));
 560
 561         M_CLR(REG_ITMP1);                            /* prepare a "zero" register */
 562
 563         /* save argument registers */
 564
 565         for (i = 0; i < md->paramcount; i++) {
 566                 if (!md->params[i].inmemory) {
 567                         s = md->params[i].regoff;
 568                         d = LA_SIZE + (1 + i) * 8;
 569
 570                         switch (md->paramtypes[i].type) {
 571                         case TYPE_INT:
 572                         case TYPE_ADR:
 573                                 M_IST(REG_ITMP1, REG_SP, d);            /* high-bits are zero */
 574                                 M_IST(s, REG_SP, d + 4);
 575                                 break;
 576                         case TYPE_LNG:
 577                                 M_LST(s, REG_SP, d);
 578                                 break;
 579                         case TYPE_FLT:
 580                                 M_IST(REG_ITMP1, REG_SP, d);            /* high-bits are zero */
 581                                 M_FST(s, REG_SP, d + 4);
 582                                 break;
 583                         case TYPE_DBL:
 584                                 M_DST(s, REG_SP, d);
 585                                 break;
 586                         }
 587                 }
 588         }
 589
 590         /* load arguments as longs */
 591
 592         d = 0;
 593
 594         for (i = 0; i < md->paramcount && i < TRACE_ARGS_NUM; i++) {
 595                 s = LA_SIZE + (1 + i) * 8;
 596                 x = PACK_REGS(abi_registers_integer_argument[d + 1],
 597                                           abi_registers_integer_argument[d]);
 598
 599                 M_LLD(x, REG_SP, s);
 600
 601                 d += 2;
 602         }
 603
 604         /* put methodinfo pointer as last argument on the stack */
 605
 606         disp = dseg_add_address(cd, m);
 607         M_ALD(REG_ITMP1, REG_PV, disp);
 608 #if defined(__DARWIN__)
 609         M_AST(REG_ITMP1, REG_SP, LA_SIZE + TRACE_ARGS_NUM * 8);
 610 #else
 611         M_AST(REG_ITMP1, REG_SP, LA_SIZE);
 612 #endif
 613         disp = dseg_add_functionptr(cd, builtin_verbosecall_enter);
 614         M_ALD(REG_ITMP2, REG_PV, disp);
 615         M_MTCTR(REG_ITMP2);
 616         M_JSR;
 617
 618         /* restore argument registers */
 619
 620         for (i = 0; i < md->paramcount; i++) {
 621                 if (!md->params[i].inmemory) {
 622                         s = LA_SIZE + (1 + i) * 8;
 623                         d = md->params[i].regoff;
 624
 625                         switch (md->paramtypes[i].type) {
 626                         case TYPE_INT:
 627                         case TYPE_ADR:
 628                                 M_ILD(d, REG_SP, s + 4);                      /* get low-bits */
 629                                 break;
 630                         case TYPE_LNG:
 631                                 M_LLD(d, REG_SP, s);
 632                                 break;
 633                         case TYPE_FLT:
 634                                 M_FLD(d, REG_SP, s + 4);                      /* get low-bits */
 635                                 break;
 636                         case TYPE_DBL:
 637                                 M_DLD(d, REG_SP, s);
 638                                 break;
 639                         }
 640                 }
 641         }
 642
 643         M_ALD(REG_ZERO, REG_SP, LA_SIZE + (1 + ARG_CNT + TMP_CNT) * 8 + LA_LR_OFFSET);
 644         M_MTLR(REG_ZERO);
 645         M_LDA(REG_SP, REG_SP, LA_SIZE + (1 + ARG_CNT + TMP_CNT) * 8);
 646
 647         /* mark trace code */
 648
 649         M_NOP;
 650 #endif /* !defined(NDEBUG) */
 651 }
 652
 653
 654 /* emit_verbosecall_exit *******************************************************
 655
 656    Generates the code for the call trace.
 657
 658    void builtin_verbosecall_exit(s8 l, double d, float f, methodinfo *m);
 659
 660 *******************************************************************************/
 661
 662 void emit_verbosecall_exit(jitdata *jd)
 663 {
 664 #if !defined(NDEBUG)
 665         methodinfo   *m;
 666         codegendata  *cd;
 667         registerdata *rd;
 668         methoddesc   *md;
 669         s4            disp;
 670
 671         if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
 672                 return;
 673
 674         /* get required compiler data */
 675
 676         m  = jd->m;
 677         cd = jd->cd;
 678         rd = jd->rd;
 679
 680         md = m->parseddesc;
 681
 682         /* mark trace code */
 683
 684         M_NOP;
 685
 686         M_MFLR(REG_ZERO);
 687         M_AST(REG_ZERO, REG_SP, LA_LR_OFFSET);
 688         M_STWU(REG_SP, REG_SP, -(LA_SIZE + (1 + 2 + 2 + 1 + 4) * 4));
 689
 690         /* save return registers */
 691
 692         M_LST(REG_RESULT_PACKED, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 0) * 4);
 693         M_DST(REG_FRESULT, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 2) * 4);
 694
 695         /* keep this order */
 696         switch (md->returntype.type) {
 697         case TYPE_INT:
 698         case TYPE_ADR:
 699                 M_INTMOVE(REG_RESULT, REG_A1);
 700                 M_CLR(REG_A0);
 701                 break;
 702
 703         case TYPE_LNG:
 704                 M_LNGMOVE(REG_RESULT_PACKED, REG_A0_A1_PACKED);
 705                 break;
 706         }
 707
 708         M_FLTMOVE(REG_FRESULT, REG_FA0);
 709         M_FLTMOVE(REG_FRESULT, REG_FA1);
 710
 711         disp = dseg_add_address(cd, m);
 712         M_ALD(REG_A2, REG_PV, disp);
 713
 714         disp = dseg_add_functionptr(cd, builtin_verbosecall_exit);
 715         M_ALD(REG_ITMP2, REG_PV, disp);
 716         M_MTCTR(REG_ITMP2);
 717         M_JSR;
 718
 719         /* restore return registers */
 720
 721         M_LLD(REG_RESULT_PACKED, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 0) * 4);
 722         M_DLD(REG_FRESULT, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 2) * 4);
 723
 724         M_ALD(REG_ZERO, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 4) * 4 + LA_LR_OFFSET);
 725         M_MTLR(REG_ZERO);
 726         M_LDA(REG_SP, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 4) * 4);
 727
 728         /* mark trace code */
 729
 730         M_NOP;
 731 #endif /* !defined(NDEBUG) */
 732 }
 733
 734
 735 /*
 736  * These are local overrides for various environment variables in Emacs.
 737  * Please do not remove this and leave it at the end of the file, where
 738  * Emacs will automagically detect them.
 739  * ---------------------------------------------------------------------
 740  * Local variables:
 741  * mode: c
 742  * indent-tabs-mode: t
 743  * c-basic-offset: 4
 744  * tab-width: 4
 745  * End:
 746  * vim:noexpandtab:sw=4:ts=4:
 747  */