src/vm/jit/powerpc/emit.c

   1 /* src/vm/jit/powerpc/emit.c - PowerPC code emitter functions
   2
   3    Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
   4    C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
   5    E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
   6    J. Wenninger, Institut f. Computersprachen - TU Wien
   7
   8    This file is part of CACAO.
   9
  10    This program is free software; you can redistribute it and/or
  11    modify it under the terms of the GNU General Public License as
  12    published by the Free Software Foundation; either version 2, or (at
  13    your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful, but
  16    WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18    General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  23    02110-1301, USA.
  24
  25    $Id: emit.c 8318 2007-08-16 10:05:34Z michi $
  26
  27 */
  28
  29
  30 #include "config.h"
  31
  32 #include <assert.h>
  33 #include <stdint.h>
  34
  35 #include "vm/types.h"
  36
  37 #include "md-abi.h"
  38
  39 #include "vm/jit/powerpc/codegen.h"
  40
  41 #include "mm/memory.h"
  42
  43 #include "threads/lock-common.h"
  44
  45 #include "vm/builtin.h"
  46 #include "vm/exceptions.h"
  47
  48 #include "vm/jit/abi.h"
  49 #include "vm/jit/asmpart.h"
  50 #include "vm/jit/codegen-common.h"
  51 #include "vm/jit/dseg.h"
  52 #include "vm/jit/emit-common.h"
  53 #include "vm/jit/jit.h"
  54 #include "vm/jit/replace.h"
  55
  56 #include "vmcore/options.h"
  57
  58
  59 /* emit_load *******************************************************************
  60
  61    Emits a possible load of an operand.
  62
  63 *******************************************************************************/
  64
  65 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
  66 {
  67         codegendata *cd;
  68         s4           disp;
  69         s4           reg;
  70
  71         /* get required compiler data */
  72
  73         cd = jd->cd;
  74
  75         if (IS_INMEMORY(src->flags)) {
  76                 COUNT_SPILLS;
  77
  78                 disp = src->vv.regoff;
  79
  80                 switch (src->type) {
  81                 case TYPE_INT:
  82                 case TYPE_ADR:
  83                         M_ILD(tempreg, REG_SP, disp);
  84                         break;
  85                 case TYPE_LNG:
  86                         M_LLD(tempreg, REG_SP, disp);
  87                         break;
  88                 case TYPE_FLT:
  89                 case TYPE_DBL:
  90                         M_DLD(tempreg, REG_SP, disp);
  91                         break;
  92                 default:
  93                         vm_abort("emit_load: unknown type %d", src->type);
  94                 }
  95
  96                 reg = tempreg;
  97         }
  98         else
  99                 reg = src->vv.regoff;
 100
 101         return reg;
 102 }
 103
 104
 105 /* emit_load_low ***************************************************************
 106
 107    Emits a possible load of the low 32-bits of an operand.
 108
 109 *******************************************************************************/
 110
 111 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
 112 {
 113         codegendata  *cd;
 114         s4            disp;
 115         s4            reg;
 116
 117         assert(src->type == TYPE_LNG);
 118
 119         /* get required compiler data */
 120
 121         cd = jd->cd;
 122
 123         if (IS_INMEMORY(src->flags)) {
 124                 COUNT_SPILLS;
 125
 126                 disp = src->vv.regoff;
 127
 128                 M_ILD(tempreg, REG_SP, disp + 4);
 129
 130                 reg = tempreg;
 131         }
 132         else
 133                 reg = GET_LOW_REG(src->vv.regoff);
 134
 135         return reg;
 136 }
 137
 138
 139 /* emit_load_high **************************************************************
 140
 141    Emits a possible load of the high 32-bits of an operand.
 142
 143 *******************************************************************************/
 144
 145 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
 146 {
 147         codegendata  *cd;
 148         s4            disp;
 149         s4            reg;
 150
 151         assert(src->type == TYPE_LNG);
 152
 153         /* get required compiler data */
 154
 155         cd = jd->cd;
 156
 157         if (IS_INMEMORY(src->flags)) {
 158                 COUNT_SPILLS;
 159
 160                 disp = src->vv.regoff;
 161
 162                 M_ILD(tempreg, REG_SP, disp);
 163
 164                 reg = tempreg;
 165         }
 166         else
 167                 reg = GET_HIGH_REG(src->vv.regoff);
 168
 169         return reg;
 170 }
 171
 172
 173 /* emit_store ******************************************************************
 174
 175    Emit a possible store for the given variable.
 176
 177 *******************************************************************************/
 178
 179 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
 180 {
 181         codegendata *cd;
 182         s4           disp;
 183
 184         /* get required compiler data */
 185
 186         cd = jd->cd;
 187
 188         if (IS_INMEMORY(dst->flags)) {
 189                 COUNT_SPILLS;
 190
 191                 disp = dst->vv.regoff;
 192
 193                 switch (dst->type) {
 194                 case TYPE_INT:
 195                 case TYPE_ADR:
 196                         M_IST(d, REG_SP, disp);
 197                         break;
 198                 case TYPE_LNG:
 199                         M_LST(d, REG_SP, disp);
 200                         break;
 201                 case TYPE_FLT:
 202                 case TYPE_DBL:
 203                         M_DST(d, REG_SP, disp);
 204                         break;
 205                 default:
 206                         vm_abort("emit_store: unknown type %d", dst->type);
 207                 }
 208         }
 209 }
 210
 211
 212 /* emit_copy *******************************************************************
 213
 214    Generates a register/memory to register/memory copy.
 215
 216 *******************************************************************************/
 217
 218 void emit_copy(jitdata *jd, instruction *iptr)
 219 {
 220         codegendata *cd;
 221         varinfo     *src;
 222         varinfo     *dst;
 223         s4           s1, d;
 224
 225         /* get required compiler data */
 226
 227         cd = jd->cd;
 228
 229         /* get source and destination variables */
 230
 231         src = VAROP(iptr->s1);
 232         dst = VAROP(iptr->dst);
 233
 234         if ((src->vv.regoff != dst->vv.regoff) ||
 235                 (IS_INMEMORY(src->flags ^ dst->flags))) {
 236
 237                 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
 238                         /* emit nothing, as the value won't be used anyway */
 239                         return;
 240                 }
 241
 242                 /* If one of the variables resides in memory, we can eliminate
 243                    the register move from/to the temporary register with the
 244                    order of getting the destination register and the load. */
 245
 246                 if (IS_INMEMORY(src->flags)) {
 247                         if (IS_LNG_TYPE(src->type))
 248                                 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
 249                         else
 250                                 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
 251
 252                         s1 = emit_load(jd, iptr, src, d);
 253                 }
 254                 else {
 255                         if (IS_LNG_TYPE(src->type))
 256                                 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
 257                         else
 258                                 s1 = emit_load(jd, iptr, src, REG_IFTMP);
 259
 260                         d = codegen_reg_of_var(iptr->opc, dst, s1);
 261                 }
 262
 263                 if (s1 != d) {
 264                         switch (src->type) {
 265                         case TYPE_INT:
 266                         case TYPE_ADR:
 267                                 M_MOV(s1, d);
 268                                 break;
 269                         case TYPE_LNG:
 270                                 M_MOV(GET_LOW_REG(s1), GET_LOW_REG(d));
 271                                 M_MOV(GET_HIGH_REG(s1), GET_HIGH_REG(d));
 272                                 break;
 273                         case TYPE_FLT:
 274                         case TYPE_DBL:
 275                                 M_FMOV(s1, d);
 276                                 break;
 277                         default:
 278                                 vm_abort("emit_copy: unknown type %d", src->type);
 279                         }
 280                 }
 281
 282                 emit_store(jd, iptr, dst, d);
 283         }
 284 }
 285
 286
 287 /* emit_iconst *****************************************************************
 288
 289    XXX
 290
 291 *******************************************************************************/
 292
 293 void emit_iconst(codegendata *cd, s4 d, s4 value)
 294 {
 295         s4 disp;
 296
 297         if ((value >= -32768) && (value <= 32767))
 298                 M_LDA_INTERN(d, REG_ZERO, value);
 299         else {
 300                 disp = dseg_add_s4(cd, value);
 301                 M_ILD(d, REG_PV, disp);
 302         }
 303 }
 304
 305
 306 /* emit_branch *****************************************************************
 307
 308    Emits the code for conditional and unconditional branchs.
 309
 310 *******************************************************************************/
 311
 312 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt)
 313 {
 314         s4 checkdisp;
 315         s4 branchdisp;
 316
 317         /* calculate the different displacements */
 318
 319         checkdisp  =  disp + 4;
 320         branchdisp = (disp - 4) >> 2;
 321
 322         /* check which branch to generate */
 323
 324         if (condition == BRANCH_UNCONDITIONAL) {
 325                 /* check displacement for overflow */
 326
 327                 if ((checkdisp < (s4) 0xfe000000) || (checkdisp > (s4) 0x01fffffc)) {
 328                         /* if the long-branches flag isn't set yet, do it */
 329
 330                         if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
 331                                 cd->flags |= (CODEGENDATA_FLAG_ERROR |
 332                                                           CODEGENDATA_FLAG_LONGBRANCHES);
 333                         }
 334
 335                         vm_abort("emit_branch: emit unconditional long-branch code");
 336                 }
 337                 else {
 338                         M_BR(branchdisp);
 339                 }
 340         }
 341         else {
 342                 /* and displacement for overflow */
 343
 344                 if ((checkdisp < (s4) 0xffff8000) || (checkdisp > (s4) 0x00007fff)) {
 345                         /* if the long-branches flag isn't set yet, do it */
 346
 347                         if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
 348                                 cd->flags |= (CODEGENDATA_FLAG_ERROR |
 349                                                           CODEGENDATA_FLAG_LONGBRANCHES);
 350                         }
 351
 352                         switch (condition) {
 353                         case BRANCH_EQ:
 354                                 M_BNE(1);
 355                                 M_BR(branchdisp);
 356                                 break;
 357                         case BRANCH_NE:
 358                                 M_BEQ(1);
 359                                 M_BR(branchdisp);
 360                                 break;
 361                         case BRANCH_LT:
 362                                 M_BGE(1);
 363                                 M_BR(branchdisp);
 364                                 break;
 365                         case BRANCH_GE:
 366                                 M_BLT(1);
 367                                 M_BR(branchdisp);
 368                                 break;
 369                         case BRANCH_GT:
 370                                 M_BLE(1);
 371                                 M_BR(branchdisp);
 372                                 break;
 373                         case BRANCH_LE:
 374                                 M_BGT(1);
 375                                 M_BR(branchdisp);
 376                                 break;
 377                         case BRANCH_NAN:
 378                                 vm_abort("emit_branch: long BRANCH_NAN");
 379                                 break;
 380                         default:
 381                                 vm_abort("emit_branch: unknown condition %d", condition);
 382                         }
 383                 }
 384                 else {
 385                         switch (condition) {
 386                         case BRANCH_EQ:
 387                                 M_BEQ(branchdisp);
 388                                 break;
 389                         case BRANCH_NE:
 390                                 M_BNE(branchdisp);
 391                                 break;
 392                         case BRANCH_LT:
 393                                 M_BLT(branchdisp);
 394                                 break;
 395                         case BRANCH_GE:
 396                                 M_BGE(branchdisp);
 397                                 break;
 398                         case BRANCH_GT:
 399                                 M_BGT(branchdisp);
 400                                 break;
 401                         case BRANCH_LE:
 402                                 M_BLE(branchdisp);
 403                                 break;
 404                         case BRANCH_NAN:
 405                                 M_BNAN(branchdisp);
 406                                 break;
 407                         default:
 408                                 vm_abort("emit_branch: unknown condition %d", condition);
 409                         }
 410                 }
 411         }
 412 }
 413
 414
 415 /* emit_arithmetic_check *******************************************************
 416
 417    Emit an ArithmeticException check.
 418
 419 *******************************************************************************/
 420
 421 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
 422 {
 423         if (INSTRUCTION_MUST_CHECK(iptr)) {
 424                 M_TST(reg);
 425                 M_BNE(1);
 426                 M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_ARITHMETIC);
 427         }
 428 }
 429
 430
 431 /* emit_arrayindexoutofbounds_check ********************************************
 432
 433    Emit a ArrayIndexOutOfBoundsException check.
 434
 435 *******************************************************************************/
 436
 437 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
 438 {
 439         if (INSTRUCTION_MUST_CHECK(iptr)) {
 440                 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
 441                 M_TRAPGEU(s2, REG_ITMP3);
 442         }
 443 }
 444
 445
 446 /* emit_classcast_check ********************************************************
 447
 448    Emit a ClassCastException check.
 449
 450 *******************************************************************************/
 451
 452 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
 453 {
 454         if (INSTRUCTION_MUST_CHECK(iptr)) {
 455                 switch (condition) {
 456                 case BRANCH_LE:
 457                         M_BGT(1);
 458                         break;
 459                 case BRANCH_EQ:
 460                         M_BNE(1);
 461                         break;
 462                 case BRANCH_GT:
 463                         M_BLE(1);
 464                         break;
 465                 default:
 466                         vm_abort("emit_classcast_check: unknown condition %d", condition);
 467                 }
 468                 M_ALD_INTERN(s1, REG_ZERO, EXCEPTION_HARDWARE_CLASSCAST);
 469         }
 470 }
 471
 472
 473 /* emit_nullpointer_check ******************************************************
 474
 475    Emit a NullPointerException check.
 476
 477 *******************************************************************************/
 478
 479 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
 480 {
 481         if (INSTRUCTION_MUST_CHECK(iptr)) {
 482                 M_TST(reg);
 483                 M_BNE(1);
 484                 M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_NULLPOINTER);
 485         }
 486 }
 487
 488
 489 /* emit_exception_check ********************************************************
 490
 491    Emit an Exception check.
 492
 493 *******************************************************************************/
 494
 495 void emit_exception_check(codegendata *cd, instruction *iptr)
 496 {
 497         if (INSTRUCTION_MUST_CHECK(iptr)) {
 498                 M_TST(REG_RESULT);
 499                 M_BNE(1);
 500                 M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_EXCEPTION);
 501         }
 502 }
 503
 504
 505 /* emit_trap *******************************************************************
 506
 507    Emit a trap instruction and return the original machine code.
 508
 509 *******************************************************************************/
 510
 511 uint32_t emit_trap(codegendata *cd)
 512 {
 513         uint32_t mcode;
 514
 515         /* Get machine code which is patched back in later. The
 516            trap is 1 instruction word long. */
 517
 518         mcode = *((u4 *) cd->mcodeptr);
 519
 520         M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_PATCHER);
 521
 522         return mcode;
 523 }
 524
 525
 526 /* emit_verbosecall_enter ******************************************************
 527
 528    Generates the code for the call trace.
 529
 530 *******************************************************************************/
 531
 532 void emit_verbosecall_enter(jitdata *jd)
 533 {
 534 #if !defined(NDEBUG)
 535         methodinfo   *m;
 536         codegendata  *cd;
 537         registerdata *rd;
 538         methoddesc   *md;
 539         int32_t       disp;
 540         int32_t       i;
 541         int32_t       s, d;
 542         int32_t       x;
 543
 544         if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
 545                 return;
 546
 547         /* get required compiler data */
 548
 549         m  = jd->m;
 550         cd = jd->cd;
 551         rd = jd->rd;
 552
 553         md = m->parseddesc;
 554
 555         /* mark trace code */
 556
 557         M_NOP;
 558
 559         M_MFLR(REG_ZERO);
 560         M_AST(REG_ZERO, REG_SP, LA_LR_OFFSET);
 561         M_STWU(REG_SP, REG_SP, -(LA_SIZE + (1 + ARG_CNT + TMP_CNT) * 8));
 562
 563         M_CLR(REG_ITMP1);                            /* prepare a "zero" register */
 564
 565         /* save argument registers */
 566
 567         for (i = 0; i < md->paramcount; i++) {
 568                 if (!md->params[i].inmemory) {
 569                         s = md->params[i].regoff;
 570                         d = LA_SIZE + (1 + i) * 8;
 571
 572                         switch (md->paramtypes[i].type) {
 573                         case TYPE_INT:
 574                         case TYPE_ADR:
 575                                 M_IST(REG_ITMP1, REG_SP, d);            /* high-bits are zero */
 576                                 M_IST(s, REG_SP, d + 4);
 577                                 break;
 578                         case TYPE_LNG:
 579                                 M_LST(s, REG_SP, d);
 580                                 break;
 581                         case TYPE_FLT:
 582                                 M_IST(REG_ITMP1, REG_SP, d);            /* high-bits are zero */
 583                                 M_FST(s, REG_SP, d + 4);
 584                                 break;
 585                         case TYPE_DBL:
 586                                 M_DST(s, REG_SP, d);
 587                                 break;
 588                         }
 589                 }
 590         }
 591
 592         /* load arguments as longs */
 593
 594         d = 0;
 595
 596         for (i = 0; i < md->paramcount && i < TRACE_ARGS_NUM; i++) {
 597                 s = LA_SIZE + (1 + i) * 8;
 598                 x = PACK_REGS(abi_registers_integer_argument[d + 1],
 599                                           abi_registers_integer_argument[d]);
 600
 601                 M_LLD(x, REG_SP, s);
 602
 603                 d += 2;
 604         }
 605
 606         /* put methodinfo pointer as last argument on the stack */
 607
 608         disp = dseg_add_address(cd, m);
 609         M_ALD(REG_ITMP1, REG_PV, disp);
 610 #if defined(__DARWIN__)
 611         M_AST(REG_ITMP1, REG_SP, LA_SIZE + TRACE_ARGS_NUM * 8);
 612 #else
 613         M_AST(REG_ITMP1, REG_SP, LA_SIZE);
 614 #endif
 615         disp = dseg_add_functionptr(cd, builtin_verbosecall_enter);
 616         M_ALD(REG_ITMP2, REG_PV, disp);
 617         M_MTCTR(REG_ITMP2);
 618         M_JSR;
 619
 620         /* restore argument registers */
 621
 622         for (i = 0; i < md->paramcount; i++) {
 623                 if (!md->params[i].inmemory) {
 624                         s = LA_SIZE + (1 + i) * 8;
 625                         d = md->params[i].regoff;
 626
 627                         switch (md->paramtypes[i].type) {
 628                         case TYPE_INT:
 629                         case TYPE_ADR:
 630                                 M_ILD(d, REG_SP, s + 4);                      /* get low-bits */
 631                                 break;
 632                         case TYPE_LNG:
 633                                 M_LLD(d, REG_SP, s);
 634                                 break;
 635                         case TYPE_FLT:
 636                                 M_FLD(d, REG_SP, s + 4);                      /* get low-bits */
 637                                 break;
 638                         case TYPE_DBL:
 639                                 M_DLD(d, REG_SP, s);
 640                                 break;
 641                         }
 642                 }
 643         }
 644
 645         M_ALD(REG_ZERO, REG_SP, LA_SIZE + (1 + ARG_CNT + TMP_CNT) * 8 + LA_LR_OFFSET);
 646         M_MTLR(REG_ZERO);
 647         M_LDA(REG_SP, REG_SP, LA_SIZE + (1 + ARG_CNT + TMP_CNT) * 8);
 648
 649         /* mark trace code */
 650
 651         M_NOP;
 652 #endif /* !defined(NDEBUG) */
 653 }
 654
 655
 656 /* emit_verbosecall_exit *******************************************************
 657
 658    Generates the code for the call trace.
 659
 660    void builtin_verbosecall_exit(s8 l, double d, float f, methodinfo *m);
 661
 662 *******************************************************************************/
 663
 664 void emit_verbosecall_exit(jitdata *jd)
 665 {
 666 #if !defined(NDEBUG)
 667         methodinfo   *m;
 668         codegendata  *cd;
 669         registerdata *rd;
 670         methoddesc   *md;
 671         s4            disp;
 672
 673         if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
 674                 return;
 675
 676         /* get required compiler data */
 677
 678         m  = jd->m;
 679         cd = jd->cd;
 680         rd = jd->rd;
 681
 682         md = m->parseddesc;
 683
 684         /* mark trace code */
 685
 686         M_NOP;
 687
 688         M_MFLR(REG_ZERO);
 689         M_AST(REG_ZERO, REG_SP, LA_LR_OFFSET);
 690         M_STWU(REG_SP, REG_SP, -(LA_SIZE + (1 + 2 + 2 + 1 + 4) * 4));
 691
 692         /* save return registers */
 693
 694         M_LST(REG_RESULT_PACKED, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 0) * 4);
 695         M_DST(REG_FRESULT, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 2) * 4);
 696
 697         /* keep this order */
 698         switch (md->returntype.type) {
 699         case TYPE_INT:
 700         case TYPE_ADR:
 701                 M_INTMOVE(REG_RESULT, REG_A1);
 702                 M_CLR(REG_A0);
 703                 break;
 704
 705         case TYPE_LNG:
 706                 M_LNGMOVE(REG_RESULT_PACKED, REG_A0_A1_PACKED);
 707                 break;
 708         }
 709
 710         M_FLTMOVE(REG_FRESULT, REG_FA0);
 711         M_FLTMOVE(REG_FRESULT, REG_FA1);
 712
 713         disp = dseg_add_address(cd, m);
 714         M_ALD(REG_A2, REG_PV, disp);
 715
 716         disp = dseg_add_functionptr(cd, builtin_verbosecall_exit);
 717         M_ALD(REG_ITMP2, REG_PV, disp);
 718         M_MTCTR(REG_ITMP2);
 719         M_JSR;
 720
 721         /* restore return registers */
 722
 723         M_LLD(REG_RESULT_PACKED, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 0) * 4);
 724         M_DLD(REG_FRESULT, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 2) * 4);
 725
 726         M_ALD(REG_ZERO, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 4) * 4 + LA_LR_OFFSET);
 727         M_MTLR(REG_ZERO);
 728         M_LDA(REG_SP, REG_SP, LA_SIZE + (1 + 2 + 2 + 1 + 4) * 4);
 729
 730         /* mark trace code */
 731
 732         M_NOP;
 733 #endif /* !defined(NDEBUG) */
 734 }
 735
 736
 737 /*
 738  * These are local overrides for various environment variables in Emacs.
 739  * Please do not remove this and leave it at the end of the file, where
 740  * Emacs will automagically detect them.
 741  * ---------------------------------------------------------------------
 742  * Local variables:
 743  * mode: c
 744  * indent-tabs-mode: t
 745  * c-basic-offset: 4
 746  * tab-width: 4
 747  * End:
 748  * vim:noexpandtab:sw=4:ts=4:
 749  */