1 /* src/vm/jit/powerpc/codegen.h - code generation macros and definitions for
4 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
5 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
6 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
7 J. Wenninger, Institut f. Computersprachen - TU Wien
9 This file is part of CACAO.
11 This program is free software; you can redistribute it and/or
12 modify it under the terms of the GNU General Public License as
13 published by the Free Software Foundation; either version 2, or (at
14 your option) any later version.
16 This program is distributed in the hope that it will be useful, but
17 WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
26 Contact: cacao@cacaojvm.org
28 Authors: Andreas Krall
31 Changes: Christian Thalinger
34 $Id: codegen.h 4357 2006-01-22 23:33:38Z twisti $
46 #include "vm/global.h"
47 #include "vm/jit/jit.h"
48 #include "vm/jit/reg.h"
51 /* additional functions and macros to generate code ***************************/
53 /* gen_nullptr_check(objreg) */
55 #define gen_nullptr_check(objreg) \
59 codegen_addxnullrefs(cd, mcodeptr); \
62 #define gen_bound_check \
64 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));\
65 M_CMPU(s2, REG_ITMP3);\
67 codegen_addxboundrefs(cd, mcodeptr, s2); \
71 /* MCODECHECK(icnt) */
73 #define MCODECHECK(icnt) \
74 if ((mcodeptr + (icnt)) > cd->mcodeend) \
75 mcodeptr = codegen_increase(cd, (u1 *) mcodeptr)
79 generates an integer-move from register a to b.
80 if a and b are the same int-register, no code will be generated.
83 #define M_INTMOVE(a,b) if ((a) != (b)) { M_MOV(a, b); }
85 #define M_TINTMOVE(t,a,b) \
86 if ((t) == TYPE_LNG) { \
88 M_INTMOVE(GET_LOW_REG((a)), GET_LOW_REG((b))); \
89 M_INTMOVE(GET_HIGH_REG((a)), GET_HIGH_REG((b))); \
91 M_INTMOVE(GET_LOW_REG((a)), GET_LOW_REG((b))); \
93 M_INTMOVE((a), (b)); \
98 generates a floating-point-move from register a to b.
99 if a and b are the same float-register, no code will be generated
102 #define M_FLTMOVE(a,b) if ((a) != (b)) { M_FMOV(a, b); }
106 this function generates code to fetch data from a pseudo-register
107 into a real register.
108 If the pseudo-register has actually been assigned to a real
109 register, no code will be emitted, since following operations
110 can use this register directly.
112 v: pseudoregister to be fetched from
113 tempregnum: temporary register to be used if v is actually spilled to ram
115 return: the register number, where the operand can be found after
116 fetching (this wil be either tempregnum or the register
117 number allready given to v)
120 #define var_to_reg_int(regnr,v,tempnr) \
122 if ((v)->flags & INMEMORY) { \
124 if (IS_2_WORD_TYPE((v)->type)) { \
125 M_ILD(GET_HIGH_REG((tempnr)), REG_SP, (v)->regoff * 4); \
126 M_ILD(GET_LOW_REG((tempnr)), REG_SP, (v)->regoff * 4 + 4); \
128 M_ILD((tempnr), REG_SP, (v)->regoff * 4); \
131 regnr = (v)->regoff; \
136 /* fetch only the low part of v, regnr hast to be a single register */
138 #define var_to_reg_lng_low(regnr,v,tempnr) \
140 if ((v)->flags & INMEMORY) { \
142 M_ILD((tempnr), REG_SP, (v)->regoff * 4 + 4); \
145 regnr = GET_LOW_REG((v)->regoff); \
150 /* fetch only the high part of v, regnr hast to be a single register */
152 #define var_to_reg_lng_high(regnr,v,tempnr) \
154 if ((v)->flags & INMEMORY) { \
156 M_ILD((tempnr), REG_SP, (v)->regoff * 4); \
159 regnr = GET_HIGH_REG((v)->regoff); \
165 #define var_to_reg_flt(regnr,v,tempnr) \
167 if ((v)->flags & INMEMORY) { \
169 if ((v)->type == TYPE_DBL) \
170 M_DLD(tempnr, REG_SP, (v)->regoff * 4); \
172 M_FLD(tempnr, REG_SP, (v)->regoff * 4); \
175 regnr = (v)->regoff; \
180 /* store_reg_to_var_xxx ********************************************************
182 This function generates the code to store the result of an
183 operation back into a spilled pseudo-variable. If the
184 pseudo-variable has not been spilled in the first place, this
185 function will generate nothing.
187 v ............ Pseudovariable
188 tempregnum ... Number of the temporary registers as returned by
191 *******************************************************************************/
193 #define store_reg_to_var_int(sptr, tempregnum) \
195 if ((sptr)->flags & INMEMORY) { \
197 M_IST(tempregnum, REG_SP, (sptr)->regoff * 4); \
201 #define store_reg_to_var_lng(sptr, tempregnum) \
203 if ((sptr)->flags & INMEMORY) { \
205 M_IST(GET_HIGH_REG(tempregnum), REG_SP, (sptr)->regoff * 4); \
206 M_IST(GET_LOW_REG(tempregnum), REG_SP, (sptr)->regoff * 4 + 4); \
210 #define store_reg_to_var_adr(sptr, tempregnum) \
211 store_reg_to_var_int(sptr, tempregnum)
213 #define store_reg_to_var_flt(sptr, tempregnum) \
215 if ((sptr)->flags & INMEMORY) { \
217 M_FST(tempregnum, REG_SP, (sptr)->regoff * 4); \
221 #define store_reg_to_var_dbl(sptr, tempregnum) \
223 if ((sptr)->flags & INMEMORY) { \
225 M_DST(tempregnum, REG_SP, (sptr)->regoff * 4); \
230 #define ICONST(reg,c) \
231 if (((c) >= 0 && (c) <= 32767) || ((c) >= -32768 && (c) < 0)) {\
232 M_LDA((reg), REG_ZERO, (c)); \
234 a = dseg_adds4(cd, c); \
235 M_ILD((reg), REG_PV, a); \
238 #define LCONST(reg,c) \
239 ICONST(GET_HIGH_REG((reg)), (s4) ((s8) (c) >> 32)); \
240 ICONST(GET_LOW_REG((reg)), (s4) ((s8) (c)));
243 #define M_COPY(from,to) \
244 d = reg_of_var(rd, to, REG_IFTMP); \
245 if ((from->regoff != to->regoff) || \
246 ((from->flags ^ to->flags) & INMEMORY)) { \
247 if (IS_FLT_DBL_TYPE(from->type)) { \
248 var_to_reg_flt(s1, from, d); \
250 store_reg_to_var_flt(to, d); \
253 var_to_reg_int(s1, from, d); \
254 M_TINTMOVE(from->type,s1,d); \
255 store_reg_to_var_int(to, d); \
260 #define ALIGNCODENOP \
261 if ((s4) ((ptrint) mcodeptr & 7)) { \
266 /* macros to create code ******************************************************/
268 #define M_OP3(opcode,y,oe,rc,d,a,b) \
269 *(mcodeptr++) = (((opcode) << 26) | ((d) << 21) | ((a) << 16) | ((b) << 11) | ((oe) << 10) | ((y) << 1) | (rc))
271 #define M_OP4(x,y,rc,d,a,b,c) \
272 *(mcodeptr++) = (((x) << 26) | ((d) << 21) | ((a) << 16) | ((b) << 11) | ((c) << 6) | ((y) << 1) | (rc))
274 #define M_OP2_IMM(x,d,a,i) \
275 *(mcodeptr++) = (((x) << 26) | ((d) << 21) | ((a) << 16) | ((i) & 0xffff))
277 #define M_BRMASK 0x0000fffc /* (((1 << 16) - 1) & ~3) */
278 #define M_BRAMASK 0x03fffffc /* (((1 << 26) - 1) & ~3) */
280 #define M_BRA(x,i,a,l) \
281 *(mcodeptr++) = (((x) << 26) | ((((i) * 4) + 4) & M_BRAMASK) | ((a) << 1) | (l))
283 #define M_BRAC(x,bo,bi,i,a,l) \
284 *(mcodeptr++) = (((x) << 26) | ((bo) << 21) | ((bi) << 16) | (((i) * 4 + 4) & M_BRMASK) | ((a) << 1) | (l))
287 /* instruction macros *********************************************************/
289 #define M_IADD(a,b,c) M_OP3(31, 266, 0, 0, c, a, b)
290 #define M_IADD_IMM(a,b,c) M_OP2_IMM(14, c, a, b)
291 #define M_ADDC(a,b,c) M_OP3(31, 10, 0, 0, c, a, b)
292 #define M_ADDIC(a,b,c) M_OP2_IMM(12, c, a, b)
293 #define M_ADDICTST(a,b,c) M_OP2_IMM(13, c, a, b)
294 #define M_ADDE(a,b,c) M_OP3(31, 138, 0, 0, c, a, b)
295 #define M_ADDZE(a,b) M_OP3(31, 202, 0, 0, b, a, 0)
296 #define M_ADDME(a,b) M_OP3(31, 234, 0, 0, b, a, 0)
297 #define M_ISUB(a,b,c) M_OP3(31, 40, 0, 0, c, b, a)
298 #define M_ISUBTST(a,b,c) M_OP3(31, 40, 0, 1, c, b, a)
299 #define M_SUBC(a,b,c) M_OP3(31, 8, 0, 0, c, b, a)
300 #define M_SUBIC(a,b,c) M_OP2_IMM(8, c, b, a)
301 #define M_SUBE(a,b,c) M_OP3(31, 136, 0, 0, c, b, a)
302 #define M_SUBZE(a,b) M_OP3(31, 200, 0, 0, b, a, 0)
303 #define M_SUBME(a,b) M_OP3(31, 232, 0, 0, b, a, 0)
305 #define M_AND(a,b,c) M_OP3(31, 28, 0, 0, a, c, b)
306 #define M_AND_IMM(a,b,c) M_OP2_IMM(28, a, c, b)
307 #define M_ANDIS(a,b,c) M_OP2_IMM(29, a, c, b)
308 #define M_OR(a,b,c) M_OP3(31, 444, 0, 0, a, c, b)
309 #define M_OR_TST(a,b,c) M_OP3(31, 444, 0, 1, a, c, b)
310 #define M_OR_IMM(a,b,c) M_OP2_IMM(24, a, c, b)
311 #define M_ORIS(a,b,c) M_OP2_IMM(25, a, c, b)
312 #define M_XOR(a,b,c) M_OP3(31, 316, 0, 0, a, c, b)
313 #define M_XOR_IMM(a,b,c) M_OP2_IMM(26, a, c, b)
314 #define M_XORIS(a,b,c) M_OP2_IMM(27, a, c, b)
316 #define M_SLL(a,b,c) M_OP3(31, 24, 0, 0, a, c, b)
317 #define M_SRL(a,b,c) M_OP3(31, 536, 0, 0, a, c, b)
318 #define M_SRA(a,b,c) M_OP3(31, 792, 0, 0, a, c, b)
319 #define M_SRA_IMM(a,b,c) M_OP3(31, 824, 0, 0, a, c, b)
321 #define M_IMUL(a,b,c) M_OP3(31, 235, 0, 0, c, a, b)
322 #define M_IMUL_IMM(a,b,c) M_OP2_IMM(7, c, a, b)
323 #define M_IDIV(a,b,c) M_OP3(31, 491, 0, 0, c, a, b)
325 #define M_NEG(a,b) M_OP3(31, 104, 0, 0, b, a, 0)
326 #define M_NOT(a,b) M_OP3(31, 124, 0, 0, a, b, a)
328 #define M_SUBFIC(a,b,c) M_OP2_IMM(8, c, a, b)
329 #define M_SUBFZE(a,b) M_OP3(31, 200, 0, 0, b, a, 0)
330 #define M_RLWINM(a,b,c,d,e) M_OP4(21, d, 0, a, e, b, c)
331 #define M_ADDZE(a,b) M_OP3(31, 202, 0, 0, b, a, 0)
332 #define M_SLL_IMM(a,b,c) M_RLWINM(a,b,0,31-(b),c)
333 #define M_SRL_IMM(a,b,c) M_RLWINM(a,32-(b),b,31,c)
334 #define M_ADDIS(a,b,c) M_OP2_IMM(15, c, a, b)
335 #define M_STFIWX(a,b,c) M_OP3(31, 983, 0, 0, a, b, c)
336 #define M_LWZX(a,b,c) M_OP3(31, 23, 0, 0, a, b, c)
337 #define M_LHZX(a,b,c) M_OP3(31, 279, 0, 0, a, b, c)
338 #define M_LHAX(a,b,c) M_OP3(31, 343, 0, 0, a, b, c)
339 #define M_LBZX(a,b,c) M_OP3(31, 87, 0, 0, a, b, c)
340 #define M_LFSX(a,b,c) M_OP3(31, 535, 0, 0, a, b, c)
341 #define M_LFDX(a,b,c) M_OP3(31, 599, 0, 0, a, b, c)
342 #define M_STWX(a,b,c) M_OP3(31, 151, 0, 0, a, b, c)
343 #define M_STHX(a,b,c) M_OP3(31, 407, 0, 0, a, b, c)
344 #define M_STBX(a,b,c) M_OP3(31, 215, 0, 0, a, b, c)
345 #define M_STFSX(a,b,c) M_OP3(31, 663, 0, 0, a, b, c)
346 #define M_STFDX(a,b,c) M_OP3(31, 727, 0, 0, a, b, c)
348 #define M_STWU_INTERN(a,b,disp) M_OP2_IMM(37,a,b,disp)
350 #define M_STWU(a,b,disp) \
352 s4 lo = (disp) & 0x0000ffff; \
353 s4 hi = ((disp) >> 16); \
354 if (((disp) >= -32678) && ((disp) <= 32767)) { \
355 M_STWU_INTERN(a,b,lo); \
357 M_ADDIS(REG_ZERO,hi,REG_ITMP3); \
358 M_OR_IMM(REG_ITMP3,lo,REG_ITMP3); \
359 M_STWUX(REG_SP,REG_SP,REG_ITMP3); \
363 #define M_STWUX(a,b,c) M_OP3(31,183,0,0,a,b,c)
365 #define M_LDAH(a,b,c) M_ADDIS(b, c, a)
366 #define M_TRAP M_OP3(31, 4, 0, 0, 31, 0, 0)
368 #define M_NOP M_OR_IMM(0, 0, 0)
369 #define M_MOV(a,b) M_OR(a, a, b)
370 #define M_TST(a) M_OP3(31, 444, 0, 1, a, a, a)
372 #define M_DADD(a,b,c) M_OP3(63, 21, 0, 0, c, a, b)
373 #define M_FADD(a,b,c) M_OP3(59, 21, 0, 0, c, a, b)
374 #define M_DSUB(a,b,c) M_OP3(63, 20, 0, 0, c, a, b)
375 #define M_FSUB(a,b,c) M_OP3(59, 20, 0, 0, c, a, b)
376 #define M_DMUL(a,b,c) M_OP4(63, 25, 0, c, a, 0, b)
377 #define M_FMUL(a,b,c) M_OP4(59, 25, 0, c, a, 0, b)
378 #define M_DDIV(a,b,c) M_OP3(63, 18, 0, 0, c, a, b)
379 #define M_FDIV(a,b,c) M_OP3(59, 18, 0, 0, c, a, b)
381 #define M_FABS(a,b) M_OP3(63, 264, 0, 0, b, 0, a)
382 #define M_CVTDL(a,b) M_OP3(63, 14, 0, 0, b, 0, a)
383 #define M_CVTDL_C(a,b) M_OP3(63, 15, 0, 0, b, 0, a)
384 #define M_CVTDF(a,b) M_OP3(63, 12, 0, 0, b, 0, a)
385 #define M_FMOV(a,b) M_OP3(63, 72, 0, 0, b, 0, a)
386 #define M_FMOVN(a,b) M_OP3(63, 40, 0, 0, b, 0, a)
387 #define M_DSQRT(a,b) M_OP3(63, 22, 0, 0, b, 0, a)
388 #define M_FSQRT(a,b) M_OP3(59, 22, 0, 0, b, 0, a)
390 #define M_FCMPU(a,b) M_OP3(63, 0, 0, 0, 0, a, b)
391 #define M_FCMPO(a,b) M_OP3(63, 32, 0, 0, 0, a, b)
393 #define M_BLDU(a,b,c) M_OP2_IMM(34, a, b, c)
394 #define M_SLDU(a,b,c) M_OP2_IMM(40, a, b, c)
396 #define M_ILD_INTERN(a,b,disp) M_OP2_IMM(32,a,b,disp)
398 #define M_ILD(a,b,disp) \
400 s4 lo = (short) (disp); \
401 s4 hi = (short) (((disp) - lo) >> 16); \
403 M_ILD_INTERN(a,b,lo); \
406 M_ILD_INTERN(a,a,lo); \
410 #define M_ALD_INTERN(a,b,disp) M_ILD_INTERN(a,b,disp)
411 #define M_ALD(a,b,disp) M_ILD(a,b,disp)
413 #define M_BST(a,b,c) M_OP2_IMM(38, a, b, c)
414 #define M_SST(a,b,c) M_OP2_IMM(44, a, b, c)
416 #define M_IST_INTERN(a,b,disp) M_OP2_IMM(36,a,b,disp)
418 /* Stores with displacement overflow should only happen with PUTFIELD or on */
419 /* the stack. The PUTFIELD instruction does not use REG_ITMP3 and a */
420 /* reg_of_var call should not use REG_ITMP3!!! */
422 #define M_IST(a,b,disp) \
424 s4 lo = (short) (disp); \
425 s4 hi = (short) (((disp) - lo) >> 16); \
427 M_IST_INTERN(a,b,lo); \
429 M_ADDIS(b,hi,REG_ITMP3); \
430 M_IST_INTERN(a,REG_ITMP3,lo); \
434 #define M_AST_INTERN(a,b,disp) M_IST_INTERN(a,b,disp)
435 #define M_AST(a,b,disp) M_IST(a,b,disp)
437 #define M_BSEXT(a,b) M_OP3(31, 954, 0, 0, a, b, 0)
438 #define M_SSEXT(a,b) M_OP3(31, 922, 0, 0, a, b, 0)
439 #define M_CZEXT(a,b) M_RLWINM(a,0,16,31,b)
441 #define M_BR(a) M_BRA(18, a, 0, 0)
442 #define M_BL(a) M_BRA(18, a, 0, 1)
443 #define M_RET M_OP3(19, 16, 0, 0, 20, 0, 0)
444 #define M_JSR M_OP3(19, 528, 0, 1, 20, 0, 0)
445 #define M_RTS M_OP3(19, 528, 0, 0, 20, 0, 0)
447 #define M_CMP(a,b) M_OP3(31, 0, 0, 0, 0, a, b)
448 #define M_CMPU(a,b) M_OP3(31, 32, 0, 0, 0, a, b)
449 #define M_CMPI(a,b) M_OP2_IMM(11, 0, a, b)
450 #define M_CMPUI(a,b) M_OP2_IMM(10, 0, a, b)
452 #define M_BLT(a) M_BRAC(16, 12, 0, a, 0, 0)
453 #define M_BLE(a) M_BRAC(16, 4, 1, a, 0, 0)
454 #define M_BGT(a) M_BRAC(16, 12, 1, a, 0, 0)
455 #define M_BGE(a) M_BRAC(16, 4, 0, a, 0, 0)
456 #define M_BEQ(a) M_BRAC(16, 12, 2, a, 0, 0)
457 #define M_BNE(a) M_BRAC(16, 4, 2, a, 0, 0)
458 #define M_BNAN(a) M_BRAC(16, 12, 3, a, 0, 0)
460 #define M_FLD_INTERN(a,b,disp) M_OP2_IMM(48,a,b,disp)
461 #define M_DLD_INTERN(a,b,disp) M_OP2_IMM(50,a,b,disp)
463 #define M_FLD(a,b,disp) \
465 s4 lo = (short) (disp); \
466 s4 hi = (short) (((disp) - lo) >> 16); \
468 M_FLD_INTERN(a,b,lo); \
470 M_ADDIS(b,hi,REG_ITMP3); \
471 M_FLD_INTERN(a,REG_ITMP3,lo); \
475 #define M_DLD(a,b,disp) \
477 s4 lo = (short) (disp); \
478 s4 hi = (short) (((disp) - lo) >> 16); \
480 M_DLD_INTERN(a,b,lo); \
482 M_ADDIS(b,hi,REG_ITMP3); \
483 M_DLD_INTERN(a,REG_ITMP3,lo); \
487 #define M_FST_INTERN(a,b,disp) M_OP2_IMM(52,a,b,disp)
488 #define M_DST_INTERN(a,b,disp) M_OP2_IMM(54,a,b,disp)
490 #define M_FST(a,b,disp) \
492 s4 lo = (short) (disp); \
493 s4 hi = (short) (((disp) - lo) >> 16); \
495 M_FST_INTERN(a,b,lo); \
497 M_ADDIS(b,hi,REG_ITMP3); \
498 M_FST_INTERN(a,REG_ITMP3,lo); \
502 #define M_DST(a,b,disp) \
504 s4 lo = (short) (disp); \
505 s4 hi = (short) (((disp) - lo) >> 16); \
507 M_DST_INTERN(a,b,lo); \
509 M_ADDIS(b,hi,REG_ITMP3); \
510 M_DST_INTERN(a,REG_ITMP3,lo); \
514 #define M_MFLR(a) M_OP3(31, 339, 0, 0, a, 8, 0)
515 #define M_MFXER(a) M_OP3(31, 339, 0, 0, a, 1, 0)
516 #define M_MFCTR(a) M_OP3(31, 339, 0, 0, a, 9, 0)
517 #define M_MTLR(a) M_OP3(31, 467, 0, 0, a, 8, 0)
518 #define M_MTXER(a) M_OP3(31, 467, 0, 0, a, 1, 0)
519 #define M_MTCTR(a) M_OP3(31, 467, 0, 0, a, 9, 0)
521 #define M_LDA_INTERN(a,b,c) M_IADD_IMM(b, c, a)
523 #define M_LDA(a,b,disp) \
525 s4 lo = (short) (disp); \
526 s4 hi = (short) (((disp) - lo) >> 16); \
528 M_LDA_INTERN(a,b,lo); \
531 M_LDA_INTERN(a,a,lo); \
536 #define M_LDATST(a,b,c) M_ADDICTST(b, c, a)
537 #define M_CLR(a) M_IADD_IMM(0, 0, a)
538 #define M_AADD_IMM(a,b,c) M_IADD_IMM(a, b, c)
541 /* function gen_resolvebranch **************************************************
543 parameters: ip ... pointer to instruction after branch (void*)
544 so ... offset of instruction after branch (s4)
545 to ... offset of branch target (s4)
547 *******************************************************************************/
549 #define gen_resolvebranch(ip,so,to) \
550 *((s4*)(ip)-1)=(*((s4*)(ip)-1) & ~M_BRMASK) | (((s4)((to)-(so))+4)&((((*((s4*)(ip)-1)>>26)&63)==18)?M_BRAMASK:M_BRMASK))
553 /* function prototypes ********************************************************/
555 void docacheflush(u1 *p, long bytelen);
557 #endif /* _CODEGEN_H */
561 * These are local overrides for various environment variables in Emacs.
562 * Please do not remove this and leave it at the end of the file, where
563 * Emacs will automagically detect them.
564 * ---------------------------------------------------------------------
567 * indent-tabs-mode: t