1 /* src/vm/jit/m68k/codegen.h
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: arch.h 5330 2006-09-05 18:43:12Z edwin $
38 #include "vm/jit/m68k/emit.h"
41 #define MCODECHECK(icnt) \
43 if ((cd->mcodeptr + (icnt) * 4) > cd->mcodeend) \
44 codegen_increase(cd); \
48 /* branch defines *************************************************************/
52 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) { \
63 /* patcher defines ************************************************************/
65 #define PATCHER_NOPS \
66 do { M_TPFL; M_TPF; M_TPF } while (0);
69 /* stub defines ***************************************************************/
71 #define COMPILERSTUB_CODESIZE (6+6+6+2)
74 /* coldfire instruction format:
75 * -----------------------------
77 * |____________________________|
78 * | extension word 1(optional) |
79 * |____________________________|
80 * | extension word 2(optional) |
81 * |____________________________|
88 * x x x x x x x x x x | M M M | R R R
90 * MMM = 000 ---> data register direct: RRR = register
91 * MMM = 001 ---> addr register direct: RRR = register
92 * MMM = 010 ---> addr register indirect: RRR = register
93 * MMM = 011 ---> addr reg ind postincr : RRR = register
94 * MMM = 100 ---> addr reg ind predecr : RRR = register
95 * MMM = 101 ---> addr reg ind + displac: RRR = register + ext.wrd.1
96 * MMM = 110 ---> addr reg ind + scaled index and 8 bit displacement
97 * MMM = 111, RRR = 010 ---> PC ind. with displacement + ext.wrd.1
98 * MMM = 111, RRR = 011 ---> PC ind. with scaled inex + 8but displacement
99 * MMM = 111, RRR = 000 + ext.wrd.1 ---> absolute short
100 * MMM = 111, RRR = 001 + ext.wrd.1+2 -> absolute long
101 * MMM = 111, RRR = 100 + ext.wrd1/2 --> immediate data
104 /* one word opcodes */
105 #define OPWORD(op, mode, reg) \
107 *((u2*)cd->mcodeptr) = (u2) (((op) << 6) | ((mode)<<3) | (reg)); \
110 /* opword + one extension word */
111 /* usage of int16_t instead of s2 as is clashes with variable name */
112 #define OPWORD_IMM16(op, mode, reg, imm) \
114 *((u2*)cd->mcodeptr) = (u2) (((op) << 6) | ((mode)<<3) | (reg)); \
116 *((int16_t*)(cd->mcodeptr)) = imm; \
120 /* opword + two extension words */
121 /* usage of int32_t instead of s4 as is clashes with variable name */
122 #define OPWORD_IMM32(op, mode, reg, imm) \
124 *((u2*)cd->mcodeptr) = (u2) (((op) << 6) | ((mode)<<3) | (reg)); \
126 *((int32_t*)(cd->mcodeptr)) = imm; \
130 /* create NOPS to align basicblock boundaries
131 * using real nops here as they are not executed, so no performance penalty
133 #define ALIGNCODENOP \
135 for (s1 = 0; s1 < (s4) (((ptrint) cd->mcodeptr) & 7); s1++) \
141 #define PATCHER_CALL_SIZE 6
143 #define M_NOP OPWORD(0x139,6,1) /* 0x4371 do not use as it syncs pipeline */
144 #define M_ILLEGAL OPWORD(0x12b,7,4) /* 0x4afc */
145 #define M_TPF OPWORD(0x147,7,4) /* tfp with no ext. word use instead of NOP*/
146 #define M_TPFW OPWORD(0x147,7,2) /* tfp with one ext. word */
147 #define M_TPFL OPWORD(0x147,7,3) /* tfp with two ext. word */
149 /*M_XMOVX....M_XMOVX(source, destination) */
150 #define M_IMOV(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 0), 0, (a)) /* move.l */
151 #define M_AMOV(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 1), 1, (a)) /* movea.l */
152 #define M_IMOV_IMM(a,b) emit_mov_imm_reg(cd, (a), (b))
153 #define M_AMOV_IMM(a,b) OPWORD_IMM32( ( (2<<6) | ((b) << 3) | 1), 7, 4, (a))
155 /* for sure generates a 32 bit immedeate form, needed when there are patchers involved */
156 #define M_IMOV_IMM32(a,b) OPWORD_IMM32(((2<<6) | ((b) << 3) | 0), 7, 4, (a))
158 #define M_ICLR(a) OPWORD(0x10a, 0, (a)) /* clr.l */
159 #define M_ISET(a) OPWORD( ( (0xa <<6) | (0 << 3) | 5), 0, (a)) /* mov3q #-1 */
161 #define M_JMP(a) OPWORD(0x13b,2,(a)) /* jmp %aX@ */
162 #define M_JMP_IMM(a) OPWORD_IMM32(0x13b,7,1,(a)) /* jmp.l */
163 #define M_JSR(a) OPWORD(0x13a,2,(a)) /* jsr %aX@ */
164 #define M_JSR_IMM(a) OPWORD_IMM32(0x13a,7,1,(a)) /* jsr.l */
165 #define M_BSR_IMM(a) OPWORD_IMM32(0x187,7,7,(a)) /* bsr.l */
166 #define M_JSR_PCREL(a) OPWORD_IMM16(0x13a,7,2,(a)) /* jsr.l (d16,PC) */
168 #define M_RET OPWORD(0x139,6,5) /* 0x4375 */
169 #define M_LINK(a,b) OPWORD_IMM16(0x139,2,(a), (b)) /* link */
170 #define M_UNLK(a) OPWORD(0x139, 3, (a)) /* unlk */
172 /* push and pop are implemented using move.l */
173 /* we need 3 variants, data, address and float registers */
174 /* also a POPALL and PUSHALL for verbose:call code, use them only there! */
175 #define M_IPUSH(a) OPWORD(0xbc,0,(a))
176 #define M_APUSH(a) OPWORD(0xbc,1,(a))
178 #define M_IPOP(a) OPWORD( ( (2<<6) | ((a) << 3) | 0 ), 3, REG_SP)
179 #define M_APOP(a) OPWORD( ( (2<<6) | ((a) << 3) | 1 ), 3, REG_SP) /* movea.l acutally */
182 #define M_IPUSH_IMM(a) OPWORD_IMM32(0x121,7,1, (a)) /* pea.l */
184 #define M_PUSHALL OPWORD_IMM16(0x123,2,REG_SP,0xFFFF) /* A0-A7, D0-D7 pushed onto stack */
185 #define M_POPALL OPWORD_IMM16(0x133,2,REG_SP,0xFFFF) /* A0-A7, D0-D7 poped off stack */
187 /* M_XLD(a,b,c)....M_XLD(destinationreg, addressbase, offset) */
188 #define M_ILD(a,b,c) OPWORD_IMM16( ( (2<<6) | ((a) << 3) | 0), 5, (b), (c))
189 #define M_ALD(a,b,c) OPWORD_IMM16( ( (2<<6) | ((a) << 3) | 1), 5, (b), (c))
190 #define M_LLD(a,b,c) do {\
191 M_ILD(GET_HIGH_REG(a), (b), (c));\
192 M_ILD(GET_LOW_REG (a), (b), (c)+4);\
195 #if !defined(ENABLE_SOFTFLOAT)
196 #define M_FLD(a,b,c) M_ILLEGAL
197 #define M_DLD(a,b,c) M_ILLEGAL
200 /* M_XST(a,b,c)....M_XST(sourceregister, addressbase, offset) */
201 #define M_IST(a,b,c) OPWORD_IMM16( ( (2<<6) | ((b) << 3) | 5), 0, (a), (c))
202 #define M_AST(a,b,c) OPWORD_IMM16( ( (2<<6) | ((b) << 3) | 5), 1, (a), (c))
203 #define M_LST(a,b,c) do {\
204 M_IST(GET_HIGH_REG(a), (b), (c));\
205 M_IST(GET_LOW_REG (a), (b), (c)+4);\
208 #if !defined(ENABLE_SOFTFLOAT)
209 #define M_FST(a,b,c) M_ILLEGAL
210 #define M_DST(a,b,c) M_ILLEGAL
213 /*M_XADD_IMM(a,b)...M_XADD_IMM(offset, reg) */
214 #define M_AADD_IMM(a,b) OPWORD_IMM32( ( (0xd<<6) | ((b)<<3) | 7), 7, 4, (a))
215 #define M_IADD_IMM(a,b) OPWORD_IMM32( ( (0xd<<6) | ((b)<<3) | 2), 7, 4, (a))
216 #define M_ISUB_IMM(a,b) M_IADD_IMM(-(a), (b))
218 /* M_OP(source, dest) ... dest (OP) source -> dest*/
219 #define M_ISUB(a,b) OPWORD ( ( (9<<6) | ((b)<<3) | 2), 0, (a)) /* sub.l */
220 #define M_IADD(a,b) OPWORD ( ( (0xd<<6) | ((b)<<3) | 2), 0, (a)) /* add.l */
222 #define M_IMUL(a,b) OPWORD_IMM16 ( 0x130, 0, (a), ( ((b) << 12) | (1 << 11))) /* muls.l */
223 #define M_IDIV(a,b) OPWORD_IMM16 ( 0x131, 0, (a), ( ((b) << 12) | (1 << 11) | (b))) /* divs.l */
225 #define M_ISSL(a,b) OPWORD ( ( (0xe<<6) | ((a) << 3) | 6), 4, (b)) /* asl.l */
226 #define M_ISSR(a,b) OPWORD ( ( (0xe<<6) | ((a) << 3) | 2), 4, (b)) /* asr.l */
227 #define M_IUSR(a,b) OPWORD ( ( (0xe<<6) | ((a) << 3) | 2), 5, (b)) /* lsr.l */
229 #define M_IAND(a,b) OPWORD ( ( (0xc<<6) | ((b) << 3) | 2), 0, (a)) /* and.l */
231 #define M_IOR(a,b) OPWORD ( ( (0x8<<6) | ((b) << 3) | 2), 0, (a)) /* or.l */
234 /* ultra sepcial 3 register form, b%a = c, (a!=c) */
235 #define M_IREM(a,b,c) OPWORD_IMM16 ( 0x131, 0, (a), ( ((b) << 12) | (1 << 11) | (c))) /* rems.l */
238 #define M_INEG(a) OPWORD(0x112, 0, (a)) /* neg.l */
240 /* only generate opcode when condition true */
241 #define OPWORD_COND(c, u,v,w) \
243 if ( (c) ) { OPWORD( (u),(v),(w) ) } \
245 /* assert on the opcode */
246 #define OPWORD_ASSERT(a, u,v,w) \
249 OPWORD( (u),(v),(w) ) \
252 /* M_XMOVE....M_XMOVE(sourcereg, destreg) */
253 #define M_INTMOVE(a,b) OPWORD_COND(((a) != (b)), ( ( 2<<6) | ((b) << 3) | 0), 0, (a));
254 #define M_ADRMOVE(a,b) OPWORD_COND(((a) != (b)), ( ( 2<<6) | ((b) << 3) | 1), 1, (a));
255 #define M_INT2ADRMOVE(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 1), 0, (a));
256 #define M_ADR2INTMOVE(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 0), 1, (a));
257 #define M_LNGMOVE(a,b) do {\
258 M_INTMOVE(GET_LOW_REG (a), GET_LOW_REG (b));\
259 M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b));\
262 #if !defined(ENABLE_SOFTLFOAT)
263 #define M_FLTMOVE(a,b) M_ILLEGAL
264 #define M_DBLMOVE(a,b) M_ILLEGAL
266 /* M_XTST....M_XTST(register) */
267 #define M_ITST(a) OPWORD(0x12a, 0, (a)) /* tst.l */
268 #define M_ATST(a) OPWORD(0x12a, 1, (a)) /* tst.l */
270 /* M_XCMPI....M_XMCPI(immideate, register) */
271 #define M_ICMP_IMM(a,b) OPWORD_IMM32( 0x32, 0, (b), (a))
273 #define M_ACMPI(a,b) OPWORD_IMM32( ( (0xb << 6) | ((b) << 3) | 7), 7, 4, (a)) /* cmpa.l # */
275 /* M_XCMP....M_XCMP(reg1, reg2) */
276 #define M_ICMP(b,a) OPWORD( ( (0xb << 6) | ((a) << 3) | 2), 0, (b)) /* cmp.l */
277 #define M_ACMP(b,a) OPWORD( ( (0xb << 6) | ((a) << 3) | 7), 1, (b)) /* cmpa.l */
279 /* M_AND_IMM(imm, register) */
280 #define M_IAND_IMM(a,b) OPWORD_IMM32( 0xa, 0, (b), (a)) /* andi.l # */
282 /* All kind of branches one could ever possibly need, each with 16 and 32 bit displacement */
283 /* BRANCH16 and BRANCH32 are helpers */
284 #define BRANCH8(cond,imm) \
286 *((u2*)cd->mcodeptr) = (u2) (((0x6) << 12) | ((cond)<<8) | (int8_t)imm); \
290 #define BRANCH16(cond,imm) \
292 *((u2*)cd->mcodeptr) = (u2) (((0x6) << 12) | ((cond)<<8) | 0x00); \
294 *((int16_t*)(cd->mcodeptr)) = imm; \
297 #define BRANCH32(cond,imm) \
299 *((u2*)cd->mcodeptr) = (u2) (((0x6) << 12) | ((cond)<<8) | 0xff); \
301 *((int32_t*)(cd->mcodeptr)) = imm; \
305 #define M_BR_16(a) BRANCH16(0x0, (a)) /* branch always */
306 #define M_BR_32(a) BRANCH32(0x0, (a))
308 #define M_BEQ(a) BRANCH8 (0x7, (a))
309 #define M_BEQ_16(a) BRANCH16(0x7, (a))
310 #define M_BEQ_32(a) BRANCH32(0x7, (a))
312 #define M_BNE(a) BRANCH8 (0x6, (a))
313 #define M_BNE_16(a) BRANCH16(0x6, (a))
314 #define M_BNE_32(a) BRANCH32(0x6, (a))
316 #define M_BLT(a) BRANCH8 (0xd, (a))
317 #define M_BLT_16(a) BRANCH16(0xd, (a))
318 #define M_BLT_32(a) BRANCH32(0xd, (a))
320 #define M_BGE(a) BRANCH8 (0xc, (a))
321 #define M_BGE_16(a) BRANCH16(0xc, (a))
322 #define M_BGE_32(a) BRANCH32(0xc, (a))
324 #define M_BGT(a) BRANCH8 (0xe, (a))
325 #define M_BGT_16(a) BRANCH16(0xe, (a))
326 #define M_BGT_32(a) BRANCH32(0xe, (a))
328 #define M_BLE(a) BRANCH8 (0xf, (a))
329 #define M_BLE_16(a) BRANCH16(0xf, (a))
330 #define M_BLE_32(a) BRANCH32(0xf, (a))
332 #define M_BHI(a) BRANCH8 (0x2, (a))
333 #define M_BHI_16(a) BRANCH16(0x2, (a))
334 #define M_BHI_32(a) BRANCH32(0x2, (a))
336 #define M_BLS(a) BRANCH8 (0x3, (a))
338 #define M_BMI(a) BRANCH8(0xb, (a))
339 #define M_BPL(a) BRANCH8(0xa, (a))
341 #define M_BNAN_16(a) M_ILLEGAL /* TODO */
342 #define M_BNAN_32(a) M_ILLEGAL
344 /* array store/load stuff */
345 /* M_LXXX(baseaddressregister, targetregister) */
346 /* M_SXXX(baseaddressregsiter, sourceregister) */
347 #define M_LBZX(a,c) OPWORD( ( (1<<6) | ((c) << 3) | 0), 2, (a)) /* move.l */
348 #define M_LHZX(a,c) OPWORD( ( (3<<6) | ((c) << 3) | 0), 2, (a))
349 #define M_LWZX(a,c) OPWORD( ( (2<<6) | ((c) << 3) | 0), 2, (a))
350 #define M_LAX(a,c) OPWORD( ( (2<<6) | ((c) << 3) | 1), 2, (a)) /* movea.l */
352 #define M_STBX(a,c) OPWORD( ( (1<<6) | ((a) << 3) | 2), 0, (c)) /* move.l */
353 #define M_STHX(a,c) OPWORD( ( (3<<6) | ((a) << 3) | 2), 0, (c))
354 #define M_STWX(a,c) OPWORD( ( (2<<6) | ((a) << 3) | 2), 0, (c))
355 #define M_STAX(a,c) OPWORD( ( (2<<6) | ((a) << 3) | 2), 1, (c)) /* movea.l */
357 #if !defined(ENABLE_SOFTFLOAT)
358 #define M_LFSX(a,c) M_ILLEGAL
359 #define M_LFDX(a,c) M_ILLEGAL
360 #define M_STFSX(a,c) M_ILLEGAL
361 #define M_STFDX(a,c) M_ILLEGAL
364 #define M_BSEXT(a,b) OPWORD( ( (7<<6) | ((b) << 3) | 4), 0, (a)) /* mvs.b */
365 #define M_CZEXT(a,b) OPWORD( ( (7<<6) | ((b) << 3) | 7), 0, (a)) /* mvz.w */
366 #define M_SSEXT(a,b) OPWORD( ( (7<<6) | ((b) << 3) | 5), 0, (a)) /* mvs.w */
367 #define M_HSEXT(a,b) M_ILLEGAL
369 /* adds content of integer reg a to address register b, result is b */
370 #define M_AADDINT(a,b) OPWORD( ( (0xd<<6) | ((b) << 3) | 7), 0, (a)) /* adda.l */
371 #define M_ASUBINT(a,b) OPWORD( ( (0x9<<6) | ((b) << 3) | 7), 0, (a)) /* suba.l */
373 /* immideate a shift left int register b, immideate has 3 bits */
374 #define M_ISSL_IMM(a,b) OPWORD_ASSERT( ((a)<=7), ( (0xe<<6) | ((a) << 3) | 6), 1, (b)) /* lsl */
375 #define M_ISSR_IMM(a,b) OPWORD_ASSERT( ((a)<=7), ( (0xe<<6) | ((a) << 3) | 2), 0, (b)) /* lsl */
376 #define M_IUSR_IMM(a,b) OPWORD_ASSERT( ((a)<=7), ( (0xe<<6) | ((a) << 3) | 2), 1, (b)) /* lsl */
379 /* constant handling */
380 /* XCONST(constant value, register) */
381 #define LCONST(a,b) do {\
382 M_IMOV_IMM(((uint32_t)(a)), GET_LOW_REG((b)));\
383 M_IMOV_IMM(((uint32_t)(a>>32)), GET_HIGH_REG((b)));\
386 #if !defined(ENABLE_SOFTFLOAT)
387 #define FCONST(a,b) M_ILLEGAL
388 #define DCONST(a,b) M_ILLEGAL
391 #define M_TRAP_SETREGISTER(a) OPWORD( 0x128, 0, (a)) /* tst.b */
394 *((u2*)cd->mcodeptr) = (u2) ( 0x4e40 | (a) ); \
398 #endif /* _CODEGEN_H */