1 /* src/vm/jit/i386/emit.c - i386 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
34 #include "vm/jit/i386/codegen.h"
35 #include "vm/jit/i386/emit.h"
36 #include "vm/jit/i386/md-abi.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/builtin.h"
43 #include "vm/exceptions.h"
45 #include "vm/jit/abi.h"
46 #include "vm/jit/asmpart.h"
47 #include "vm/jit/dseg.h"
48 #include "vm/jit/emit-common.h"
49 #include "vm/jit/jit.h"
50 #include "vm/jit/replace.h"
52 #include "vmcore/options.h"
53 #include "vmcore/statistics.h"
56 /* emit_load ******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 inline s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff;
80 M_ILD(tempreg, REG_SP, disp);
83 M_LLD(tempreg, REG_SP, disp);
86 M_FLD(tempreg, REG_SP, disp);
89 M_DLD(tempreg, REG_SP, disp);
92 vm_abort("emit_load: unknown type %d", src->type);
104 /* emit_load_low ************************************************************
106 Emits a possible load of the low 32-bits of an operand.
108 *******************************************************************************/
110 inline s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src,s4 tempreg)
116 assert(src->type == TYPE_LNG);
118 /* get required compiler data */
123 if (IS_INMEMORY(src->flags)) {
126 disp = src->vv.regoff;
128 M_ILD(tempreg, REG_SP, disp);
133 reg = GET_LOW_REG(src->vv.regoff);
139 /* emit_load_high ***********************************************************
141 Emits a possible load of the high 32-bits of an operand.
143 *******************************************************************************/
145 inline s4 emit_load_high(jitdata *jd, instruction *iptr,varinfo *src,s4 tempreg)
151 /* get required compiler data */
153 assert(src->type == TYPE_LNG);
157 if (IS_INMEMORY(src->flags)) {
160 disp = src->vv.regoff;
162 M_ILD(tempreg, REG_SP, disp + 4);
167 reg = GET_HIGH_REG(src->vv.regoff);
173 /* emit_store ******************************************************************
175 Emits a possible store of the destination operand.
177 *******************************************************************************/
179 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
184 /* get required compiler data */
188 if (IS_INMEMORY(dst->flags)) {
191 disp = dst->vv.regoff;
196 M_IST(d, REG_SP, disp);
199 M_LST(d, REG_SP, disp);
202 M_FST(d, REG_SP, disp);
205 M_DST(d, REG_SP, disp);
208 vm_abort("emit_store: unknown type %d", dst->type);
214 /* emit_store_low **************************************************************
216 Emits a possible store of the low 32-bits of the destination
219 *******************************************************************************/
221 inline void emit_store_low(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
225 assert(dst->type == TYPE_LNG);
227 /* get required compiler data */
231 if (IS_INMEMORY(dst->flags)) {
233 M_IST(GET_LOW_REG(d), REG_SP, dst->vv.regoff);
238 /* emit_store_high *************************************************************
240 Emits a possible store of the high 32-bits of the destination
243 *******************************************************************************/
245 inline void emit_store_high(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
249 assert(dst->type == TYPE_LNG);
251 /* get required compiler data */
255 if (IS_INMEMORY(dst->flags)) {
257 M_IST(GET_HIGH_REG(d), REG_SP, dst->vv.regoff + 4);
262 /* emit_copy *******************************************************************
264 Generates a register/memory to register/memory copy.
266 *******************************************************************************/
268 void emit_copy(jitdata *jd, instruction *iptr)
275 /* get required compiler data */
279 /* get source and destination variables */
281 src = VAROP(iptr->s1);
282 dst = VAROP(iptr->dst);
284 if ((src->vv.regoff != dst->vv.regoff) ||
285 ((src->flags ^ dst->flags) & INMEMORY)) {
287 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
288 /* emit nothing, as the value won't be used anyway */
292 /* If one of the variables resides in memory, we can eliminate
293 the register move from/to the temporary register with the
294 order of getting the destination register and the load. */
296 if (IS_INMEMORY(src->flags)) {
297 if (IS_LNG_TYPE(src->type))
298 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
300 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
302 s1 = emit_load(jd, iptr, src, d);
305 if (IS_LNG_TYPE(src->type))
306 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
308 s1 = emit_load(jd, iptr, src, REG_ITMP1);
310 d = codegen_reg_of_var(iptr->opc, dst, s1);
327 vm_abort("emit_copy: unknown type %d", src->type);
331 emit_store(jd, iptr, dst, d);
336 /* emit_branch *****************************************************************
338 Emits the code for conditional and unconditional branchs.
340 *******************************************************************************/
342 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
346 /* ATTENTION: a displacement overflow cannot happen */
348 /* check which branch to generate */
350 if (condition == BRANCH_UNCONDITIONAL) {
352 /* calculate the different displacements */
354 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
356 M_JMP_IMM(branchdisp);
359 /* calculate the different displacements */
361 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
395 vm_abort("emit_branch: unknown condition %d", condition);
401 /* emit_arithmetic_check *******************************************************
403 Emit an ArithmeticException check.
405 *******************************************************************************/
407 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
409 if (INSTRUCTION_MUST_CHECK(iptr)) {
412 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
417 /* emit_arrayindexoutofbounds_check ********************************************
419 Emit a ArrayIndexOutOfBoundsException check.
421 *******************************************************************************/
423 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
425 if (INSTRUCTION_MUST_CHECK(iptr)) {
426 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
427 M_CMP(REG_ITMP3, s2);
429 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
434 /* emit_classcast_check ********************************************************
436 Emit a ClassCastException check.
438 *******************************************************************************/
440 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
442 if (INSTRUCTION_MUST_CHECK(iptr)) {
454 vm_abort("emit_classcast_check: unknown condition %d", condition);
456 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
461 /* emit_nullpointer_check ******************************************************
463 Emit a NullPointerException check.
465 *******************************************************************************/
467 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
469 if (INSTRUCTION_MUST_CHECK(iptr)) {
472 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
477 /* emit_exception_check ********************************************************
479 Emit an Exception check.
481 *******************************************************************************/
483 void emit_exception_check(codegendata *cd, instruction *iptr)
485 if (INSTRUCTION_MUST_CHECK(iptr)) {
488 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
493 /* emit_patcher_stubs **********************************************************
495 Generates the code for the patcher stubs.
497 *******************************************************************************/
499 void emit_patcher_stubs(jitdata *jd)
509 /* get required compiler data */
513 /* generate code patching stub call code */
517 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
518 /* check code segment size */
522 /* Get machine code which is patched back in later. A
523 `call rel32' is 5 bytes long. */
525 savedmcodeptr = cd->mcodebase + pref->branchpos;
526 mcode = *((u8 *) savedmcodeptr);
528 /* patch in `call rel32' to call the following code */
530 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
531 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
533 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
535 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
541 /* move pointer to java_objectheader onto stack */
543 #if defined(ENABLE_THREADS)
544 (void) dseg_add_unique_address(cd, NULL); /* flcword */
545 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
546 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
548 M_MOV_IMM(0, REG_ITMP3);
550 M_AADD_IMM(disp, REG_ITMP3);
556 /* move machine code bytes and classinfo pointer into registers */
558 M_PUSH_IMM(mcode >> 32);
560 M_PUSH_IMM(pref->ref);
561 M_PUSH_IMM(pref->patcher);
563 if (targetdisp == 0) {
564 targetdisp = cd->mcodeptr - cd->mcodebase;
566 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
570 M_JMP_IMM((cd->mcodebase + targetdisp) -
571 (cd->mcodeptr + PATCHER_CALL_SIZE));
577 /* emit_trap *******************************************************************
579 Emit a trap instruction and return the original machine code.
581 *******************************************************************************/
583 uint32_t emit_trap(codegendata *cd)
587 /* Get machine code which is patched back in later. The
588 trap is 1 instruction word long. */
590 mcode = *((uint32_t *) cd->mcodeptr);
598 /* emit_verbosecall_enter ******************************************************
600 Generates the code for the call trace.
602 *******************************************************************************/
605 void emit_verbosecall_enter(jitdata *jd)
615 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
618 /* get required compiler data */
626 /* mark trace code */
630 /* methodinfo* + arguments + return address */
632 disp = (TRACE_ARGS_NUM + 1 + TMP_CNT) * 8 + cd->stackframesize * 8 + 4;
634 M_ASUB_IMM((TRACE_ARGS_NUM + 1 + TMP_CNT) * 8, REG_SP);
636 /* save temporary registers for leaf methods */
638 for (i = 0; i < INT_TMP_CNT; i++)
639 M_IST(rd->tmpintregs[i], REG_SP, (TRACE_ARGS_NUM + 1 + i) * 8);
641 /* save argument registers */
643 for (i = 0; i < md->paramcount; i++) {
646 switch (md->paramtypes[i].type) {
648 M_ILD(EAX, REG_SP, disp);
650 M_LST(EAX_EDX_PACKED, REG_SP, d);
653 M_LLD(REG_ITMP12_PACKED, REG_SP, disp);
654 M_LST(REG_ITMP12_PACKED, REG_SP, d);
657 M_ALD(REG_ITMP1, REG_SP, disp);
658 M_AST(REG_ITMP1, REG_SP, d);
659 M_IST_IMM(0, REG_SP, d + 4); /* high-bits are zero */
662 M_FLD(REG_NULL, REG_SP, disp);
663 M_FST(REG_NULL, REG_SP, d);
664 M_IST_IMM(0, REG_SP, d + 4); /* high-bits are zero */
667 M_DLD(REG_NULL, REG_SP, disp);
668 M_DST(REG_NULL, REG_SP, d);
675 M_AST_IMM(m, REG_SP, TRACE_ARGS_NUM * 8);
677 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
680 /* restore temporary registers for leaf methods */
682 for (i = 0; i < INT_TMP_CNT; i++)
683 M_ILD(rd->tmpintregs[i], REG_SP, (TRACE_ARGS_NUM + 1 + i) * 8);
685 M_AADD_IMM((TRACE_ARGS_NUM + 1 + TMP_CNT) * 8, REG_SP);
687 /* mark trace code */
691 #endif /* !defined(NDEBUG) */
694 /* emit_verbosecall_exit *******************************************************
696 Generates the code for the call trace.
698 void builtin_verbosecall_exit(s8 l, double d, float f, methodinfo *m);
700 *******************************************************************************/
703 void emit_verbosecall_exit(jitdata *jd)
709 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
712 /* get required compiler data */
718 /* mark trace code */
722 M_ASUB_IMM(8 + 8 + 4 + 4 + 8, REG_SP); /* +8: keep stack 16-byte aligned */
724 M_LST(REG_RESULT_PACKED, REG_SP, 0 * 8);
726 M_DSTNP(REG_NULL, REG_SP, 1 * 8);
727 M_FSTNP(REG_NULL, REG_SP, 2 * 8);
729 M_AST_IMM(m, REG_SP, 2 * 8 + 1 * 4);
731 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
734 M_LLD(REG_RESULT_PACKED, REG_SP, 0 * 4);
736 M_AADD_IMM(8 + 8 + 4 + 4 + 8, REG_SP);
738 /* mark trace code */
742 #endif /* !defined(NDEBUG) */
745 /* code generation functions **************************************************/
747 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
749 if (basereg == ESP) {
751 emit_address_byte(0, dreg, ESP);
752 emit_address_byte(0, ESP, ESP);
754 else if (IS_IMM8(disp)) {
755 emit_address_byte(1, dreg, ESP);
756 emit_address_byte(0, ESP, ESP);
760 emit_address_byte(2, dreg, ESP);
761 emit_address_byte(0, ESP, ESP);
765 else if ((disp == 0) && (basereg != EBP)) {
766 emit_address_byte(0, dreg, basereg);
768 else if (IS_IMM8(disp)) {
769 emit_address_byte(1, dreg, basereg);
773 emit_address_byte(2, dreg, basereg);
779 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
781 if (basereg == ESP) {
782 emit_address_byte(2, dreg, ESP);
783 emit_address_byte(0, ESP, ESP);
787 emit_address_byte(2, dreg, basereg);
793 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
796 emit_address_byte(0, reg, 4);
797 emit_address_byte(scale, indexreg, 5);
800 else if ((disp == 0) && (basereg != EBP)) {
801 emit_address_byte(0, reg, 4);
802 emit_address_byte(scale, indexreg, basereg);
804 else if (IS_IMM8(disp)) {
805 emit_address_byte(1, reg, 4);
806 emit_address_byte(scale, indexreg, basereg);
810 emit_address_byte(2, reg, 4);
811 emit_address_byte(scale, indexreg, basereg);
817 /* low-level code emitter functions *******************************************/
819 void emit_mov_reg_reg(codegendata *cd, s4 reg, s4 dreg)
821 COUNT(count_mov_reg_reg);
822 *(cd->mcodeptr++) = 0x89;
823 emit_reg((reg),(dreg));
827 void emit_mov_imm_reg(codegendata *cd, s4 imm, s4 reg)
829 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
834 void emit_movb_imm_reg(codegendata *cd, s4 imm, s4 reg)
836 *(cd->mcodeptr++) = 0xc6;
842 void emit_mov_membase_reg(codegendata *cd, s4 basereg, s4 disp, s4 reg)
844 COUNT(count_mov_mem_reg);
845 *(cd->mcodeptr++) = 0x8b;
846 emit_membase(cd, (basereg),(disp),(reg));
851 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
852 * constant membase immediate length of 32bit
854 void emit_mov_membase32_reg(codegendata *cd, s4 basereg, s4 disp, s4 reg)
856 COUNT(count_mov_mem_reg);
857 *(cd->mcodeptr++) = 0x8b;
858 emit_membase32(cd, (basereg),(disp),(reg));
862 void emit_mov_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
864 COUNT(count_mov_reg_mem);
865 *(cd->mcodeptr++) = 0x89;
866 emit_membase(cd, (basereg),(disp),(reg));
870 void emit_mov_reg_membase32(codegendata *cd, s4 reg, s4 basereg, s4 disp)
872 COUNT(count_mov_reg_mem);
873 *(cd->mcodeptr++) = 0x89;
874 emit_membase32(cd, (basereg),(disp),(reg));
878 void emit_mov_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
880 COUNT(count_mov_mem_reg);
881 *(cd->mcodeptr++) = 0x8b;
882 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
886 void emit_mov_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
888 COUNT(count_mov_reg_mem);
889 *(cd->mcodeptr++) = 0x89;
890 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
894 void emit_movw_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
896 COUNT(count_mov_reg_mem);
897 *(cd->mcodeptr++) = 0x66;
898 *(cd->mcodeptr++) = 0x89;
899 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
903 void emit_movb_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
905 COUNT(count_mov_reg_mem);
906 *(cd->mcodeptr++) = 0x88;
907 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
911 void emit_mov_reg_mem(codegendata *cd, s4 reg, s4 mem)
913 COUNT(count_mov_reg_mem);
914 *(cd->mcodeptr++) = 0x89;
915 emit_mem((reg),(mem));
919 void emit_mov_mem_reg(codegendata *cd, s4 mem, s4 dreg)
921 COUNT(count_mov_mem_reg);
922 *(cd->mcodeptr++) = 0x8b;
923 emit_mem((dreg),(mem));
927 void emit_mov_imm_mem(codegendata *cd, s4 imm, s4 mem)
929 *(cd->mcodeptr++) = 0xc7;
935 void emit_mov_imm_membase(codegendata *cd, s4 imm, s4 basereg, s4 disp)
937 *(cd->mcodeptr++) = 0xc7;
938 emit_membase(cd, (basereg),(disp),0);
943 void emit_mov_imm_membase32(codegendata *cd, s4 imm, s4 basereg, s4 disp)
945 *(cd->mcodeptr++) = 0xc7;
946 emit_membase32(cd, (basereg),(disp),0);
951 void emit_movb_imm_membase(codegendata *cd, s4 imm, s4 basereg, s4 disp)
953 *(cd->mcodeptr++) = 0xc6;
954 emit_membase(cd, (basereg),(disp),0);
959 void emit_movsbl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
961 COUNT(count_mov_mem_reg);
962 *(cd->mcodeptr++) = 0x0f;
963 *(cd->mcodeptr++) = 0xbe;
964 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
968 void emit_movswl_reg_reg(codegendata *cd, s4 a, s4 b)
970 *(cd->mcodeptr++) = 0x0f;
971 *(cd->mcodeptr++) = 0xbf;
976 void emit_movswl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
978 COUNT(count_mov_mem_reg);
979 *(cd->mcodeptr++) = 0x0f;
980 *(cd->mcodeptr++) = 0xbf;
981 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
985 void emit_movzwl_reg_reg(codegendata *cd, s4 a, s4 b)
987 *(cd->mcodeptr++) = 0x0f;
988 *(cd->mcodeptr++) = 0xb7;
993 void emit_movzwl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
995 COUNT(count_mov_mem_reg);
996 *(cd->mcodeptr++) = 0x0f;
997 *(cd->mcodeptr++) = 0xb7;
998 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1002 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1004 *(cd->mcodeptr++) = 0xc7;
1005 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1010 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1012 *(cd->mcodeptr++) = 0x66;
1013 *(cd->mcodeptr++) = 0xc7;
1014 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1019 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1021 *(cd->mcodeptr++) = 0xc6;
1022 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1030 void emit_alu_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1032 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 1;
1033 emit_reg((reg),(dreg));
1037 void emit_alu_reg_membase(codegendata *cd, s4 opc, s4 reg, s4 basereg, s4 disp)
1039 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 1;
1040 emit_membase(cd, (basereg),(disp),(reg));
1044 void emit_alu_membase_reg(codegendata *cd, s4 opc, s4 basereg, s4 disp, s4 reg)
1046 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 3;
1047 emit_membase(cd, (basereg),(disp),(reg));
1051 void emit_alu_imm_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1054 *(cd->mcodeptr++) = 0x83;
1055 emit_reg((opc),(dreg));
1058 *(cd->mcodeptr++) = 0x81;
1059 emit_reg((opc),(dreg));
1065 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1067 *(cd->mcodeptr++) = 0x81;
1068 emit_reg((opc),(dreg));
1073 void emit_alu_imm_membase(codegendata *cd, s4 opc, s4 imm, s4 basereg, s4 disp)
1076 *(cd->mcodeptr++) = 0x83;
1077 emit_membase(cd, (basereg),(disp),(opc));
1080 *(cd->mcodeptr++) = 0x81;
1081 emit_membase(cd, (basereg),(disp),(opc));
1087 void emit_alu_imm_memabs(codegendata *cd, s4 opc, s4 imm, s4 disp)
1090 *(cd->mcodeptr++) = 0x83;
1091 emit_mem(opc, disp);
1094 *(cd->mcodeptr++) = 0x81;
1095 emit_mem(opc, disp);
1101 void emit_test_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1103 *(cd->mcodeptr++) = 0x85;
1104 emit_reg((reg),(dreg));
1108 void emit_test_imm_reg(codegendata *cd, s4 imm, s4 reg)
1110 *(cd->mcodeptr++) = 0xf7;
1118 * inc, dec operations
1120 void emit_dec_mem(codegendata *cd, s4 mem)
1122 *(cd->mcodeptr++) = 0xff;
1127 void emit_cltd(codegendata *cd)
1129 *(cd->mcodeptr++) = 0x99;
1133 void emit_imul_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1135 *(cd->mcodeptr++) = 0x0f;
1136 *(cd->mcodeptr++) = 0xaf;
1137 emit_reg((dreg),(reg));
1141 void emit_imul_membase_reg(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
1143 *(cd->mcodeptr++) = 0x0f;
1144 *(cd->mcodeptr++) = 0xaf;
1145 emit_membase(cd, (basereg),(disp),(dreg));
1149 void emit_imul_imm_reg(codegendata *cd, s4 imm, s4 dreg)
1151 if (IS_IMM8((imm))) {
1152 *(cd->mcodeptr++) = 0x6b;
1156 *(cd->mcodeptr++) = 0x69;
1163 void emit_imul_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1165 if (IS_IMM8((imm))) {
1166 *(cd->mcodeptr++) = 0x6b;
1167 emit_reg((dreg),(reg));
1170 *(cd->mcodeptr++) = 0x69;
1171 emit_reg((dreg),(reg));
1177 void emit_imul_imm_membase_reg(codegendata *cd, s4 imm, s4 basereg, s4 disp, s4 dreg)
1179 if (IS_IMM8((imm))) {
1180 *(cd->mcodeptr++) = 0x6b;
1181 emit_membase(cd, (basereg),(disp),(dreg));
1184 *(cd->mcodeptr++) = 0x69;
1185 emit_membase(cd, (basereg),(disp),(dreg));
1191 void emit_mul_reg(codegendata *cd, s4 reg)
1193 *(cd->mcodeptr++) = 0xf7;
1198 void emit_mul_membase(codegendata *cd, s4 basereg, s4 disp)
1200 *(cd->mcodeptr++) = 0xf7;
1201 emit_membase(cd, (basereg),(disp),4);
1205 void emit_idiv_reg(codegendata *cd, s4 reg)
1207 *(cd->mcodeptr++) = 0xf7;
1212 void emit_ret(codegendata *cd)
1214 *(cd->mcodeptr++) = 0xc3;
1222 void emit_shift_reg(codegendata *cd, s4 opc, s4 reg)
1224 *(cd->mcodeptr++) = 0xd3;
1225 emit_reg((opc),(reg));
1229 void emit_shift_imm_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1232 *(cd->mcodeptr++) = 0xd1;
1233 emit_reg((opc),(dreg));
1235 *(cd->mcodeptr++) = 0xc1;
1236 emit_reg((opc),(dreg));
1242 void emit_shld_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1244 *(cd->mcodeptr++) = 0x0f;
1245 *(cd->mcodeptr++) = 0xa5;
1246 emit_reg((reg),(dreg));
1250 void emit_shld_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1252 *(cd->mcodeptr++) = 0x0f;
1253 *(cd->mcodeptr++) = 0xa4;
1254 emit_reg((reg),(dreg));
1259 void emit_shld_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1261 *(cd->mcodeptr++) = 0x0f;
1262 *(cd->mcodeptr++) = 0xa5;
1263 emit_membase(cd, (basereg),(disp),(reg));
1267 void emit_shrd_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1269 *(cd->mcodeptr++) = 0x0f;
1270 *(cd->mcodeptr++) = 0xad;
1271 emit_reg((reg),(dreg));
1275 void emit_shrd_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1277 *(cd->mcodeptr++) = 0x0f;
1278 *(cd->mcodeptr++) = 0xac;
1279 emit_reg((reg),(dreg));
1284 void emit_shrd_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1286 *(cd->mcodeptr++) = 0x0f;
1287 *(cd->mcodeptr++) = 0xad;
1288 emit_membase(cd, (basereg),(disp),(reg));
1296 void emit_jmp_imm(codegendata *cd, s4 imm)
1298 *(cd->mcodeptr++) = 0xe9;
1303 void emit_jmp_reg(codegendata *cd, s4 reg)
1305 *(cd->mcodeptr++) = 0xff;
1310 void emit_jcc(codegendata *cd, s4 opc, s4 imm)
1312 *(cd->mcodeptr++) = 0x0f;
1313 *(cd->mcodeptr++) = 0x80 + (u1) (opc);
1320 * conditional set operations
1322 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1324 *(cd->mcodeptr++) = 0x0f;
1325 *(cd->mcodeptr++) = 0x90 + (u1) (opc);
1330 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1332 *(cd->mcodeptr++) = 0x0f;
1333 *(cd->mcodeptr++) = 0x90 + (u1) (opc);
1334 emit_membase(cd, (basereg),(disp),0);
1338 void emit_xadd_reg_mem(codegendata *cd, s4 reg, s4 mem)
1340 *(cd->mcodeptr++) = 0x0f;
1341 *(cd->mcodeptr++) = 0xc1;
1342 emit_mem((reg),(mem));
1346 void emit_neg_reg(codegendata *cd, s4 reg)
1348 *(cd->mcodeptr++) = 0xf7;
1354 void emit_push_imm(codegendata *cd, s4 imm)
1356 *(cd->mcodeptr++) = 0x68;
1361 void emit_pop_reg(codegendata *cd, s4 reg)
1363 *(cd->mcodeptr++) = 0x58 + (0x07 & (u1) (reg));
1367 void emit_push_reg(codegendata *cd, s4 reg)
1369 *(cd->mcodeptr++) = 0x50 + (0x07 & (u1) (reg));
1373 void emit_nop(codegendata *cd)
1375 *(cd->mcodeptr++) = 0x90;
1379 void emit_lock(codegendata *cd)
1381 *(cd->mcodeptr++) = 0xf0;
1388 void emit_call_reg(codegendata *cd, s4 reg)
1390 *(cd->mcodeptr++) = 0xff;
1395 void emit_call_imm(codegendata *cd, s4 imm)
1397 *(cd->mcodeptr++) = 0xe8;
1404 * floating point instructions
1406 void emit_fld1(codegendata *cd)
1408 *(cd->mcodeptr++) = 0xd9;
1409 *(cd->mcodeptr++) = 0xe8;
1413 void emit_fldz(codegendata *cd)
1415 *(cd->mcodeptr++) = 0xd9;
1416 *(cd->mcodeptr++) = 0xee;
1420 void emit_fld_reg(codegendata *cd, s4 reg)
1422 *(cd->mcodeptr++) = 0xd9;
1423 *(cd->mcodeptr++) = 0xc0 + (0x07 & (u1) (reg));
1427 void emit_flds_membase(codegendata *cd, s4 basereg, s4 disp)
1429 *(cd->mcodeptr++) = 0xd9;
1430 emit_membase(cd, (basereg),(disp),0);
1434 void emit_flds_membase32(codegendata *cd, s4 basereg, s4 disp)
1436 *(cd->mcodeptr++) = 0xd9;
1437 emit_membase32(cd, (basereg),(disp),0);
1441 void emit_fldl_membase(codegendata *cd, s4 basereg, s4 disp)
1443 *(cd->mcodeptr++) = 0xdd;
1444 emit_membase(cd, (basereg),(disp),0);
1448 void emit_fldl_membase32(codegendata *cd, s4 basereg, s4 disp)
1450 *(cd->mcodeptr++) = 0xdd;
1451 emit_membase32(cd, (basereg),(disp),0);
1455 void emit_fldt_membase(codegendata *cd, s4 basereg, s4 disp)
1457 *(cd->mcodeptr++) = 0xdb;
1458 emit_membase(cd, (basereg),(disp),5);
1462 void emit_flds_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1464 *(cd->mcodeptr++) = 0xd9;
1465 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1469 void emit_fldl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1471 *(cd->mcodeptr++) = 0xdd;
1472 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1476 void emit_flds_mem(codegendata *cd, s4 mem)
1478 *(cd->mcodeptr++) = 0xd9;
1483 void emit_fldl_mem(codegendata *cd, s4 mem)
1485 *(cd->mcodeptr++) = 0xdd;
1490 void emit_fildl_membase(codegendata *cd, s4 basereg, s4 disp)
1492 *(cd->mcodeptr++) = 0xdb;
1493 emit_membase(cd, (basereg),(disp),0);
1497 void emit_fildll_membase(codegendata *cd, s4 basereg, s4 disp)
1499 *(cd->mcodeptr++) = 0xdf;
1500 emit_membase(cd, (basereg),(disp),5);
1504 void emit_fst_reg(codegendata *cd, s4 reg)
1506 *(cd->mcodeptr++) = 0xdd;
1507 *(cd->mcodeptr++) = 0xd0 + (0x07 & (u1) (reg));
1511 void emit_fsts_membase(codegendata *cd, s4 basereg, s4 disp)
1513 *(cd->mcodeptr++) = 0xd9;
1514 emit_membase(cd, (basereg),(disp),2);
1518 void emit_fstl_membase(codegendata *cd, s4 basereg, s4 disp)
1520 *(cd->mcodeptr++) = 0xdd;
1521 emit_membase(cd, (basereg),(disp),2);
1525 void emit_fsts_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1527 *(cd->mcodeptr++) = 0xd9;
1528 emit_memindex(cd, 2,(disp),(basereg),(indexreg),(scale));
1532 void emit_fstl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1534 *(cd->mcodeptr++) = 0xdd;
1535 emit_memindex(cd, 2,(disp),(basereg),(indexreg),(scale));
1539 void emit_fstp_reg(codegendata *cd, s4 reg)
1541 *(cd->mcodeptr++) = 0xdd;
1542 *(cd->mcodeptr++) = 0xd8 + (0x07 & (u1) (reg));
1546 void emit_fstps_membase(codegendata *cd, s4 basereg, s4 disp)
1548 *(cd->mcodeptr++) = 0xd9;
1549 emit_membase(cd, (basereg),(disp),3);
1553 void emit_fstps_membase32(codegendata *cd, s4 basereg, s4 disp)
1555 *(cd->mcodeptr++) = 0xd9;
1556 emit_membase32(cd, (basereg),(disp),3);
1560 void emit_fstpl_membase(codegendata *cd, s4 basereg, s4 disp)
1562 *(cd->mcodeptr++) = 0xdd;
1563 emit_membase(cd, (basereg),(disp),3);
1567 void emit_fstpl_membase32(codegendata *cd, s4 basereg, s4 disp)
1569 *(cd->mcodeptr++) = 0xdd;
1570 emit_membase32(cd, (basereg),(disp),3);
1574 void emit_fstpt_membase(codegendata *cd, s4 basereg, s4 disp)
1576 *(cd->mcodeptr++) = 0xdb;
1577 emit_membase(cd, (basereg),(disp),7);
1581 void emit_fstps_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1583 *(cd->mcodeptr++) = 0xd9;
1584 emit_memindex(cd, 3,(disp),(basereg),(indexreg),(scale));
1588 void emit_fstpl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1590 *(cd->mcodeptr++) = 0xdd;
1591 emit_memindex(cd, 3,(disp),(basereg),(indexreg),(scale));
1595 void emit_fstps_mem(codegendata *cd, s4 mem)
1597 *(cd->mcodeptr++) = 0xd9;
1602 void emit_fstpl_mem(codegendata *cd, s4 mem)
1604 *(cd->mcodeptr++) = 0xdd;
1609 void emit_fistl_membase(codegendata *cd, s4 basereg, s4 disp)
1611 *(cd->mcodeptr++) = 0xdb;
1612 emit_membase(cd, (basereg),(disp),2);
1616 void emit_fistpl_membase(codegendata *cd, s4 basereg, s4 disp)
1618 *(cd->mcodeptr++) = 0xdb;
1619 emit_membase(cd, (basereg),(disp),3);
1623 void emit_fistpll_membase(codegendata *cd, s4 basereg, s4 disp)
1625 *(cd->mcodeptr++) = 0xdf;
1626 emit_membase(cd, (basereg),(disp),7);
1630 void emit_fchs(codegendata *cd)
1632 *(cd->mcodeptr++) = 0xd9;
1633 *(cd->mcodeptr++) = 0xe0;
1637 void emit_faddp(codegendata *cd)
1639 *(cd->mcodeptr++) = 0xde;
1640 *(cd->mcodeptr++) = 0xc1;
1644 void emit_fadd_reg_st(codegendata *cd, s4 reg)
1646 *(cd->mcodeptr++) = 0xd8;
1647 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1651 void emit_fadd_st_reg(codegendata *cd, s4 reg)
1653 *(cd->mcodeptr++) = 0xdc;
1654 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1658 void emit_faddp_st_reg(codegendata *cd, s4 reg)
1660 *(cd->mcodeptr++) = 0xde;
1661 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1665 void emit_fadds_membase(codegendata *cd, s4 basereg, s4 disp)
1667 *(cd->mcodeptr++) = 0xd8;
1668 emit_membase(cd, (basereg),(disp),0);
1672 void emit_faddl_membase(codegendata *cd, s4 basereg, s4 disp)
1674 *(cd->mcodeptr++) = 0xdc;
1675 emit_membase(cd, (basereg),(disp),0);
1679 void emit_fsub_reg_st(codegendata *cd, s4 reg)
1681 *(cd->mcodeptr++) = 0xd8;
1682 *(cd->mcodeptr++) = 0xe0 + (0x07 & (u1) (reg));
1686 void emit_fsub_st_reg(codegendata *cd, s4 reg)
1688 *(cd->mcodeptr++) = 0xdc;
1689 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1693 void emit_fsubp_st_reg(codegendata *cd, s4 reg)
1695 *(cd->mcodeptr++) = 0xde;
1696 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1700 void emit_fsubp(codegendata *cd)
1702 *(cd->mcodeptr++) = 0xde;
1703 *(cd->mcodeptr++) = 0xe9;
1707 void emit_fsubs_membase(codegendata *cd, s4 basereg, s4 disp)
1709 *(cd->mcodeptr++) = 0xd8;
1710 emit_membase(cd, (basereg),(disp),4);
1714 void emit_fsubl_membase(codegendata *cd, s4 basereg, s4 disp)
1716 *(cd->mcodeptr++) = 0xdc;
1717 emit_membase(cd, (basereg),(disp),4);
1721 void emit_fmul_reg_st(codegendata *cd, s4 reg)
1723 *(cd->mcodeptr++) = 0xd8;
1724 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1728 void emit_fmul_st_reg(codegendata *cd, s4 reg)
1730 *(cd->mcodeptr++) = 0xdc;
1731 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1735 void emit_fmulp(codegendata *cd)
1737 *(cd->mcodeptr++) = 0xde;
1738 *(cd->mcodeptr++) = 0xc9;
1742 void emit_fmulp_st_reg(codegendata *cd, s4 reg)
1744 *(cd->mcodeptr++) = 0xde;
1745 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1749 void emit_fmuls_membase(codegendata *cd, s4 basereg, s4 disp)
1751 *(cd->mcodeptr++) = 0xd8;
1752 emit_membase(cd, (basereg),(disp),1);
1756 void emit_fmull_membase(codegendata *cd, s4 basereg, s4 disp)
1758 *(cd->mcodeptr++) = 0xdc;
1759 emit_membase(cd, (basereg),(disp),1);
1763 void emit_fdiv_reg_st(codegendata *cd, s4 reg)
1765 *(cd->mcodeptr++) = 0xd8;
1766 *(cd->mcodeptr++) = 0xf0 + (0x07 & (u1) (reg));
1770 void emit_fdiv_st_reg(codegendata *cd, s4 reg)
1772 *(cd->mcodeptr++) = 0xdc;
1773 *(cd->mcodeptr++) = 0xf8 + (0x07 & (u1) (reg));
1777 void emit_fdivp(codegendata *cd)
1779 *(cd->mcodeptr++) = 0xde;
1780 *(cd->mcodeptr++) = 0xf9;
1784 void emit_fdivp_st_reg(codegendata *cd, s4 reg)
1786 *(cd->mcodeptr++) = 0xde;
1787 *(cd->mcodeptr++) = 0xf8 + (0x07 & (u1) (reg));
1791 void emit_fxch(codegendata *cd)
1793 *(cd->mcodeptr++) = 0xd9;
1794 *(cd->mcodeptr++) = 0xc9;
1798 void emit_fxch_reg(codegendata *cd, s4 reg)
1800 *(cd->mcodeptr++) = 0xd9;
1801 *(cd->mcodeptr++) = 0xc8 + (0x07 & (reg));
1805 void emit_fprem(codegendata *cd)
1807 *(cd->mcodeptr++) = 0xd9;
1808 *(cd->mcodeptr++) = 0xf8;
1812 void emit_fprem1(codegendata *cd)
1814 *(cd->mcodeptr++) = 0xd9;
1815 *(cd->mcodeptr++) = 0xf5;
1819 void emit_fucom(codegendata *cd)
1821 *(cd->mcodeptr++) = 0xdd;
1822 *(cd->mcodeptr++) = 0xe1;
1826 void emit_fucom_reg(codegendata *cd, s4 reg)
1828 *(cd->mcodeptr++) = 0xdd;
1829 *(cd->mcodeptr++) = 0xe0 + (0x07 & (u1) (reg));
1833 void emit_fucomp_reg(codegendata *cd, s4 reg)
1835 *(cd->mcodeptr++) = 0xdd;
1836 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1840 void emit_fucompp(codegendata *cd)
1842 *(cd->mcodeptr++) = 0xda;
1843 *(cd->mcodeptr++) = 0xe9;
1847 void emit_fnstsw(codegendata *cd)
1849 *(cd->mcodeptr++) = 0xdf;
1850 *(cd->mcodeptr++) = 0xe0;
1854 void emit_sahf(codegendata *cd)
1856 *(cd->mcodeptr++) = 0x9e;
1860 void emit_finit(codegendata *cd)
1862 *(cd->mcodeptr++) = 0x9b;
1863 *(cd->mcodeptr++) = 0xdb;
1864 *(cd->mcodeptr++) = 0xe3;
1868 void emit_fldcw_mem(codegendata *cd, s4 mem)
1870 *(cd->mcodeptr++) = 0xd9;
1875 void emit_fldcw_membase(codegendata *cd, s4 basereg, s4 disp)
1877 *(cd->mcodeptr++) = 0xd9;
1878 emit_membase(cd, (basereg),(disp),5);
1882 void emit_wait(codegendata *cd)
1884 *(cd->mcodeptr++) = 0x9b;
1888 void emit_ffree_reg(codegendata *cd, s4 reg)
1890 *(cd->mcodeptr++) = 0xdd;
1891 *(cd->mcodeptr++) = 0xc0 + (0x07 & (u1) (reg));
1895 void emit_fdecstp(codegendata *cd)
1897 *(cd->mcodeptr++) = 0xd9;
1898 *(cd->mcodeptr++) = 0xf6;
1902 void emit_fincstp(codegendata *cd)
1904 *(cd->mcodeptr++) = 0xd9;
1905 *(cd->mcodeptr++) = 0xf7;
1910 * These are local overrides for various environment variables in Emacs.
1911 * Please do not remove this and leave it at the end of the file, where
1912 * Emacs will automagically detect them.
1913 * ---------------------------------------------------------------------
1916 * indent-tabs-mode: t