1 /* src/vm/jit/i386/emit.c - i386 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007, 2008, 2009
4 CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 This file is part of CACAO.
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at
11 your option) any later version.
13 This program is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
33 #include "vm/jit/i386/codegen.h"
34 #include "vm/jit/i386/emit.h"
35 #include "vm/jit/i386/md-abi.h"
37 #include "mm/memory.hpp"
39 #include "threads/lock.hpp"
41 #include "vm/options.h"
42 #include "vm/statistics.h"
44 #include "vm/jit/abi.h"
45 #include "vm/jit/asmpart.h"
46 #include "vm/jit/dseg.h"
47 #include "vm/jit/emit-common.hpp"
48 #include "vm/jit/jit.hpp"
49 #include "vm/jit/patcher-common.hpp"
50 #include "vm/jit/replace.hpp"
51 #include "vm/jit/trace.hpp"
52 #include "vm/jit/trap.hpp"
55 /* emit_load ******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 inline s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
79 M_ILD(tempreg, REG_SP, disp);
82 M_LLD(tempreg, REG_SP, disp);
85 M_FLD(tempreg, REG_SP, disp);
88 M_DLD(tempreg, REG_SP, disp);
91 vm_abort("emit_load: unknown type %d", src->type);
103 /* emit_load_low ************************************************************
105 Emits a possible load of the low 32-bits of an operand.
107 *******************************************************************************/
109 inline s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src,s4 tempreg)
115 assert(src->type == TYPE_LNG);
117 /* get required compiler data */
122 if (IS_INMEMORY(src->flags)) {
125 disp = src->vv.regoff;
127 M_ILD(tempreg, REG_SP, disp);
132 reg = GET_LOW_REG(src->vv.regoff);
138 /* emit_load_high ***********************************************************
140 Emits a possible load of the high 32-bits of an operand.
142 *******************************************************************************/
144 inline s4 emit_load_high(jitdata *jd, instruction *iptr,varinfo *src,s4 tempreg)
150 /* get required compiler data */
152 assert(src->type == TYPE_LNG);
156 if (IS_INMEMORY(src->flags)) {
159 disp = src->vv.regoff;
161 M_ILD(tempreg, REG_SP, disp + 4);
166 reg = GET_HIGH_REG(src->vv.regoff);
172 /* emit_store ******************************************************************
174 Emits a possible store of the destination operand.
176 *******************************************************************************/
178 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
183 /* get required compiler data */
187 if (IS_INMEMORY(dst->flags)) {
190 disp = dst->vv.regoff;
195 M_IST(d, REG_SP, disp);
198 M_LST(d, REG_SP, disp);
201 M_FST(d, REG_SP, disp);
204 M_DST(d, REG_SP, disp);
207 vm_abort("emit_store: unknown type %d", dst->type);
213 /* emit_store_low **************************************************************
215 Emits a possible store of the low 32-bits of the destination
218 *******************************************************************************/
220 inline void emit_store_low(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
224 assert(dst->type == TYPE_LNG);
226 /* get required compiler data */
230 if (IS_INMEMORY(dst->flags)) {
232 M_IST(GET_LOW_REG(d), REG_SP, dst->vv.regoff);
237 /* emit_store_high *************************************************************
239 Emits a possible store of the high 32-bits of the destination
242 *******************************************************************************/
244 inline void emit_store_high(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
248 assert(dst->type == TYPE_LNG);
250 /* get required compiler data */
254 if (IS_INMEMORY(dst->flags)) {
256 M_IST(GET_HIGH_REG(d), REG_SP, dst->vv.regoff + 4);
261 /* emit_copy *******************************************************************
263 Generates a register/memory to register/memory copy.
265 *******************************************************************************/
267 void emit_copy(jitdata *jd, instruction *iptr)
274 /* get required compiler data */
278 /* get source and destination variables */
280 src = VAROP(iptr->s1);
281 dst = VAROP(iptr->dst);
283 if ((src->vv.regoff != dst->vv.regoff) ||
284 ((src->flags ^ dst->flags) & INMEMORY)) {
286 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
287 /* emit nothing, as the value won't be used anyway */
291 /* If one of the variables resides in memory, we can eliminate
292 the register move from/to the temporary register with the
293 order of getting the destination register and the load. */
295 if (IS_INMEMORY(src->flags)) {
296 if (IS_LNG_TYPE(src->type))
297 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
299 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
301 s1 = emit_load(jd, iptr, src, d);
304 if (IS_LNG_TYPE(src->type))
305 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
307 s1 = emit_load(jd, iptr, src, REG_ITMP1);
309 d = codegen_reg_of_var(iptr->opc, dst, s1);
326 vm_abort("emit_copy: unknown type %d", src->type);
330 emit_store(jd, iptr, dst, d);
336 * Emits code updating the condition register by comparing one integer
337 * register to an immediate integer value.
339 void emit_icmp_imm(codegendata* cd, int reg, int32_t value)
341 M_CMP_IMM(value, reg);
345 /* emit_branch *****************************************************************
347 Emits the code for conditional and unconditional branchs.
349 *******************************************************************************/
351 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
355 /* ATTENTION: a displacement overflow cannot happen */
357 /* check which branch to generate */
359 if (condition == BRANCH_UNCONDITIONAL) {
361 /* calculate the different displacements */
363 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
365 M_JMP_IMM(branchdisp);
368 /* calculate the different displacements */
370 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
404 vm_abort("emit_branch: unknown condition %d", condition);
410 /* emit_arithmetic_check *******************************************************
412 Emit an ArithmeticException check.
414 *******************************************************************************/
416 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
418 if (INSTRUCTION_MUST_CHECK(iptr)) {
421 M_ALD_MEM(reg, TRAP_ArithmeticException);
426 /* emit_arrayindexoutofbounds_check ********************************************
428 Emit a ArrayIndexOutOfBoundsException check.
430 *******************************************************************************/
432 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
434 if (INSTRUCTION_MUST_CHECK(iptr)) {
435 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
436 M_CMP(REG_ITMP3, s2);
438 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
443 /* emit_arraystore_check *******************************************************
445 Emit an ArrayStoreException check.
447 *******************************************************************************/
449 void emit_arraystore_check(codegendata *cd, instruction *iptr)
451 if (INSTRUCTION_MUST_CHECK(iptr)) {
454 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
459 /* emit_classcast_check ********************************************************
461 Emit a ClassCastException check.
463 *******************************************************************************/
465 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
467 if (INSTRUCTION_MUST_CHECK(iptr)) {
485 vm_abort("emit_classcast_check: unknown condition %d", condition);
487 M_ALD_MEM(s1, TRAP_ClassCastException);
492 /* emit_nullpointer_check ******************************************************
494 Emit a NullPointerException check.
496 *******************************************************************************/
498 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
500 if (INSTRUCTION_MUST_CHECK(iptr)) {
503 M_ALD_MEM(reg, TRAP_NullPointerException);
508 /* emit_exception_check ********************************************************
510 Emit an Exception check.
512 *******************************************************************************/
514 void emit_exception_check(codegendata *cd, instruction *iptr)
516 if (INSTRUCTION_MUST_CHECK(iptr)) {
519 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
524 /* emit_trap_compiler **********************************************************
526 Emit a trap instruction which calls the JIT compiler.
528 *******************************************************************************/
530 void emit_trap_compiler(codegendata *cd)
532 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
535 /* emit_trap_countdown *********************************************************
537 Emit a countdown trap.
539 counter....absolute address of the counter variable
541 *******************************************************************************/
543 void emit_trap_countdown(codegendata *cd, s4 *counter)
545 M_ISUB_IMM_MEMABS(1, (s4) counter);
547 M_ALD_MEM(REG_METHODPTR, TRAP_COUNTDOWN);
550 /* emit_patcher_alignment ******************************************************
552 Emit NOP to ensure placement at an even address.
554 *******************************************************************************/
556 void emit_patcher_alignment(codegendata *cd)
558 if ((uintptr_t) cd->mcodeptr & 1)
563 /* emit_trap *******************************************************************
565 Emit a trap instruction and return the original machine code.
567 *******************************************************************************/
569 uint32_t emit_trap(codegendata *cd)
573 /* Get machine code which is patched back in later. The
574 trap is 2 bytes long. */
576 mcode = *((uint16_t *) cd->mcodeptr);
579 /* XXX this breaks GDB, so we disable it for now */
580 *(cd->mcodeptr++) = 0xcc;
586 return (uint32_t) mcode;
591 * Generates synchronization code to enter a monitor.
593 #if defined(ENABLE_THREADS)
594 void emit_monitor_enter(jitdata* jd, int32_t syncslot_offset)
598 // Get required compiler data.
599 methodinfo* m = jd->m;
600 codegendata* cd = jd->cd;
602 align_off = cd->stackframesize ? 4 : 0;
604 if (m->flags & ACC_STATIC) {
605 M_MOV_IMM(&m->clazz->object.header, REG_ITMP1);
608 M_ALD(REG_ITMP1, REG_SP, cd->stackframesize * 8 + 4 + align_off);
611 M_ALD_MEM(REG_ITMP1, TRAP_NullPointerException);
614 M_AST(REG_ITMP1, REG_SP, syncslot_offset);
615 M_AST(REG_ITMP1, REG_SP, 0 * 4);
616 M_MOV_IMM(LOCK_monitor_enter, REG_ITMP3);
623 * Generates synchronization code to leave a monitor.
625 #if defined(ENABLE_THREADS)
626 void emit_monitor_exit(jitdata* jd, int32_t syncslot_offset)
628 // Get required compiler data.
629 methodinfo* m = jd->m;
630 codegendata* cd = jd->cd;
632 M_ALD(REG_ITMP2, REG_SP, syncslot_offset);
634 /* we need to save the proper return value */
636 methoddesc* md = m->parseddesc;
638 switch (md->returntype.type) {
641 M_IST(REG_RESULT, REG_SP, syncslot_offset);
645 M_LST(REG_RESULT_PACKED, REG_SP, syncslot_offset);
649 emit_fstps_membase(cd, REG_SP, syncslot_offset);
653 emit_fstpl_membase(cd, REG_SP, syncslot_offset);
657 M_AST(REG_ITMP2, REG_SP, 0);
658 M_MOV_IMM(LOCK_monitor_exit, REG_ITMP3);
661 /* and now restore the proper return value */
663 switch (md->returntype.type) {
666 M_ILD(REG_RESULT, REG_SP, syncslot_offset);
670 M_LLD(REG_RESULT_PACKED, REG_SP, syncslot_offset);
674 emit_flds_membase(cd, REG_SP, syncslot_offset);
678 emit_fldl_membase(cd, REG_SP, syncslot_offset);
686 * Emit profiling code for method frequency counting.
688 #if defined(ENABLE_PROFILING)
689 void emit_profile_method(codegendata* cd, codeinfo* code)
691 M_MOV_IMM(code, REG_ITMP3);
692 M_IADD_IMM_MEMBASE(1, REG_ITMP3, OFFSET(codeinfo, frequency));
698 * Emit profiling code for basicblock frequency counting.
700 #if defined(ENABLE_PROFILING)
701 void emit_profile_basicblock(codegendata* cd, codeinfo* code, basicblock* bptr)
703 M_MOV_IMM(code->bbfrequency, REG_ITMP3);
704 M_IADD_IMM_MEMBASE(1, REG_ITMP3, bptr->nr * 4);
710 * Emit profiling code to start CPU cycle counting.
712 #if defined(ENABLE_PROFILING)
713 void emit_profile_cycle_start(codegendata* cd, codeinfo* code)
715 // XXX Not implemented yet!
721 * Emit profiling code to stop CPU cycle counting.
723 #if defined(ENABLE_PROFILING)
724 void emit_profile_cycle_stop(codegendata* cd, codeinfo* code)
726 // XXX Not implemented yet!
731 /* emit_verbosecall_enter ******************************************************
733 Generates the code for the call trace.
735 *******************************************************************************/
738 void emit_verbosecall_enter(jitdata *jd)
745 int32_t stackframesize;
747 int align_off; /* offset for alignment compensation */
749 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
752 /* get required compiler data */
761 /* mark trace code */
765 /* keep stack 16-byte aligned */
767 stackframesize = 2 + TMP_CNT;
768 ALIGN_2(stackframesize);
770 M_ASUB_IMM(stackframesize * 8, REG_SP);
772 /* save temporary registers for leaf methods */
774 if (code_is_leafmethod(code)) {
775 for (i = 0; i < INT_TMP_CNT; i++)
776 M_IST(rd->tmpintregs[i], REG_SP, (2 + i) * 8);
779 /* no argument registers to save */
781 align_off = cd->stackframesize ? 4 : 0;
782 M_AST_IMM(m, REG_SP, 0 * 4);
783 M_AST_IMM(0, REG_SP, 1 * 4);
784 M_AST(REG_SP, REG_SP, 2 * 4);
785 M_IADD_IMM_MEMBASE(stackframesize * 8 + cd->stackframesize * 8 + 4 + align_off, REG_SP, 2 * 4);
786 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
789 /* no argument registers to restore */
791 /* restore temporary registers for leaf methods */
793 if (code_is_leafmethod(code)) {
794 for (i = 0; i < INT_TMP_CNT; i++)
795 M_ILD(rd->tmpintregs[i], REG_SP, (2 + i) * 8);
798 M_AADD_IMM(stackframesize * 8, REG_SP);
800 /* mark trace code */
804 #endif /* !defined(NDEBUG) */
807 /* emit_verbosecall_exit *******************************************************
809 Generates the code for the call trace.
811 *******************************************************************************/
814 void emit_verbosecall_exit(jitdata *jd)
821 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
824 /* get required compiler data */
832 /* mark trace code */
836 /* keep stack 16-byte aligned */
838 M_ASUB_IMM(4 + 4 + 8, REG_SP);
840 /* save return value */
842 switch (md->returntype.type) {
845 M_IST(REG_RESULT, REG_SP, 2 * 4);
848 M_LST(REG_RESULT_PACKED, REG_SP, 2 * 4);
851 M_FSTNP(REG_NULL, REG_SP, 2 * 4);
854 M_DSTNP(REG_NULL, REG_SP, 2 * 4);
858 M_AST_IMM(m, REG_SP, 0 * 4);
859 M_AST(REG_SP, REG_SP, 1 * 4);
860 M_IADD_IMM_MEMBASE(2 * 4, REG_SP, 1 * 4);
861 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
864 /* restore return value */
866 switch (md->returntype.type) {
869 M_ILD(REG_RESULT, REG_SP, 2 * 4);
872 M_LLD(REG_RESULT_PACKED, REG_SP, 2 * 4);
876 M_AADD_IMM(4 + 4 + 8, REG_SP);
878 /* mark trace code */
882 #endif /* !defined(NDEBUG) */
885 /* code generation functions **************************************************/
887 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
889 if (basereg == ESP) {
891 emit_address_byte(0, dreg, ESP);
892 emit_address_byte(0, ESP, ESP);
894 else if (IS_IMM8(disp)) {
895 emit_address_byte(1, dreg, ESP);
896 emit_address_byte(0, ESP, ESP);
900 emit_address_byte(2, dreg, ESP);
901 emit_address_byte(0, ESP, ESP);
905 else if ((disp == 0) && (basereg != EBP)) {
906 emit_address_byte(0, dreg, basereg);
908 else if (IS_IMM8(disp)) {
909 emit_address_byte(1, dreg, basereg);
913 emit_address_byte(2, dreg, basereg);
919 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
921 if (basereg == ESP) {
922 emit_address_byte(2, dreg, ESP);
923 emit_address_byte(0, ESP, ESP);
927 emit_address_byte(2, dreg, basereg);
933 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
936 emit_address_byte(0, reg, 4);
937 emit_address_byte(scale, indexreg, 5);
940 else if ((disp == 0) && (basereg != EBP)) {
941 emit_address_byte(0, reg, 4);
942 emit_address_byte(scale, indexreg, basereg);
944 else if (IS_IMM8(disp)) {
945 emit_address_byte(1, reg, 4);
946 emit_address_byte(scale, indexreg, basereg);
950 emit_address_byte(2, reg, 4);
951 emit_address_byte(scale, indexreg, basereg);
957 /* low-level code emitter functions *******************************************/
959 void emit_mov_reg_reg(codegendata *cd, s4 reg, s4 dreg)
961 COUNT(count_mov_reg_reg);
962 *(cd->mcodeptr++) = 0x89;
963 emit_reg((reg),(dreg));
967 void emit_mov_imm_reg(codegendata *cd, s4 imm, s4 reg)
969 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
973 /* 2-byte opcode for use with patchers */
974 void emit_mov_imm2_reg(codegendata *cd, s4 imm, s4 reg)
976 *(cd->mcodeptr++) = 0xc7;
977 emit_address_byte(3, 0, reg);
983 void emit_movb_imm_reg(codegendata *cd, s4 imm, s4 reg)
985 *(cd->mcodeptr++) = 0xc6;
991 void emit_mov_membase_reg(codegendata *cd, s4 basereg, s4 disp, s4 reg)
993 COUNT(count_mov_mem_reg);
994 *(cd->mcodeptr++) = 0x8b;
995 emit_membase(cd, (basereg),(disp),(reg));
1000 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1001 * constant membase immediate length of 32bit
1003 void emit_mov_membase32_reg(codegendata *cd, s4 basereg, s4 disp, s4 reg)
1005 COUNT(count_mov_mem_reg);
1006 *(cd->mcodeptr++) = 0x8b;
1007 emit_membase32(cd, (basereg),(disp),(reg));
1011 void emit_mov_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1013 COUNT(count_mov_reg_mem);
1014 *(cd->mcodeptr++) = 0x89;
1015 emit_membase(cd, (basereg),(disp),(reg));
1019 void emit_mov_reg_membase32(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1021 COUNT(count_mov_reg_mem);
1022 *(cd->mcodeptr++) = 0x89;
1023 emit_membase32(cd, (basereg),(disp),(reg));
1027 void emit_mov_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1029 COUNT(count_mov_mem_reg);
1030 *(cd->mcodeptr++) = 0x8b;
1031 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1035 void emit_mov_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1037 COUNT(count_mov_reg_mem);
1038 *(cd->mcodeptr++) = 0x89;
1039 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1043 void emit_movw_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1045 COUNT(count_mov_reg_mem);
1046 *(cd->mcodeptr++) = 0x66;
1047 *(cd->mcodeptr++) = 0x89;
1048 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1052 void emit_movb_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1054 COUNT(count_mov_reg_mem);
1055 *(cd->mcodeptr++) = 0x88;
1056 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1060 void emit_mov_reg_mem(codegendata *cd, s4 reg, s4 mem)
1062 COUNT(count_mov_reg_mem);
1063 *(cd->mcodeptr++) = 0x89;
1064 emit_mem((reg),(mem));
1068 void emit_mov_mem_reg(codegendata *cd, s4 mem, s4 dreg)
1070 COUNT(count_mov_mem_reg);
1071 *(cd->mcodeptr++) = 0x8b;
1072 emit_mem((dreg),(mem));
1076 void emit_mov_imm_mem(codegendata *cd, s4 imm, s4 mem)
1078 *(cd->mcodeptr++) = 0xc7;
1084 void emit_mov_imm_membase(codegendata *cd, s4 imm, s4 basereg, s4 disp)
1086 *(cd->mcodeptr++) = 0xc7;
1087 emit_membase(cd, (basereg),(disp),0);
1092 void emit_mov_imm_membase32(codegendata *cd, s4 imm, s4 basereg, s4 disp)
1094 *(cd->mcodeptr++) = 0xc7;
1095 emit_membase32(cd, (basereg),(disp),0);
1100 void emit_movb_imm_membase(codegendata *cd, s4 imm, s4 basereg, s4 disp)
1102 *(cd->mcodeptr++) = 0xc6;
1103 emit_membase(cd, (basereg),(disp),0);
1108 void emit_movsbl_reg_reg(codegendata *cd, s4 a, s4 b)
1110 assert(a < 4); /* Can only operate on al, bl, cl, dl. */
1111 *(cd->mcodeptr++) = 0x0f;
1112 *(cd->mcodeptr++) = 0xbe;
1117 void emit_movsbl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1119 COUNT(count_mov_mem_reg);
1120 *(cd->mcodeptr++) = 0x0f;
1121 *(cd->mcodeptr++) = 0xbe;
1122 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1126 void emit_movswl_reg_reg(codegendata *cd, s4 a, s4 b)
1128 *(cd->mcodeptr++) = 0x0f;
1129 *(cd->mcodeptr++) = 0xbf;
1134 void emit_movswl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1136 COUNT(count_mov_mem_reg);
1137 *(cd->mcodeptr++) = 0x0f;
1138 *(cd->mcodeptr++) = 0xbf;
1139 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1143 void emit_movzbl_reg_reg(codegendata *cd, s4 a, s4 b)
1145 assert(a < 4); /* Can only operate on al, bl, cl, dl. */
1146 *(cd->mcodeptr++) = 0x0f;
1147 *(cd->mcodeptr++) = 0xb6;
1152 void emit_movzwl_reg_reg(codegendata *cd, s4 a, s4 b)
1154 *(cd->mcodeptr++) = 0x0f;
1155 *(cd->mcodeptr++) = 0xb7;
1160 void emit_movzwl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1162 COUNT(count_mov_mem_reg);
1163 *(cd->mcodeptr++) = 0x0f;
1164 *(cd->mcodeptr++) = 0xb7;
1165 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1169 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1171 *(cd->mcodeptr++) = 0xc7;
1172 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1177 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1179 *(cd->mcodeptr++) = 0x66;
1180 *(cd->mcodeptr++) = 0xc7;
1181 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1186 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1188 *(cd->mcodeptr++) = 0xc6;
1189 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1197 void emit_alu_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1199 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 1;
1200 emit_reg((reg),(dreg));
1204 void emit_alu_reg_membase(codegendata *cd, s4 opc, s4 reg, s4 basereg, s4 disp)
1206 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 1;
1207 emit_membase(cd, (basereg),(disp),(reg));
1211 void emit_alu_membase_reg(codegendata *cd, s4 opc, s4 basereg, s4 disp, s4 reg)
1213 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 3;
1214 emit_membase(cd, (basereg),(disp),(reg));
1218 void emit_alu_imm_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1221 *(cd->mcodeptr++) = 0x83;
1222 emit_reg((opc),(dreg));
1225 *(cd->mcodeptr++) = 0x81;
1226 emit_reg((opc),(dreg));
1232 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1234 *(cd->mcodeptr++) = 0x81;
1235 emit_reg((opc),(dreg));
1240 void emit_alu_imm_membase(codegendata *cd, s4 opc, s4 imm, s4 basereg, s4 disp)
1243 *(cd->mcodeptr++) = 0x83;
1244 emit_membase(cd, (basereg),(disp),(opc));
1247 *(cd->mcodeptr++) = 0x81;
1248 emit_membase(cd, (basereg),(disp),(opc));
1254 void emit_alu_imm_memabs(codegendata *cd, s4 opc, s4 imm, s4 disp)
1257 *(cd->mcodeptr++) = 0x83;
1258 emit_mem(opc, disp);
1261 *(cd->mcodeptr++) = 0x81;
1262 emit_mem(opc, disp);
1267 void emit_alu_memindex_reg(codegendata *cd, s4 opc, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1269 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 3;
1270 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1273 void emit_test_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1275 *(cd->mcodeptr++) = 0x85;
1276 emit_reg((reg),(dreg));
1280 void emit_test_imm_reg(codegendata *cd, s4 imm, s4 reg)
1282 *(cd->mcodeptr++) = 0xf7;
1290 * inc, dec operations
1292 void emit_inc_reg(codegendata *cd, s4 reg)
1294 *(cd->mcodeptr++) = 0xff;
1298 void emit_dec_mem(codegendata *cd, s4 mem)
1300 *(cd->mcodeptr++) = 0xff;
1305 void emit_imul_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1307 *(cd->mcodeptr++) = 0x0f;
1308 *(cd->mcodeptr++) = 0xaf;
1309 emit_reg((dreg),(reg));
1313 void emit_imul_membase_reg(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
1315 *(cd->mcodeptr++) = 0x0f;
1316 *(cd->mcodeptr++) = 0xaf;
1317 emit_membase(cd, (basereg),(disp),(dreg));
1321 void emit_imul_imm_reg(codegendata *cd, s4 imm, s4 dreg)
1323 if (IS_IMM8((imm))) {
1324 *(cd->mcodeptr++) = 0x6b;
1328 *(cd->mcodeptr++) = 0x69;
1335 void emit_imul_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1337 if (IS_IMM8((imm))) {
1338 *(cd->mcodeptr++) = 0x6b;
1339 emit_reg((dreg),(reg));
1342 *(cd->mcodeptr++) = 0x69;
1343 emit_reg((dreg),(reg));
1349 void emit_imul_imm_membase_reg(codegendata *cd, s4 imm, s4 basereg, s4 disp, s4 dreg)
1351 if (IS_IMM8((imm))) {
1352 *(cd->mcodeptr++) = 0x6b;
1353 emit_membase(cd, (basereg),(disp),(dreg));
1356 *(cd->mcodeptr++) = 0x69;
1357 emit_membase(cd, (basereg),(disp),(dreg));
1363 void emit_mul_reg(codegendata *cd, s4 reg)
1365 *(cd->mcodeptr++) = 0xf7;
1370 void emit_mul_membase(codegendata *cd, s4 basereg, s4 disp)
1372 *(cd->mcodeptr++) = 0xf7;
1373 emit_membase(cd, (basereg),(disp),4);
1377 void emit_idiv_reg(codegendata *cd, s4 reg)
1379 *(cd->mcodeptr++) = 0xf7;
1388 void emit_shift_reg(codegendata *cd, s4 opc, s4 reg)
1390 *(cd->mcodeptr++) = 0xd3;
1391 emit_reg((opc),(reg));
1395 void emit_shift_imm_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1398 *(cd->mcodeptr++) = 0xd1;
1399 emit_reg((opc),(dreg));
1401 *(cd->mcodeptr++) = 0xc1;
1402 emit_reg((opc),(dreg));
1408 void emit_shld_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1410 *(cd->mcodeptr++) = 0x0f;
1411 *(cd->mcodeptr++) = 0xa5;
1412 emit_reg((reg),(dreg));
1416 void emit_shld_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1418 *(cd->mcodeptr++) = 0x0f;
1419 *(cd->mcodeptr++) = 0xa4;
1420 emit_reg((reg),(dreg));
1425 void emit_shld_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1427 *(cd->mcodeptr++) = 0x0f;
1428 *(cd->mcodeptr++) = 0xa5;
1429 emit_membase(cd, (basereg),(disp),(reg));
1433 void emit_shrd_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1435 *(cd->mcodeptr++) = 0x0f;
1436 *(cd->mcodeptr++) = 0xad;
1437 emit_reg((reg),(dreg));
1441 void emit_shrd_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1443 *(cd->mcodeptr++) = 0x0f;
1444 *(cd->mcodeptr++) = 0xac;
1445 emit_reg((reg),(dreg));
1450 void emit_shrd_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1452 *(cd->mcodeptr++) = 0x0f;
1453 *(cd->mcodeptr++) = 0xad;
1454 emit_membase(cd, (basereg),(disp),(reg));
1462 void emit_jmp_imm(codegendata *cd, s4 imm)
1464 *(cd->mcodeptr++) = 0xe9;
1469 void emit_jmp_reg(codegendata *cd, s4 reg)
1471 *(cd->mcodeptr++) = 0xff;
1476 void emit_jcc(codegendata *cd, s4 opc, s4 imm)
1478 *(cd->mcodeptr++) = 0x0f;
1479 *(cd->mcodeptr++) = 0x80 + (u1) (opc);
1486 * conditional set operations
1488 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1490 assert(reg < 4); /* Can only operate on al, bl, cl, dl. */
1491 *(cd->mcodeptr++) = 0x0f;
1492 *(cd->mcodeptr++) = 0x90 + (u1) (opc);
1497 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1499 *(cd->mcodeptr++) = 0x0f;
1500 *(cd->mcodeptr++) = 0x90 + (u1) (opc);
1501 emit_membase(cd, (basereg),(disp),0);
1505 void emit_xadd_reg_mem(codegendata *cd, s4 reg, s4 mem)
1507 *(cd->mcodeptr++) = 0x0f;
1508 *(cd->mcodeptr++) = 0xc1;
1509 emit_mem((reg),(mem));
1513 void emit_neg_reg(codegendata *cd, s4 reg)
1515 *(cd->mcodeptr++) = 0xf7;
1521 void emit_push_imm(codegendata *cd, s4 imm)
1523 *(cd->mcodeptr++) = 0x68;
1528 void emit_pop_reg(codegendata *cd, s4 reg)
1530 *(cd->mcodeptr++) = 0x58 + (0x07 & (u1) (reg));
1534 void emit_push_reg(codegendata *cd, s4 reg)
1536 *(cd->mcodeptr++) = 0x50 + (0x07 & (u1) (reg));
1540 void emit_lock(codegendata *cd)
1542 *(cd->mcodeptr++) = 0xf0;
1549 void emit_call_reg(codegendata *cd, s4 reg)
1551 *(cd->mcodeptr++) = 0xff;
1556 void emit_call_imm(codegendata *cd, s4 imm)
1558 *(cd->mcodeptr++) = 0xe8;
1565 * floating point instructions
1567 void emit_fld1(codegendata *cd)
1569 *(cd->mcodeptr++) = 0xd9;
1570 *(cd->mcodeptr++) = 0xe8;
1574 void emit_fldz(codegendata *cd)
1576 *(cd->mcodeptr++) = 0xd9;
1577 *(cd->mcodeptr++) = 0xee;
1581 void emit_fld_reg(codegendata *cd, s4 reg)
1583 *(cd->mcodeptr++) = 0xd9;
1584 *(cd->mcodeptr++) = 0xc0 + (0x07 & (u1) (reg));
1588 void emit_flds_membase(codegendata *cd, s4 basereg, s4 disp)
1590 *(cd->mcodeptr++) = 0xd9;
1591 emit_membase(cd, (basereg),(disp),0);
1595 void emit_flds_membase32(codegendata *cd, s4 basereg, s4 disp)
1597 *(cd->mcodeptr++) = 0xd9;
1598 emit_membase32(cd, (basereg),(disp),0);
1602 void emit_fldl_membase(codegendata *cd, s4 basereg, s4 disp)
1604 *(cd->mcodeptr++) = 0xdd;
1605 emit_membase(cd, (basereg),(disp),0);
1609 void emit_fldl_membase32(codegendata *cd, s4 basereg, s4 disp)
1611 *(cd->mcodeptr++) = 0xdd;
1612 emit_membase32(cd, (basereg),(disp),0);
1616 void emit_fldt_membase(codegendata *cd, s4 basereg, s4 disp)
1618 *(cd->mcodeptr++) = 0xdb;
1619 emit_membase(cd, (basereg),(disp),5);
1623 void emit_flds_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1625 *(cd->mcodeptr++) = 0xd9;
1626 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1630 void emit_fldl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1632 *(cd->mcodeptr++) = 0xdd;
1633 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1637 void emit_flds_mem(codegendata *cd, s4 mem)
1639 *(cd->mcodeptr++) = 0xd9;
1644 void emit_fldl_mem(codegendata *cd, s4 mem)
1646 *(cd->mcodeptr++) = 0xdd;
1651 void emit_fildl_membase(codegendata *cd, s4 basereg, s4 disp)
1653 *(cd->mcodeptr++) = 0xdb;
1654 emit_membase(cd, (basereg),(disp),0);
1658 void emit_fildll_membase(codegendata *cd, s4 basereg, s4 disp)
1660 *(cd->mcodeptr++) = 0xdf;
1661 emit_membase(cd, (basereg),(disp),5);
1665 void emit_fst_reg(codegendata *cd, s4 reg)
1667 *(cd->mcodeptr++) = 0xdd;
1668 *(cd->mcodeptr++) = 0xd0 + (0x07 & (u1) (reg));
1672 void emit_fsts_membase(codegendata *cd, s4 basereg, s4 disp)
1674 *(cd->mcodeptr++) = 0xd9;
1675 emit_membase(cd, (basereg),(disp),2);
1679 void emit_fstl_membase(codegendata *cd, s4 basereg, s4 disp)
1681 *(cd->mcodeptr++) = 0xdd;
1682 emit_membase(cd, (basereg),(disp),2);
1686 void emit_fsts_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1688 *(cd->mcodeptr++) = 0xd9;
1689 emit_memindex(cd, 2,(disp),(basereg),(indexreg),(scale));
1693 void emit_fstl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1695 *(cd->mcodeptr++) = 0xdd;
1696 emit_memindex(cd, 2,(disp),(basereg),(indexreg),(scale));
1700 void emit_fstp_reg(codegendata *cd, s4 reg)
1702 *(cd->mcodeptr++) = 0xdd;
1703 *(cd->mcodeptr++) = 0xd8 + (0x07 & (u1) (reg));
1707 void emit_fstps_membase(codegendata *cd, s4 basereg, s4 disp)
1709 *(cd->mcodeptr++) = 0xd9;
1710 emit_membase(cd, (basereg),(disp),3);
1714 void emit_fstps_membase32(codegendata *cd, s4 basereg, s4 disp)
1716 *(cd->mcodeptr++) = 0xd9;
1717 emit_membase32(cd, (basereg),(disp),3);
1721 void emit_fstpl_membase(codegendata *cd, s4 basereg, s4 disp)
1723 *(cd->mcodeptr++) = 0xdd;
1724 emit_membase(cd, (basereg),(disp),3);
1728 void emit_fstpl_membase32(codegendata *cd, s4 basereg, s4 disp)
1730 *(cd->mcodeptr++) = 0xdd;
1731 emit_membase32(cd, (basereg),(disp),3);
1735 void emit_fstpt_membase(codegendata *cd, s4 basereg, s4 disp)
1737 *(cd->mcodeptr++) = 0xdb;
1738 emit_membase(cd, (basereg),(disp),7);
1742 void emit_fstps_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1744 *(cd->mcodeptr++) = 0xd9;
1745 emit_memindex(cd, 3,(disp),(basereg),(indexreg),(scale));
1749 void emit_fstpl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1751 *(cd->mcodeptr++) = 0xdd;
1752 emit_memindex(cd, 3,(disp),(basereg),(indexreg),(scale));
1756 void emit_fstps_mem(codegendata *cd, s4 mem)
1758 *(cd->mcodeptr++) = 0xd9;
1763 void emit_fstpl_mem(codegendata *cd, s4 mem)
1765 *(cd->mcodeptr++) = 0xdd;
1770 void emit_fistl_membase(codegendata *cd, s4 basereg, s4 disp)
1772 *(cd->mcodeptr++) = 0xdb;
1773 emit_membase(cd, (basereg),(disp),2);
1777 void emit_fistpl_membase(codegendata *cd, s4 basereg, s4 disp)
1779 *(cd->mcodeptr++) = 0xdb;
1780 emit_membase(cd, (basereg),(disp),3);
1784 void emit_fistpll_membase(codegendata *cd, s4 basereg, s4 disp)
1786 *(cd->mcodeptr++) = 0xdf;
1787 emit_membase(cd, (basereg),(disp),7);
1791 void emit_fchs(codegendata *cd)
1793 *(cd->mcodeptr++) = 0xd9;
1794 *(cd->mcodeptr++) = 0xe0;
1798 void emit_faddp(codegendata *cd)
1800 *(cd->mcodeptr++) = 0xde;
1801 *(cd->mcodeptr++) = 0xc1;
1805 void emit_fadd_reg_st(codegendata *cd, s4 reg)
1807 *(cd->mcodeptr++) = 0xd8;
1808 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1812 void emit_fadd_st_reg(codegendata *cd, s4 reg)
1814 *(cd->mcodeptr++) = 0xdc;
1815 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1819 void emit_faddp_st_reg(codegendata *cd, s4 reg)
1821 *(cd->mcodeptr++) = 0xde;
1822 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1826 void emit_fadds_membase(codegendata *cd, s4 basereg, s4 disp)
1828 *(cd->mcodeptr++) = 0xd8;
1829 emit_membase(cd, (basereg),(disp),0);
1833 void emit_faddl_membase(codegendata *cd, s4 basereg, s4 disp)
1835 *(cd->mcodeptr++) = 0xdc;
1836 emit_membase(cd, (basereg),(disp),0);
1840 void emit_fsub_reg_st(codegendata *cd, s4 reg)
1842 *(cd->mcodeptr++) = 0xd8;
1843 *(cd->mcodeptr++) = 0xe0 + (0x07 & (u1) (reg));
1847 void emit_fsub_st_reg(codegendata *cd, s4 reg)
1849 *(cd->mcodeptr++) = 0xdc;
1850 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1854 void emit_fsubp_st_reg(codegendata *cd, s4 reg)
1856 *(cd->mcodeptr++) = 0xde;
1857 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1861 void emit_fsubp(codegendata *cd)
1863 *(cd->mcodeptr++) = 0xde;
1864 *(cd->mcodeptr++) = 0xe9;
1868 void emit_fsubs_membase(codegendata *cd, s4 basereg, s4 disp)
1870 *(cd->mcodeptr++) = 0xd8;
1871 emit_membase(cd, (basereg),(disp),4);
1875 void emit_fsubl_membase(codegendata *cd, s4 basereg, s4 disp)
1877 *(cd->mcodeptr++) = 0xdc;
1878 emit_membase(cd, (basereg),(disp),4);
1882 void emit_fmul_reg_st(codegendata *cd, s4 reg)
1884 *(cd->mcodeptr++) = 0xd8;
1885 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1889 void emit_fmul_st_reg(codegendata *cd, s4 reg)
1891 *(cd->mcodeptr++) = 0xdc;
1892 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1896 void emit_fmulp(codegendata *cd)
1898 *(cd->mcodeptr++) = 0xde;
1899 *(cd->mcodeptr++) = 0xc9;
1903 void emit_fmulp_st_reg(codegendata *cd, s4 reg)
1905 *(cd->mcodeptr++) = 0xde;
1906 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1910 void emit_fmuls_membase(codegendata *cd, s4 basereg, s4 disp)
1912 *(cd->mcodeptr++) = 0xd8;
1913 emit_membase(cd, (basereg),(disp),1);
1917 void emit_fmull_membase(codegendata *cd, s4 basereg, s4 disp)
1919 *(cd->mcodeptr++) = 0xdc;
1920 emit_membase(cd, (basereg),(disp),1);
1924 void emit_fdiv_reg_st(codegendata *cd, s4 reg)
1926 *(cd->mcodeptr++) = 0xd8;
1927 *(cd->mcodeptr++) = 0xf0 + (0x07 & (u1) (reg));
1931 void emit_fdiv_st_reg(codegendata *cd, s4 reg)
1933 *(cd->mcodeptr++) = 0xdc;
1934 *(cd->mcodeptr++) = 0xf8 + (0x07 & (u1) (reg));
1938 void emit_fdivp(codegendata *cd)
1940 *(cd->mcodeptr++) = 0xde;
1941 *(cd->mcodeptr++) = 0xf9;
1945 void emit_fdivp_st_reg(codegendata *cd, s4 reg)
1947 *(cd->mcodeptr++) = 0xde;
1948 *(cd->mcodeptr++) = 0xf8 + (0x07 & (u1) (reg));
1952 void emit_fxch(codegendata *cd)
1954 *(cd->mcodeptr++) = 0xd9;
1955 *(cd->mcodeptr++) = 0xc9;
1959 void emit_fxch_reg(codegendata *cd, s4 reg)
1961 *(cd->mcodeptr++) = 0xd9;
1962 *(cd->mcodeptr++) = 0xc8 + (0x07 & (reg));
1966 void emit_fprem(codegendata *cd)
1968 *(cd->mcodeptr++) = 0xd9;
1969 *(cd->mcodeptr++) = 0xf8;
1973 void emit_fprem1(codegendata *cd)
1975 *(cd->mcodeptr++) = 0xd9;
1976 *(cd->mcodeptr++) = 0xf5;
1980 void emit_fucom(codegendata *cd)
1982 *(cd->mcodeptr++) = 0xdd;
1983 *(cd->mcodeptr++) = 0xe1;
1987 void emit_fucom_reg(codegendata *cd, s4 reg)
1989 *(cd->mcodeptr++) = 0xdd;
1990 *(cd->mcodeptr++) = 0xe0 + (0x07 & (u1) (reg));
1994 void emit_fucomp_reg(codegendata *cd, s4 reg)
1996 *(cd->mcodeptr++) = 0xdd;
1997 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
2001 void emit_fucompp(codegendata *cd)
2003 *(cd->mcodeptr++) = 0xda;
2004 *(cd->mcodeptr++) = 0xe9;
2008 void emit_fnstsw(codegendata *cd)
2010 *(cd->mcodeptr++) = 0xdf;
2011 *(cd->mcodeptr++) = 0xe0;
2015 void emit_sahf(codegendata *cd)
2017 *(cd->mcodeptr++) = 0x9e;
2021 void emit_finit(codegendata *cd)
2023 *(cd->mcodeptr++) = 0x9b;
2024 *(cd->mcodeptr++) = 0xdb;
2025 *(cd->mcodeptr++) = 0xe3;
2029 void emit_fldcw_mem(codegendata *cd, s4 mem)
2031 *(cd->mcodeptr++) = 0xd9;
2036 void emit_fldcw_membase(codegendata *cd, s4 basereg, s4 disp)
2038 *(cd->mcodeptr++) = 0xd9;
2039 emit_membase(cd, (basereg),(disp),5);
2043 void emit_wait(codegendata *cd)
2045 *(cd->mcodeptr++) = 0x9b;
2049 void emit_ffree_reg(codegendata *cd, s4 reg)
2051 *(cd->mcodeptr++) = 0xdd;
2052 *(cd->mcodeptr++) = 0xc0 + (0x07 & (u1) (reg));
2056 void emit_fdecstp(codegendata *cd)
2058 *(cd->mcodeptr++) = 0xd9;
2059 *(cd->mcodeptr++) = 0xf6;
2063 void emit_fincstp(codegendata *cd)
2065 *(cd->mcodeptr++) = 0xd9;
2066 *(cd->mcodeptr++) = 0xf7;
2069 #if defined(ENABLE_ESCAPE_CHECK)
2070 void emit_escape_check(codegendata *cd, s4 reg) {
2072 M_MOV_IMM(asm_escape_check, REG_ITMP3);
2074 M_IADD_IMM(4, REG_SP);
2079 * These are local overrides for various environment variables in Emacs.
2080 * Please do not remove this and leave it at the end of the file, where
2081 * Emacs will automagically detect them.
2082 * ---------------------------------------------------------------------
2085 * indent-tabs-mode: t