1 /* vm/jit/i386/codegen.h - code generation macros and definitions for i386
3 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
4 R. Grafl, A. Krall, C. Kruegel, C. Oates, R. Obermaisser,
5 M. Probst, S. Ring, E. Steiner, C. Thalinger, D. Thuernbeck,
6 P. Tomsich, J. Wenninger
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
30 $Id: codegen.h 1623 2004-11-30 14:18:19Z twisti $
41 /* additional functions and macros to generate code ***************************/
43 #define BlockPtrOfPC(pc) ((basicblock *) iptr->target)
47 #define COUNT_SPILLS count_spills++
53 #define CALCOFFSETBYTES(var, reg, val) \
54 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
55 else if ((s4) (val) != 0) (var) += 1; \
56 else if ((reg) == EBP) (var) += 1;
59 #define CALCIMMEDIATEBYTES(var, val) \
60 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
64 /* gen_nullptr_check(objreg) */
66 #define gen_nullptr_check(objreg) \
68 i386_test_reg_reg(cd, (objreg), (objreg)); \
69 i386_jcc(cd, I386_CC_E, 0); \
70 codegen_addxnullrefs(cd, cd->mcodeptr); \
73 #define gen_bound_check \
75 i386_alu_membase_reg(cd, I386_CMP, s1, OFFSET(java_arrayheader, size), s2); \
76 i386_jcc(cd, I386_CC_AE, 0); \
77 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
80 #define gen_div_check(v) \
82 if ((v)->flags & INMEMORY) { \
83 i386_alu_imm_membase(cd, I386_CMP, 0, REG_SP, src->regoff * 8); \
85 i386_test_reg_reg(cd, src->regoff, src->regoff); \
87 i386_jcc(cd, I386_CC_E, 0); \
88 codegen_addxdivrefs(cd, cd->mcodeptr); \
92 /* MCODECHECK(icnt) */
94 #define MCODECHECK(icnt) \
95 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
96 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
99 /* XXX Do we need code padding on i386? */
100 /* #define ALIGNCODENOP {if((int)((long)cd->mcodeptr&7)){M_NOP;}} */
105 generates an integer-move from register a to b.
106 if a and b are the same int-register, no code will be generated.
109 #define M_INTMOVE(reg,dreg) \
110 if ((reg) != (dreg)) { \
111 i386_mov_reg_reg(cd, (reg),(dreg)); \
116 generates a floating-point-move from register a to b.
117 if a and b are the same float-register, no code will be generated
120 #define M_FLTMOVE(reg,dreg) panic("M_FLTMOVE");
122 #define M_LNGMEMMOVE(reg,dreg) \
124 i386_mov_membase_reg(cd, REG_SP, (reg) * 8, REG_ITMP1); \
125 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 8); \
126 i386_mov_membase_reg(cd, REG_SP, (reg) * 8 + 4, REG_ITMP1); \
127 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 8 + 4); \
132 this function generates code to fetch data from a pseudo-register
133 into a real register.
134 If the pseudo-register has actually been assigned to a real
135 register, no code will be emitted, since following operations
136 can use this register directly.
138 v: pseudoregister to be fetched from
139 tempregnum: temporary register to be used if v is actually spilled to ram
141 return: the register number, where the operand can be found after
142 fetching (this wil be either tempregnum or the register
143 number allready given to v)
146 #define var_to_reg_int(regnr,v,tempnr) \
147 if ((v)->flags & INMEMORY) { \
149 i386_mov_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
152 regnr = (v)->regoff; \
157 #define var_to_reg_flt(regnr,v,tempnr) \
158 if ((v)->type == TYPE_FLT) { \
159 if ((v)->flags & INMEMORY) { \
161 i386_flds_membase(cd, REG_SP, (v)->regoff * 8); \
165 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
167 regnr = (v)->regoff; \
170 if ((v)->flags & INMEMORY) { \
172 i386_fldl_membase(cd, REG_SP, (v)->regoff * 8); \
176 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
178 regnr = (v)->regoff; \
182 #define NEW_var_to_reg_flt(regnr,v,tempnr) \
183 if ((v)->type == TYPE_FLT) { \
184 if ((v)->flags & INMEMORY) { \
186 i386_flds_membase(cd, REG_SP, (v)->regoff * 8); \
190 regnr = (v)->regoff; \
193 if ((v)->flags & INMEMORY) { \
195 i386_fldl_membase(cd, REG_SP, (v)->regoff * 8); \
199 regnr = (v)->regoff; \
204 /* store_reg_to_var_xxx:
205 This function generates the code to store the result of an operation
206 back into a spilled pseudo-variable.
207 If the pseudo-variable has not been spilled in the first place, this
208 function will generate nothing.
210 v ............ Pseudovariable
211 tempregnum ... Number of the temporary registers as returned by
215 #define store_reg_to_var_int(sptr, tempregnum) \
216 if ((sptr)->flags & INMEMORY) { \
218 i386_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
222 #define store_reg_to_var_flt(sptr, tempregnum) \
223 if ((sptr)->type == TYPE_FLT) { \
224 if ((sptr)->flags & INMEMORY) { \
226 i386_fstps_membase(cd, REG_SP, (sptr)->regoff * 8); \
229 /* i386_fxch_reg((sptr)->regoff);*/ \
230 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
234 if ((sptr)->flags & INMEMORY) { \
236 i386_fstpl_membase(cd, REG_SP, (sptr)->regoff * 8); \
239 /* i386_fxch_reg((sptr)->regoff);*/ \
240 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
246 #define M_COPY(from,to) \
247 d = reg_of_var(rd, to, REG_ITMP1); \
248 if ((from->regoff != to->regoff) || \
249 ((from->flags ^ to->flags) & INMEMORY)) { \
250 if (IS_FLT_DBL_TYPE(from->type)) { \
251 var_to_reg_flt(s1, from, d); \
252 /*M_FLTMOVE(s1, d);*/ \
253 store_reg_to_var_flt(to, d); \
255 if (!IS_2_WORD_TYPE(from->type)) { \
256 if (to->flags & INMEMORY) { \
257 if (from->flags & INMEMORY) { \
258 i386_mov_membase_reg(cd, REG_SP, from->regoff * 8, REG_ITMP1); \
259 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, to->regoff * 8); \
261 i386_mov_reg_membase(cd, from->regoff, REG_SP, to->regoff * 8); \
264 if (from->flags & INMEMORY) { \
265 i386_mov_membase_reg(cd, REG_SP, from->regoff * 8, to->regoff); \
267 i386_mov_reg_reg(cd, from->regoff, to->regoff); \
271 M_LNGMEMMOVE(from->regoff, to->regoff); \
276 /* macros to create code ******************************************************/
291 /* opcodes for alu instructions */
319 I386_CC_B = 2, I386_CC_C = 2, I386_CC_NAE = 2,
320 I386_CC_BE = 6, I386_CC_NA = 6,
321 I386_CC_AE = 3, I386_CC_NB = 3, I386_CC_NC = 3,
322 I386_CC_E = 4, I386_CC_Z = 4,
323 I386_CC_NE = 5, I386_CC_NZ = 5,
324 I386_CC_A = 7, I386_CC_NBE = 7,
325 I386_CC_S = 8, I386_CC_LZ = 8,
326 I386_CC_NS = 9, I386_CC_GEZ = 9,
327 I386_CC_P = 0x0a, I386_CC_PE = 0x0a,
328 I386_CC_NP = 0x0b, I386_CC_PO = 0x0b,
329 I386_CC_L = 0x0c, I386_CC_NGE = 0x0c,
330 I386_CC_GE = 0x0d, I386_CC_NL = 0x0d,
331 I386_CC_LE = 0x0e, I386_CC_NG = 0x0e,
332 I386_CC_G = 0x0f, I386_CC_NLE = 0x0f,
337 /* modrm and stuff */
339 #define i386_address_byte(mod,reg,rm) \
340 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | (((rm) & 0x07)));
343 #define i386_emit_reg(reg,rm) \
344 i386_address_byte(3,(reg),(rm));
347 #define i386_is_imm8(imm) \
348 (((int)(imm) >= -128 && (int)(imm) <= 127))
351 #define i386_emit_imm8(imm) \
352 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
355 #define i386_emit_imm16(imm) \
358 imb.i = (int) (imm); \
359 *(cd->mcodeptr++) = imb.b[0]; \
360 *(cd->mcodeptr++) = imb.b[1]; \
364 #define i386_emit_imm32(imm) \
367 imb.i = (int) (imm); \
368 *(cd->mcodeptr++) = imb.b[0]; \
369 *(cd->mcodeptr++) = imb.b[1]; \
370 *(cd->mcodeptr++) = imb.b[2]; \
371 *(cd->mcodeptr++) = imb.b[3]; \
375 #define i386_emit_mem(r,mem) \
377 i386_address_byte(0,(r),5); \
378 i386_emit_imm32((mem)); \
382 #define i386_emit_membase(basereg,disp,dreg) \
384 if ((basereg) == ESP) { \
386 i386_address_byte(0, (dreg), ESP); \
387 i386_address_byte(0, ESP, ESP); \
388 } else if (i386_is_imm8((disp))) { \
389 i386_address_byte(1, (dreg), ESP); \
390 i386_address_byte(0, ESP, ESP); \
391 i386_emit_imm8((disp)); \
393 i386_address_byte(2, (dreg), ESP); \
394 i386_address_byte(0, ESP, ESP); \
395 i386_emit_imm32((disp)); \
400 if ((disp) == 0 && (basereg) != EBP) { \
401 i386_address_byte(0, (dreg), (basereg)); \
405 if (i386_is_imm8((disp))) { \
406 i386_address_byte(1, (dreg), (basereg)); \
407 i386_emit_imm8((disp)); \
409 i386_address_byte(2, (dreg), (basereg)); \
410 i386_emit_imm32((disp)); \
415 #define i386_emit_memindex(reg,disp,basereg,indexreg,scale) \
417 if ((basereg) == -1) { \
418 i386_address_byte(0, (reg), 4); \
419 i386_address_byte((scale), (indexreg), 5); \
420 i386_emit_imm32((disp)); \
422 } else if ((disp) == 0 && (basereg) != EBP) { \
423 i386_address_byte(0, (reg), 4); \
424 i386_address_byte((scale), (indexreg), (basereg)); \
426 } else if (i386_is_imm8((disp))) { \
427 i386_address_byte(1, (reg), 4); \
428 i386_address_byte((scale), (indexreg), (basereg)); \
429 i386_emit_imm8 ((disp)); \
432 i386_address_byte(2, (reg), 4); \
433 i386_address_byte((scale), (indexreg), (basereg)); \
434 i386_emit_imm32((disp)); \
439 /* function gen_resolvebranch **************************************************
441 backpatches a branch instruction
443 parameters: ip ... pointer to instruction after branch (void*)
444 so ... offset of instruction after branch (s4)
445 to ... offset of branch target (s4)
447 *******************************************************************************/
449 #define gen_resolvebranch(ip,so,to) \
450 *((void **) ((ip) - 4)) = (void **) ((to) - (so));
453 /* function prototypes */
455 void thread_restartcriticalsection(ucontext_t *);
457 #endif /* _CODEGEN_H */
461 * These are local overrides for various environment variables in Emacs.
462 * Please do not remove this and leave it at the end of the file, where
463 * Emacs will automagically detect them.
464 * ---------------------------------------------------------------------
467 * indent-tabs-mode: t