1 /* src/vm/jit/arm/codegen.h - code generation macros and definitions for ARM
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: codegen.h 8160 2007-06-28 01:52:19Z michi $
36 /* helper macros for generating code ******************************************/
38 #if defined(__ARMEL__)
39 #define SPLIT_OPEN(type, reg, tmpreg) \
40 if (IS_2_WORD_TYPE(type) && GET_HIGH_REG(reg)==REG_SPLIT) { \
41 /*dolog("SPLIT_OPEN({R%d;SPL} > {R%d;R%d})", GET_LOW_REG(reg), GET_LOW_REG(reg), tmpreg);*/ \
42 /*assert(GET_LOW_REG(reg) == 3);*/ \
43 (reg) = PACK_REGS(GET_LOW_REG(reg), tmpreg); \
45 #define SPLIT_LOAD(type, reg, offset) \
46 if (IS_2_WORD_TYPE(type) && GET_LOW_REG(reg)==3) { \
47 /*dolog("SPLIT_LOAD({R%d;R%d} from [%x])", GET_LOW_REG(reg), GET_HIGH_REG(reg), offset);*/ \
48 M_LDR(GET_HIGH_REG(reg), REG_SP, 4 * (offset)); \
50 #define SPLIT_STORE_AND_CLOSE(type, reg, offset) \
51 if (IS_2_WORD_TYPE(type) && GET_LOW_REG(reg)==3) { \
52 /*dolog("SPLIT_STORE({R%d;R%d} to [%x])", GET_LOW_REG(reg), GET_HIGH_REG(reg), offset);*/ \
53 M_STR(GET_HIGH_REG(reg), REG_SP, 4 * (offset)); \
54 (reg) = PACK_REGS(GET_LOW_REG(reg), REG_SPLIT); \
56 #else /* defined(__ARMEB__) */
57 #define SPLIT_OPEN(type, reg, tmpreg) \
58 if (IS_2_WORD_TYPE(type) && GET_LOW_REG(reg)==REG_SPLIT) { \
59 /*dolog("SPLIT_OPEN({SPL;R%d} > {R%d;R%d})", GET_HIGH_REG(reg), tmpreg, GET_HIGH_REG(reg));*/ \
60 /*assert(GET_HIGH_REG(reg) == 3);*/ \
61 (reg) = PACK_REGS(tmpreg, GET_HIGH_REG(reg)); \
63 #define SPLIT_LOAD(type, reg, offset) \
64 if (IS_2_WORD_TYPE(type) && GET_HIGH_REG(reg)==3) { \
65 /*dolog("SPLIT_LOAD({R%d;R%d} from [%x])", GET_LOW_REG(reg), GET_HIGH_REG(reg), offset);*/ \
66 M_LDR(GET_LOW_REG(reg), REG_SP, 4 * (offset)); \
68 #define SPLIT_STORE_AND_CLOSE(type, reg, offset) \
69 if (IS_2_WORD_TYPE(type) && GET_HIGH_REG(reg)==3) { \
70 /*dolog("SPLIT_STORE({R%d;R%d} to [%x])", GET_LOW_REG(reg), GET_HIGH_REG(reg), offset);*/ \
71 M_STR(GET_LOW_REG(reg), REG_SP, 4 * (offset)); \
72 (reg) = PACK_REGS(REG_SPLIT, GET_HIGH_REG(reg)); \
77 #define MCODECHECK(icnt) \
79 if ((cd->mcodeptr + (icnt) * 4) > cd->mcodeend) \
80 codegen_increase(cd); \
84 /* TODO: correct this! */
85 #define IS_IMM(val) ( ((val) >= 0) && ((val) <= 255) )
86 #define IS_OFFSET(off,max) ((s4)(off) <= (max) && (s4)(off) >= -(max))
89 # define CHECK_INT_REG(r) if ((r)<0 || (r)>15) printf("CHECK_INT_REG: this is not an integer register: %d\n", r); assert((r)>=0 && (r)<=15)
90 # define CHECK_FLT_REG(r) if ((r)<0 || (r)>7) printf("CHECK_FLT_REG: this is not an float register: %d\n", r); assert((r)>=0 && (r)<=7)
91 # define CHECK_OFFSET(off,max) \
92 if (!IS_OFFSET(off,max)) printf("CHECK_OFFSET: offset out of range: %x (>%x) SEVERE ERROR!!!\n", ((off)<0)?-(off):off, max); \
93 assert(IS_OFFSET(off,max))
95 # define CHECK_INT_REG(r)
96 # define CHECK_FLT_REG(r)
97 # define CHECK_OFFSET(off,max)
101 /* branch defines *************************************************************/
103 #define BRANCH_NOPS \
109 /* patcher defines ************************************************************/
111 #define PATCHER_CALL_SIZE 1 * 4 /* an instruction is 4-bytes long */
113 #define PATCHER_NOPS \
119 /* stub defines ***************************************************************/
121 #define COMPILERSTUB_CODESIZE 2 * 4
124 /* lazy debugger **************************************************************/
127 void asm_debug(int a1, int a2, int a3, int a4);
128 void asm_debug_intern(int a1, int a2, int a3, int a4);
130 /* if called with this macros, it can be placed nearly anywhere */
131 /* almost all registers are saved and restored afterwards */
132 /* it uses a long branch to call the asm_debug_intern (no exit) */
133 #define ASM_DEBUG_PREPARE \
134 M_STMFD(0x7fff, REG_SP)
135 #define ASM_DEBUG_EXECUTE \
136 M_LONGBRANCH(asm_debug_intern); \
137 M_LDMFD(0x7fff, REG_SP)
141 /* macros to create code ******************************************************/
143 /* the condition field */
144 #define COND_EQ 0x0 /* Equal Z set */
145 #define COND_NE 0x1 /* Not equal Z clear */
146 #define COND_CS 0x2 /* Carry set C set */
147 #define COND_CC 0x3 /* Carry clear C clear */
148 #define COND_MI 0x4 /* Negative N set */
149 #define COND_PL 0x5 /* Positive N clear */
150 #define COND_VS 0x6 /* Overflow V set */
151 #define COND_VC 0x7 /* No overflow V clear */
152 #define COND_HI 0x8 /* Unsigned higher */
153 #define COND_LS 0x9 /* Unsigned lower, same */
154 #define COND_GE 0xA /* Sig. greater, equal */
155 #define COND_LT 0xB /* Sig. less than */
156 #define COND_GT 0xC /* Sig. greater than */
157 #define COND_LE 0xD /* Sig. less, equal */
158 #define COND_AL 0xE /* Always */
159 #define CONDNV 0xF /* Special (see A3-5) */
160 #define UNCOND COND_AL
162 /* data processing operation: M_DAT
163 cond ... conditional execution
165 d ...... destination reg
167 S ...... update condition codes
168 I ...... switch to immediate mode
169 shift .. shifter operand
172 #define M_DAT(cond,op,d,n,S,I,shift) \
174 *((u4 *) cd->mcodeptr) = (((cond) << 28) | ((op) << 21) | ((d) << 12) | ((n) << 16) | ((I) << 25) | ((S) << 20) | ((shift) & 0x00000fff)); \
179 /* load and store instruction: M_MEM
180 cond ... conditional execution
181 L ...... load (L=1) or store (L=0)
182 B ...... unsigned byte (B=1) or word (B=0)
183 d ...... destination reg
184 n ...... base reg for addressing
185 adr .... addressing mode specific
188 #define M_MEM(cond,L,B,d,n,adr,I,P,U,W) \
190 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (1 << 26) | ((L) << 20) | ((B) << 22) | ((d) << 12) | ((n) << 16) | ((adr) & 0x0fff) | ((I) << 25) | ((P) << 24) | ((U) << 23) | ((W) << 21)); \
195 /* load and store instruction: M_MEM2
196 cond ... conditional execution
197 L ...... load (L=1) or store (L=0)
198 H ...... halfword (H=1) or signed byte (H=0)
199 S ...... signed (S=1) or unsigned (S=0) halfword
200 d ...... destination reg
201 n ...... base reg for addressing
202 adr .... addressing mode specific
205 #define M_MEM2(cond,L,H,S,d,n,adr,I,P,U,W) \
207 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (1 << 22) | (0x9 << 4) | ((L) << 20) | ((H) << 5) | ((S) << 6) | ((d) << 12) | ((n) << 16) | ((adr) & 0x0f) | (((adr) & 0xf0) << (8-4)) | ((I) << 22) | ((P) << 24) | ((U) << 23) | ((W) << 21)); \
212 /* load and store multiple instruction: M_MEM_MULTI
213 cond ... conditional execution
214 L ...... load (L=1) or store (L=0)
215 S ...... special (see "The ARM ARM A3-21")
216 regs ... register list
217 n ...... base reg for addressing
220 #define M_MEM_MULTI(cond,L,S,regs,n,P,U,W) \
222 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (1 << 27) | ((L) << 20) | ((S) << 22) | ((n) << 16) | ((regs) & 0xffff) | ((P) << 24) | ((U) << 23) | ((W) << 21)); \
227 /* branch and branch with link: M_BRA
228 cond ... conditional execution
229 L ...... branch with link (L=1)
230 offset . 24bit offset
233 #define M_BRA(cond,L,offset) \
235 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x5 << 25) | ((L) << 24) | ((offset) & 0x00ffffff)); \
240 /* multiplies: M_MULT
241 cond ... conditional execution
242 d ...... destination register
243 n, m ... source registers
244 S ...... update conditional codes
245 A ...... accumulate flag (enables third source)
246 s ...... third source register
249 #define M_MULT(cond,d,n,m,S,A,s) \
251 *((u4 *) cd->mcodeptr) = (((cond) << 28) | ((d) << 16) | ((n) << 8) | (m) | (0x09 << 4) | ((S) << 20) | ((A) << 21) | ((s) << 12)); \
256 /* no operation (mov r0,r0): M_NOP */
260 *((u4 *) cd->mcodeptr) = (0xe1a00000); \
265 /* software breakpoint (only v5 and above): M_BREAKPOINT */
267 #define M_BREAKPOINT(imm) \
269 *((u4 *) cd->mcodeptr) = (0x0e12 << 20) | (0x07 << 4) | (((imm) & 0xfff0) << (8-4)) | ((imm) & 0x0f); \
274 /* undefined instruction used for hardware exceptions */
276 #define M_UNDEFINED(cond,imm,n) \
278 *((u4 *) cd->mcodeptr) = ((cond) << 28) | (0x7f << 20) | (((imm) & 0x0fff) << 8) | (0x0f << 4) | (n); \
283 #if !defined(ENABLE_SOFTFLOAT)
285 /* M_CPDO **********************************************************************
287 Floating-Point Coprocessor Data Operations
289 cond ... conditional execution
291 D ...... dyadic (D=0) or monadic (D=1) instruction
292 Fd ..... destination float-register
293 Fn ..... source float-register
294 Fm ..... source float-register or immediate
296 *******************************************************************************/
298 #define M_CPDOS(cond,op,D,Fd,Fn,Fm) \
300 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0e << 24) | (1 << 8) | ((op) << 20) | ((D) << 15) | ((Fd) << 12) | ((Fn) << 16) | ((Fm) & 0x0f)); \
305 #define M_CPDOD(cond,op,D,Fd,Fn,Fm) \
307 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0e << 24) | (1 << 8) | ((op) << 20) | ((D) << 15) | ((Fd) << 12) | ((Fn) << 16) | ((Fm) & 0x0f) | (1 << 7)); \
312 /* M_CPDT **********************************************************************
314 Floating-Point Coprocessor Data Transfer
316 cond ... conditional execution
317 L ...... load (L=1) or store (L=0)
318 Fd ..... destination float-register
319 n ...... base reg for addressing
321 *******************************************************************************/
323 #define M_CPDT(cond,L,T1,T0,Fd,n,off,P,U,W) \
325 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0c << 24) | (1 << 8) | ((L) << 20) | ((T1) << 22) | ((T0) << 15) | ((Fd) << 12) | ((n) << 16) | ((off) & 0xff) | ((P) << 24) | ((U) << 23) | ((W) << 21)); \
330 /* M_CPRT **********************************************************************
332 Floating-Point Coprocessor Register Transfer
336 *******************************************************************************/
338 #define M_CPRTS(cond,L,d,Fn,Fm) \
340 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0e << 24) | (1 << 8) | (1 << 4) | ((L) << 20) | ((d) << 12) | ((Fn) << 16) | (Fm)); \
345 #define M_CPRTD(cond,L,d,Fn,Fm) \
347 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0e << 24) | (1 << 8) | (1 << 4) | ((L) << 20) | ((d) << 12) | ((Fn) << 16) | (Fm) | (1 << 7)); \
352 #define M_CPRTI(cond,L,d,Fn,Fm) \
354 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0e << 24) | (1 << 8) | (1 << 4) | ((L) << 20) | ((d) << 12) | ((Fn) << 16) | (Fm) | (3 << 5)); \
359 /* XXX TWISTI: replace X by something useful */
361 #define M_CPRTX(cond,L,d,Fn,Fm) \
363 *((u4 *) cd->mcodeptr) = (((cond) << 28) | (0x0e << 24) | (1 << 8) | (1 << 4) | ((L) << 20) | ((d) << 12) | ((Fn) << 16) | (Fm) | (1 << 23)); \
367 #endif /* !defined(ENABLE_SOFTFLOAT) */
370 /* used to store values! */
373 *((u4 *) cd->mcodeptr) = val; \
378 /* used to directly access shifter; insert this as shifter operand! */
379 #define REG_LSL(reg, shift) ( (((shift) & 0x1f) << 7) | ((reg) & 0x0f) )
380 #define REG_LSR(reg, shift) ( (((shift) & 0x1f) << 7) | ((reg) & 0x0f) | (1 << 5) )
381 #define REG_ASR(reg, shift) ( (((shift) & 0x1f) << 7) | ((reg) & 0x0f) | (1 << 6) )
382 #define REG_LSL_REG(reg, s) ( (((s) & 0x0f) << 8) | ((reg) & 0x0f) | (1 << 4) )
383 #define REG_LSR_REG(reg, s) ( (((s) & 0x0f) << 8) | ((reg) & 0x0f) | (1 << 4) | (1 << 5) )
384 #define REG_ASR_REG(reg, s) ( (((s) & 0x0f) << 8) | ((reg) & 0x0f) | (1 << 4) | (1 << 6) )
386 /* used to directly rotate immediate values; insert this as immediate! */
387 /* ATTENTION: this rotates the immediate right by (2 * rot) bits */
388 #define IMM_ROTR(imm, rot) ( ((imm) & 0xff) | (((rot) & 0x0f) << 8) )
389 #define IMM_ROTL(imm, rot) IMM_ROTR(imm, 16-(rot))
391 /* macros for all arm instructions ********************************************/
393 #define M_ADD(d,a,b) M_DAT(UNCOND,0x04,d,a,0,0,b) /* d = a + b */
394 #define M_ADC(d,a,b) M_DAT(UNCOND,0x05,d,a,0,0,b) /* d = a + b (with Carry) */
395 #define M_SUB(d,a,b) M_DAT(UNCOND,0x02,d,a,0,0,b) /* d = a - b */
396 #define M_SBC(d,a,b) M_DAT(UNCOND,0x06,d,a,0,0,b) /* d = a - b (with Carry) */
397 #define M_AND(a,b,d) M_DAT(UNCOND,0x00,d,a,0,0,b) /* d = a & b */
398 #define M_ORR(a,b,d) M_DAT(UNCOND,0x0c,d,a,0,0,b) /* d = a | b */
399 #define M_EOR(a,b,d) M_DAT(UNCOND,0x01,d,a,0,0,b) /* d = a ^ b */
400 #define M_TST(a,b) M_DAT(UNCOND,0x08,0,a,1,0,b) /* TST a & b */
401 #define M_TEQ(a,b) M_DAT(UNCOND,0x09,0,a,1,0,b) /* TST a ^ b */
402 #define M_CMP(a,b) M_DAT(UNCOND,0x0a,0,a,1,0,b) /* TST a - b */
403 #define M_MOV(d,b) M_DAT(UNCOND,0x0d,d,0,0,0,b) /* d = b */
404 #define M_ADD_S(d,a,b) M_DAT(UNCOND,0x04,d,a,1,0,b) /* d = a + b (update Flags) */
405 #define M_SUB_S(d,a,b) M_DAT(UNCOND,0x02,d,a,1,0,b) /* d = a - b (update Flags) */
406 #define M_ORR_S(a,b,d) M_DAT(UNCOND,0x0c,d,a,1,0,b) /* d = a | b (update flags) */
407 #define M_MOV_S(d,b) M_DAT(UNCOND,0x0d,d,0,1,0,b) /* d = b (update Flags) */
409 #define M_ADD_IMM(d,a,i) M_DAT(UNCOND,0x04,d,a,0,1,i) /* d = a + i */
410 #define M_ADC_IMM(d,a,i) M_DAT(UNCOND,0x05,d,a,0,1,i) /* d = a + i (with Carry) */
411 #define M_SUB_IMM(d,a,i) M_DAT(UNCOND,0x02,d,a,0,1,i) /* d = a - i */
412 #define M_SBC_IMM(d,a,i) M_DAT(UNCOND,0x06,d,a,0,1,i) /* d = a - i (with Carry) */
413 #define M_RSB_IMM(d,a,i) M_DAT(UNCOND,0x03,d,a,0,1,i) /* d = -a + i */
414 #define M_RSC_IMM(d,a,i) M_DAT(UNCOND,0x07,d,a,0,1,i) /* d = -a + i (with Carry) */
415 #define M_AND_IMM(a,i,d) M_DAT(UNCOND,0x00,d,a,0,1,i) /* d = a & i */
416 #define M_TST_IMM(a,i) M_DAT(UNCOND,0x08,0,a,1,1,i) /* TST a & i */
417 #define M_TEQ_IMM(a,i) M_DAT(UNCOND,0x09,0,a,1,1,i) /* TST a ^ i */
418 #define M_CMP_IMM(a,i) M_DAT(UNCOND,0x0a,0,a,1,1,i) /* TST a - i */
419 #define M_CMN_IMM(a,i) M_DAT(UNCOND,0x0b,0,a,1,1,i) /* TST a + i */
420 #define M_MOV_IMM(d,i) M_DAT(UNCOND,0x0d,d,0,0,1,i) /* d = i */
421 #define M_ADD_IMMS(d,a,i) M_DAT(UNCOND,0x04,d,a,1,1,i) /* d = a + i (update Flags) */
422 #define M_SUB_IMMS(d,a,i) M_DAT(UNCOND,0x02,d,a,1,1,i) /* d = a - i (update Flags) */
423 #define M_RSB_IMMS(d,a,i) M_DAT(UNCOND,0x03,d,a,1,1,i) /* d = -a + i (update Flags) */
425 #define M_ADDSUB_IMM(d,a,i) if((i)>=0) M_ADD_IMM(d,a,i); else M_SUB_IMM(d,a,-(i))
426 #define M_MOVEQ(a,d) M_DAT(COND_EQ,0x0d,d,0,0,0,a)
427 #define M_EORLE(d,a,b) M_DAT(COND_LE,0x01,d,a,0,0,b)
429 #define M_MOVVS_IMM(i,d) M_DAT(COND_VS,0x0d,d,0,0,1,i)
430 #define M_MOVEQ_IMM(i,d) M_DAT(COND_EQ,0x0d,d,0,0,1,i)
431 #define M_MOVNE_IMM(i,d) M_DAT(COND_NE,0x0d,d,0,0,1,i)
432 #define M_MOVLT_IMM(i,d) M_DAT(COND_LT,0x0d,d,0,0,1,i)
433 #define M_MOVGT_IMM(i,d) M_DAT(COND_GT,0x0d,d,0,0,1,i)
434 #define M_MOVLS_IMM(i,d) M_DAT(COND_LS,0x0d,d,0,0,1,i)
436 #define M_ADDHI_IMM(d,a,i) M_DAT(COND_HI,0x04,d,a,0,1,i)
437 #define M_ADDLT_IMM(d,a,i) M_DAT(COND_LT,0x04,d,a,0,1,i)
438 #define M_ADDGT_IMM(d,a,i) M_DAT(COND_GT,0x04,d,a,0,1,i)
439 #define M_SUBLO_IMM(d,a,i) M_DAT(COND_CC,0x02,d,a,0,1,i)
440 #define M_SUBLT_IMM(d,a,i) M_DAT(COND_LT,0x02,d,a,0,1,i)
441 #define M_SUBGT_IMM(d,a,i) M_DAT(COND_GT,0x02,d,a,0,1,i)
442 #define M_RSBMI_IMM(d,a,i) M_DAT(COND_MI,0x03,d,a,0,1,i)
443 #define M_ADCMI_IMM(d,a,i) M_DAT(COND_MI,0x05,d,a,0,1,i)
445 #define M_CMPEQ(a,b) M_DAT(COND_EQ,0x0a,0,a,1,0,b) /* TST a - b */
446 #define M_CMPLE(a,b) M_DAT(COND_LE,0x0a,0,a,1,0,b) /* TST a - b */
448 #define M_CMPEQ_IMM(a,i) M_DAT(COND_EQ,0x0a,0,a,1,1,i)
450 #define M_MUL(d,a,b) M_MULT(UNCOND,d,a,b,0,0,0x0) /* d = a * b */
453 #define M_LDMFD(regs,base) M_MEM_MULTI(UNCOND,1,0,regs,base,0,1,1)
454 #define M_STMFD(regs,base) M_MEM_MULTI(UNCOND,0,0,regs,base,1,0,1)
456 #define M_LDR_INTERN(d,base,off) \
458 CHECK_OFFSET(off, 0x0fff); \
459 M_MEM(UNCOND,1,0,d,base,(((off) < 0) ? -(off) : off),0,1,(((off) < 0) ? 0 : 1),0); \
462 #define M_STR_INTERN(d,base,off) \
464 CHECK_OFFSET(off, 0x0fff); \
465 M_MEM(UNCOND,0,0,d,base,(((off) < 0) ? -(off) : off),0,1,(((off) < 0) ? 0 : 1),0); \
468 #define M_LDR_UPDATE(d,base,off) \
470 CHECK_OFFSET(off, 0x0fff); \
471 M_MEM(UNCOND,1,0,d,base,(((off) < 0) ? -(off) : off),0,0,(((off) < 0) ? 0 : 1),0); \
474 #define M_STR_UPDATE(d,base,off) \
476 CHECK_OFFSET(off,0x0fff); \
477 M_MEM(UNCOND,0,0,d,base,(((off) < 0) ? -(off) : off),0,1,(((off) < 0) ? 0 : 1),1); \
481 #define M_LDRH(d,base,off) \
483 CHECK_OFFSET(off, 0x00ff); \
485 M_MEM2(UNCOND,1,1,0,d,base,off,1,1,1,0); \
488 #define M_LDRSH(d,base,off) \
490 CHECK_OFFSET(off, 0x00ff); \
492 M_MEM2(UNCOND,1,1,1,d,base,off,1,1,1,0); \
495 #define M_LDRSB(d,base,off) \
497 CHECK_OFFSET(off, 0x00ff); \
499 M_MEM2(UNCOND,1,0,1,d,base,off,1,1,1,0); \
502 #define M_STRH(d,base,off) \
504 CHECK_OFFSET(off, 0x00ff); \
506 M_MEM2(UNCOND,0,1,0,d,base,off,1,1,1,0); \
509 #define M_STRB(d,base,off) \
511 CHECK_OFFSET(off, 0x0fff); \
513 M_MEM(UNCOND,0,1,d,base,off,0,1,1,0); \
517 #if !defined(ENABLE_SOFTFLOAT)
519 #define M_LDFS_INTERN(d,base,off) \
521 CHECK_OFFSET(off, 0x03ff); \
522 M_CPDT(UNCOND,1,0,0,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),1,(((off) < 0) ? 0 : 1),0); \
525 #define M_LDFD_INTERN(d,base,off) \
527 CHECK_OFFSET(off, 0x03ff); \
528 M_CPDT(UNCOND,1,0,1,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),1,(((off) < 0) ? 0 : 1),0); \
531 #define M_STFS_INTERN(d,base,off) \
533 CHECK_OFFSET(off, 0x03ff); \
534 M_CPDT(UNCOND,0,0,0,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),1,(((off) < 0) ? 0 : 1),0); \
537 #define M_STFD_INTERN(d,base,off) \
539 CHECK_OFFSET(off, 0x03ff); \
540 M_CPDT(UNCOND,0,0,1,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),1,(((off) < 0) ? 0 : 1),0); \
543 #define M_LDFS_UPDATE(d,base,off) \
545 CHECK_OFFSET(off, 0x03ff); \
546 M_CPDT(UNCOND,1,0,0,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),0,(((off) < 0) ? 0 : 1),1); \
549 #define M_LDFD_UPDATE(d,base,off) \
551 CHECK_OFFSET(off, 0x03ff); \
552 M_CPDT(UNCOND,1,0,1,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),0,(((off) < 0) ? 0 : 1),1); \
555 #define M_STFS_UPDATE(d,base,off) \
557 CHECK_OFFSET(off, 0x03ff); \
558 M_CPDT(UNCOND,0,0,0,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),1,(((off) < 0) ? 0 : 1),1); \
561 #define M_STFD_UPDATE(d,base,off) \
563 CHECK_OFFSET(off, 0x03ff); \
564 M_CPDT(UNCOND,0,0,1,d,base,(((off) < 0) ? -(off) >> 2 : (off) >> 2),1,(((off) < 0) ? 0 : 1),1); \
567 #define M_ADFS(d,a,b) M_CPDOS(UNCOND,0x00,0,d,a,b) /* d = a + b */
568 #define M_SUFS(d,a,b) M_CPDOS(UNCOND,0x02,0,d,a,b) /* d = a - b */
569 #define M_RSFS(d,a,b) M_CPDOS(UNCOND,0x03,0,d,a,b) /* d = b - a */
570 #define M_MUFS(d,a,b) M_CPDOS(UNCOND,0x01,0,d,a,b) /* d = a * b */
571 #define M_DVFS(d,a,b) M_CPDOS(UNCOND,0x04,0,d,a,b) /* d = a / b */
572 #define M_RMFS(d,a,b) M_CPDOS(UNCOND,0x08,0,d,a,b) /* d = a % b */
573 #define M_ADFD(d,a,b) M_CPDOD(UNCOND,0x00,0,d,a,b) /* d = a + b */
574 #define M_SUFD(d,a,b) M_CPDOD(UNCOND,0x02,0,d,a,b) /* d = a - b */
575 #define M_RSFD(d,a,b) M_CPDOD(UNCOND,0x03,0,d,a,b) /* d = b - a */
576 #define M_MUFD(d,a,b) M_CPDOD(UNCOND,0x01,0,d,a,b) /* d = a * b */
577 #define M_DVFD(d,a,b) M_CPDOD(UNCOND,0x04,0,d,a,b) /* d = a / b */
578 #define M_RMFD(d,a,b) M_CPDOD(UNCOND,0x08,0,d,a,b) /* d = a % b */
579 #define M_MVFS(d,a) M_CPDOS(UNCOND,0x00,1,d,0,a) /* d = a */
580 #define M_MVFD(d,a) M_CPDOD(UNCOND,0x00,1,d,0,a) /* d = a */
581 #define M_MNFS(d,a) M_CPDOS(UNCOND,0x01,1,d,0,a) /* d = - a */
582 #define M_MNFD(d,a) M_CPDOD(UNCOND,0x01,1,d,0,a) /* d = - a */
583 #define M_CMF(a,b) M_CPRTX(UNCOND,1,0x0f,a,b) /* COMPARE a; b */
584 #define M_FLTS(d,a) M_CPRTS(UNCOND,0,a,d,0) /* d = (float) a */
585 #define M_FLTD(d,a) M_CPRTD(UNCOND,0,a,d,0) /* d = (float) a */
586 #define M_FIX(d,a) M_CPRTI(UNCOND,1,d,0,a) /* d = (int) a */
588 #endif /* !defined(ENABLE_SOFTFLOAT) */
591 #define M_B(off) M_BRA(UNCOND,0,off) /* unconditional branch */
592 #define M_BL(off) M_BRA(UNCOND,1,off) /* branch and link */
593 #define M_BEQ(off) M_BRA(COND_EQ,0,off) /* conditional branches */
594 #define M_BNE(off) M_BRA(COND_NE,0,off)
595 #define M_BGE(off) M_BRA(COND_GE,0,off)
596 #define M_BGT(off) M_BRA(COND_GT,0,off)
597 #define M_BLT(off) M_BRA(COND_LT,0,off)
598 #define M_BLE(off) M_BRA(COND_LE,0,off)
599 #define M_BHI(off) M_BRA(COND_HI,0,off) /* unsigned conditional */
600 #define M_BHS(off) M_BRA(COND_CS,0,off)
601 #define M_BLO(off) M_BRA(COND_CC,0,off)
602 #define M_BLS(off) M_BRA(COND_LS,0,off)
605 #define M_FMOV(a,b) M_MVFS(b,a)
606 #define M_DMOV(a,b) M_MVFD(b,a)
609 #define M_TRAP(a,i) M_UNDEFINED(UNCOND,i,a);
610 #define M_TRAPEQ(a,i) M_UNDEFINED(COND_EQ,i,a);
611 #define M_TRAPLE(a,i) M_UNDEFINED(COND_LE,i,a);
612 #define M_TRAPHI(a,i) M_UNDEFINED(COND_HI,i,a);
613 #define M_TRAPHS(a,i) M_UNDEFINED(COND_CS,i,a);
616 /* if we do not have double-word load/store command, we can fake them */
617 /* ATTENTION: the original LDRD/STRD of ARMv5e would always use (Rd/Rd+1),
618 so these faked versions are more "powerful" */
620 #if defined(__ARMEL__)
622 #define M_LDRD_INTERN(d,base,off) \
624 M_LDR_INTERN(GET_LOW_REG(d), base, off); \
625 M_LDR_INTERN(GET_HIGH_REG(d), base, (off) + 4); \
628 #define M_STRD_INTERN(d,base,off) \
630 M_STR_INTERN(GET_LOW_REG(d), base, off); \
631 M_STR_INTERN(GET_HIGH_REG(d), base, (off) + 4); \
634 #define M_LDRD_ALTERN(d,base,off) \
636 M_LDR_INTERN(GET_HIGH_REG(d), base, (off) + 4); \
637 M_LDR_INTERN(GET_LOW_REG(d), base, off); \
640 #define M_LDRD_UPDATE(d,base,off) \
642 assert((off) == +8); \
643 M_LDR_UPDATE(GET_LOW_REG(d), base, 4); \
644 M_LDR_UPDATE(GET_HIGH_REG(d), base, 4); \
647 #define M_STRD_UPDATE(d,base,off) \
649 assert((off) == -8); \
650 M_STR_UPDATE(GET_HIGH_REG(d), base, -4); \
651 M_STR_UPDATE(GET_LOW_REG(d), base, -4); \
654 #define GET_FIRST_REG(d) GET_LOW_REG(d)
655 #define GET_SECOND_REG(d) GET_HIGH_REG(d)
657 #else /* defined(__ARMEB__) */
659 #define M_LDRD_INTERN(d,base,off) \
661 M_LDR_INTERN(GET_HIGH_REG(d), base, off); \
662 M_LDR_INTERN(GET_LOW_REG(d), base, (off) + 4); \
665 #define M_STRD_INTERN(d,base,off) \
667 M_STR_INTERN(GET_HIGH_REG(d), base, off); \
668 M_STR_INTERN(GET_LOW_REG(d), base, (off) + 4); \
671 #define M_LDRD_ALTERN(d,base,off) \
673 M_LDR_INTERN(GET_LOW_REG(d), base, (off) + 4); \
674 M_LDR_INTERN(GET_HIGH_REG(d), base, off); \
677 #define M_LDRD_UPDATE(d,base,off) \
679 assert((off) == +8); \
680 M_LDR_UPDATE(GET_HIGH_REG(d), base, 4); \
681 M_LDR_UPDATE(GET_LOW_REG(d), base, 4); \
684 #define M_STRD_UPDATE(d,base,off) \
686 assert((off) == -8); \
687 M_STR_UPDATE(GET_LOW_REG(d), base, -4); \
688 M_STR_UPDATE(GET_HIGH_REG(d) ,base, -4); \
691 #define GET_FIRST_REG(d) GET_HIGH_REG(d)
692 #define GET_SECOND_REG(d) GET_LOW_REG(d)
694 #endif /* defined(__ARMEB__) */
698 these are replacements for the original LDR/STR instructions, which can
699 handle longer offsets (up to 20bits). the original functions are now
702 /* ATTENTION: We use ITMP3 here, take into account that it gets destroyed.
703 This means that only ITMP1 and ITMP2 can be used in reg_of_var()!!!
705 /* ATTENTION2: It is possible to use ITMP3 as base reg. Remember that when
706 changing these macros!!!
709 #define M_LDR(d, base, offset) \
711 CHECK_OFFSET(offset, 0x0fffff); \
712 if (IS_OFFSET(offset, 0x000fff)) { \
713 M_LDR_INTERN(d, base, offset); \
715 /* we cannot handle REG_PC here */ \
716 assert((d) != REG_PC); \
717 if ((offset) > 0) { \
718 M_ADD_IMM(d, base, IMM_ROTL((offset) >> 12, 6)); \
719 M_LDR_INTERN(d, d, (offset) & 0x000fff); \
721 M_SUB_IMM(d, base, IMM_ROTL((-(offset)) >> 12, 6)); \
722 M_LDR_INTERN(d, d, -(-(offset) & 0x000fff)); \
727 #define M_LDR_NEGATIVE(d, base, offset) { \
728 /*assert((offset) <= 0);*/ \
729 if (IS_OFFSET(offset, 0x000fff)) { \
730 M_LDR_INTERN(d, base, offset); \
732 /* we cannot handle REG_PC here */ \
733 assert((d) != REG_PC); \
734 M_SUB_IMM(d, base, IMM_ROTL((-(offset)) >> 12, 6)); \
735 M_LDR_INTERN(d, d, -(-(offset) & 0x000fff)); \
739 #define M_LDRD(d, base, offset) \
741 CHECK_OFFSET(offset, 0x0fffff - 4); \
742 if (IS_OFFSET(offset, 0x000fff - 4)) { \
743 if (GET_FIRST_REG(d) != (base)) { \
744 M_LDRD_INTERN(d, base, offset); \
746 M_LDRD_ALTERN(d, base, offset); \
748 } else if (IS_OFFSET(offset, 0x000fff)) { \
749 dolog("M_LDRD: this offset seems to be complicated (%d)", offset); \
752 if ((offset) > 0) { \
753 M_ADD_IMM(GET_SECOND_REG(d), base, IMM_ROTL((offset) >> 12, 6)); \
754 M_LDRD_INTERN(d, GET_SECOND_REG(d), (offset) & 0x000fff); \
756 M_SUB_IMM(GET_SECOND_REG(d), base, IMM_ROTL((-(offset)) >> 12, 6)); \
757 M_LDRD_INTERN(d, GET_SECOND_REG(d), -(-(offset) & 0x000fff)); \
762 #if !defined(ENABLE_SOFTFLOAT)
763 #define M_LDFS(d, base, offset) \
765 CHECK_OFFSET(offset, 0x03ffff); \
766 if (IS_OFFSET(offset, 0x03ff)) { \
767 M_LDFS_INTERN(d, base, offset); \
769 if ((offset) > 0) { \
770 M_ADD_IMM(REG_ITMP3, base, IMM_ROTL((offset) >> 10, 5)); \
771 M_LDFS_INTERN(d, REG_ITMP3, (offset) & 0x03ff); \
773 M_SUB_IMM(REG_ITMP3, base, IMM_ROTL((-(offset)) >> 10, 5)); \
774 M_LDFS_INTERN(d, REG_ITMP3, -(-(offset) & 0x03ff)); \
779 #define M_LDFD(d, base, offset) \
781 CHECK_OFFSET(offset, 0x03ffff); \
782 if (IS_OFFSET(offset, 0x03ff)) { \
783 M_LDFD_INTERN(d, base, offset); \
785 if ((offset) > 0) { \
786 M_ADD_IMM(REG_ITMP3, base, IMM_ROTL((offset) >> 10, 5)); \
787 M_LDFD_INTERN(d, REG_ITMP3, (offset) & 0x03ff); \
789 M_SUB_IMM(REG_ITMP3, base, IMM_ROTL((-(offset)) >> 10, 5)); \
790 M_LDFD_INTERN(d, REG_ITMP3, -(-(offset) & 0x03ff)); \
795 #endif /* !defined(ENABLE_SOFTFLOAT) */
797 #define M_STR(d, base, offset) \
799 assert((d) != REG_ITMP3); \
800 CHECK_OFFSET(offset, 0x0fffff); \
801 if (IS_OFFSET(offset, 0x000fff)) { \
802 M_STR_INTERN(d, base, offset); \
804 if ((offset) > 0) { \
805 M_ADD_IMM(REG_ITMP3, base, IMM_ROTL((offset) >> 12, 6)); \
806 M_STR_INTERN(d, REG_ITMP3, (offset) & 0x000fff); \
808 M_SUB_IMM(REG_ITMP3, base, IMM_ROTL((-(offset)) >> 12, 6)); \
809 M_STR_INTERN(d, REG_ITMP3, -(-(offset) & 0x000fff)); \
814 #define M_STRD(d, base, offset) \
816 assert(GET_LOW_REG(d) != REG_ITMP3); \
817 assert(GET_HIGH_REG(d) != REG_ITMP3); \
818 CHECK_OFFSET(offset, 0x0fffff - 4); \
819 if (IS_OFFSET(offset, 0x000fff - 4)) { \
820 M_STRD_INTERN(d,base,offset); \
821 } else if (IS_OFFSET(offset, 0x000fff)) { \
822 dolog("M_STRD: this offset seems to be complicated (%d)", offset); \
825 if ((offset) > 0) { \
826 M_ADD_IMM(REG_ITMP3, base, IMM_ROTL((offset) >> 12, 6)); \
827 M_STRD_INTERN(d, REG_ITMP3, (offset) & 0x000fff); \
829 M_SUB_IMM(REG_ITMP3, base, IMM_ROTL((-(offset)) >> 12, 6)); \
830 M_STRD_INTERN(d, REG_ITMP3, -(-(offset) & 0x000fff)); \
835 #if !defined(ENABLE_SOFTFLOAT)
837 #define M_STFS(d, base, offset) \
839 CHECK_OFFSET(offset, 0x03ffff); \
840 if (IS_OFFSET(offset, 0x03ff)) { \
841 M_STFS_INTERN(d, base, offset); \
843 if ((offset) > 0) { \
844 M_ADD_IMM(REG_ITMP3, base, IMM_ROTL((offset) >> 10, 5)); \
845 M_STFS_INTERN(d, REG_ITMP3, (offset) & 0x03ff); \
847 M_SUB_IMM(REG_ITMP3, base, IMM_ROTL((-(offset)) >> 10, 5)); \
848 M_STFS_INTERN(d, REG_ITMP3, -(-(offset) & 0x03ff)); \
853 #define M_STFD(d, base, offset) \
855 CHECK_OFFSET(offset, 0x03ffff); \
856 if (IS_OFFSET(offset, 0x03ff)) { \
857 M_STFD_INTERN(d, base, offset); \
859 if ((offset) > 0) { \
860 M_ADD_IMM(REG_ITMP3, base, IMM_ROTL((offset) >> 10, 5)); \
861 M_STFD_INTERN(d, REG_ITMP3, (offset) & 0x03ff); \
863 M_SUB_IMM(REG_ITMP3, base, IMM_ROTL((-(offset)) >> 10, 5)); \
864 M_STFD_INTERN(d, REG_ITMP3, -(-(offset) & 0x03ff)); \
869 #endif /* !defined(ENABLE_SOFTFLOAT) */
871 /* M_???_IMM_EXT_MUL4:
872 extended immediate operations, to handle immediates lager than 8bit.
873 ATTENTION: the immediate is rotatet left by 2 (multiplied by 4)!!!
876 #define M_ADD_IMM_EXT_MUL4(d,n,imm) \
878 assert(d != REG_PC); \
879 assert((imm) >= 0 && (imm) <= 0x00ffffff); \
880 M_ADD_IMM(d, n, IMM_ROTL(imm, 1)); \
881 if ((imm) > 0x000000ff) M_ADD_IMM(d, d, IMM_ROTL((imm) >> 8, 5)); \
882 if ((imm) > 0x0000ffff) M_ADD_IMM(d, d, IMM_ROTL((imm) >> 16, 9)); \
885 #define M_SUB_IMM_EXT_MUL4(d,n,imm) \
887 assert(d != REG_PC); \
888 assert((imm) >= 0 && (imm) <= 0x00ffffff); \
889 M_SUB_IMM(d, n, IMM_ROTL(imm, 1)); \
890 if ((imm) > 0x000000ff) M_SUB_IMM(d, d, IMM_ROTL((imm) >> 8, 5)); \
891 if ((imm) > 0x0000ffff) M_SUB_IMM(d, d, IMM_ROTL((imm) >> 16, 9)); \
896 loads the integer/long value const into register d.
899 #define ICONST(d,c) emit_iconst(cd, (d), (c))
901 #define ICONST_CONDITIONAL(cond,d,const) \
902 if (IS_IMM(const)) { \
903 /* M_MOV_IMM */ M_DAT(cond,0x0d,d,0,0,1,const); \
905 disp = dseg_adds4(cd, const); \
906 /* TODO: implement this using M_DSEG_LOAD!!! */ \
907 /* M_LDR_INTERN */ CHECK_OFFSET(disp,0x0fff); M_MEM(cond,1,0,d,REG_PV,(disp<0)?-disp:disp,0,1,(disp<0)?0:1,0); \
910 #define LCONST(d,c) \
911 if (IS_IMM((c) >> 32)) { \
912 M_MOV_IMM(GET_HIGH_REG(d), (s4) ((s8) (c) >> 32)); \
913 ICONST(GET_LOW_REG(d), (s4) ((s8) (c) & 0xffffffff)); \
914 } else if (IS_IMM((c) & 0xffffffff)) { \
915 M_MOV_IMM(GET_LOW_REG(d), (s4) ((s8) (c) & 0xffffffff)); \
916 ICONST(GET_HIGH_REG(d), (s4) ((s8) (c) >> 32)); \
918 disp = dseg_add_s8(cd, (c)); \
919 M_LDRD(d, REG_PV, disp); \
923 #if !defined(ENABLE_SOFTFLOAT)
925 #define FCONST(d,c) \
927 disp = dseg_add_float(cd, (c)); \
928 M_LDFS(d, REG_PV, disp); \
931 #define DCONST(d,c) \
933 disp = dseg_add_double(cd, (c)); \
934 M_LDFD(d, REG_PV, disp); \
937 #endif /* !defined(ENABLE_SOFTFLOAT) */
941 used to recompute our PV (we use the IP for this) out of the current PC
942 ATTENTION: if you change this, you have to look at other functions as well!
943 Following things depend on it: asm_call_jit_compiler(); codegen_findmethod();
945 #define M_RECOMPUTE_PV(disp) \
946 disp += 8; /* we use PC relative addr. */ \
947 assert((disp & 0x03) == 0); \
948 assert(disp >= 0 && disp <= 0x03ffffff); \
949 M_SUB_IMM(REG_PV, REG_PC, IMM_ROTL(disp >> 2, 1)); \
950 if (disp > 0x000003ff) M_SUB_IMM(REG_PV, REG_PV, IMM_ROTL(disp >> 10, 5)); \
951 if (disp > 0x0003ffff) M_SUB_IMM(REG_PV, REG_PV, IMM_ROTL(disp >> 18, 9)); \
954 generates an integer-move from register a to b.
955 if a and b are the same int-register, no code will be generated.
958 #define M_INTMOVE(a,b) \
964 #define M_LNGMOVE(a,b) \
966 if (GET_HIGH_REG(a) == GET_LOW_REG(b)) { \
967 assert((GET_LOW_REG(a) != GET_HIGH_REG(b))); \
968 M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b)); \
969 M_INTMOVE(GET_LOW_REG(a), GET_LOW_REG(b)); \
971 M_INTMOVE(GET_LOW_REG(a), GET_LOW_REG(b)); \
972 M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b)); \
977 #if !defined(ENABLE_SOFTFLOAT)
980 generates a floating-point-move from register a to b.
981 if a and b are the same float-register, no code will be generated.
984 #define M_FLTMOVE(a,b) \
990 #define M_DBLMOVE(a,b) \
998 #if !defined(ENABLE_SOFTFLOAT)
999 /* M_CAST_INT_TO_FLT_TYPED:
1000 loads the value of the integer-register a (argument or result) into
1001 float-register Fb. (and vice versa)
1003 #define M_CAST_INT_TO_FLT_TYPED(t,a,Fb) \
1004 CHECK_FLT_REG(Fb); \
1005 if ((t) == TYPE_FLT) { \
1007 M_STR_UPDATE(a, REG_SP, -4); \
1008 M_LDFS_UPDATE(Fb, REG_SP, 4); \
1010 CHECK_INT_REG(GET_LOW_REG(a)); \
1011 CHECK_INT_REG(GET_HIGH_REG(a)); \
1012 M_STRD_UPDATE(a, REG_SP, -8); \
1013 M_LDFD_UPDATE(Fb, REG_SP, 8); \
1015 #define M_CAST_FLT_TO_INT_TYPED(t,Fa,b) \
1016 CHECK_FLT_REG(Fa); \
1017 if ((t) == TYPE_FLT) { \
1019 M_STFS_UPDATE(Fa, REG_SP, -4); \
1020 M_LDR_UPDATE(b, REG_SP, 4); \
1022 CHECK_INT_REG(GET_LOW_REG(b)); \
1023 CHECK_INT_REG(GET_HIGH_REG(b)); \
1024 M_STFD_UPDATE(Fa, REG_SP, -8); \
1025 M_LDRD_UPDATE(b, REG_SP, 8); \
1027 #endif /* !defined(ENABLE_SOFTFLOAT) */
1031 generates the compare part of an if-sequece
1032 uses M_CMP or M_CMP_IMM to do the compare
1033 ATTENTION: uses REG_ITMP3 as intermediate register
1035 #define M_COMPARE(reg, val) \
1036 if (IS_IMM(val)) { \
1037 M_CMP_IMM(reg, (val)); \
1038 } else if(IS_IMM(-(val))) { \
1039 M_CMN_IMM(reg, -(val)); \
1041 ICONST(REG_ITMP3, (val)); \
1042 M_CMP(reg, REG_ITMP3); \
1046 performs a long branch to an absolute address with return address in LR
1047 takes up 3 bytes of code space; address is hard-coded into code
1049 #define M_LONGBRANCH(adr) \
1050 M_ADD_IMM(REG_LR, REG_PC, 4); \
1051 M_LDR_INTERN(REG_PC, REG_PC, -4); \
1054 /* M_DSEG_LOAD/BRANCH:
1056 ATTENTION: if you change this, you have to look at the asm_call_jit_compiler!
1057 ATTENTION: we use M_LDR, so the same restrictions apply to us!
1059 #define M_DSEG_LOAD(reg, offset) \
1060 M_LDR_NEGATIVE(reg, REG_PV, offset)
1062 #define M_DSEG_BRANCH(offset) \
1063 if (IS_OFFSET(offset, 0x0fff)) { \
1064 M_MOV(REG_LR, REG_PC); \
1065 M_LDR_INTERN(REG_PC, REG_PV, offset); \
1067 /*assert((offset) <= 0);*/ \
1068 CHECK_OFFSET(offset,0x0fffff); \
1069 M_SUB_IMM(REG_ITMP3, REG_PV, ((-(offset) >> 12) & 0xff) | (((10) & 0x0f) << 8)); /*TODO: more to go*/ \
1070 M_MOV(REG_LR, REG_PC); \
1071 M_LDR_INTERN(REG_PC, REG_ITMP3, -(-(offset) & 0x0fff)); /*TODO: this looks ugly*/ \
1075 #define M_ILD(a,b,c) M_LDR(a,b,c)
1076 #define M_LLD(a,b,c) M_LDRD(a,b,c)
1078 #define M_ILD_INTERN(a,b,c) M_LDR_INTERN(a,b,c)
1079 #define M_LLD_INTERN(a,b,c) M_LDRD_INTERN(a,b,c)
1081 #define M_ALD(a,b,c) M_ILD(a,b,c)
1082 #define M_ALD_INTERN(a,b,c) M_ILD_INTERN(a,b,c)
1085 #define M_IST(a,b,c) M_STR(a,b,c)
1086 #define M_LST(a,b,c) M_STRD(a,b,c)
1088 #define M_IST_INTERN(a,b,c) M_STR_INTERN(a,b,c)
1089 #define M_LST_INTERN(a,b,c) M_STRD_INTERN(a,b,c)
1091 #define M_AST(a,b,c) M_IST(a,b,c)
1092 #define M_AST_INTERN(a,b,c) M_IST_INTERN(a,b,c)
1095 #if !defined(ENABLE_SOFTFLOAT)
1097 #define M_FLD(a,b,c) M_LDFS(a,b,c)
1098 #define M_DLD(a,b,c) M_LDFD(a,b,c)
1100 #define M_FLD_INTERN(a,b,c) M_LDFS_INTERN(a,b,c)
1101 #define M_DLD_INTERN(a,b,c) M_LDFD_INTERN(a,b,c)
1104 #define M_FST(a,b,c) M_STFS(a,b,c)
1105 #define M_DST(a,b,c) M_STFD(a,b,c)
1107 #define M_FST_INTERN(a,b,c) M_STFS_INTERN(a,b,c)
1108 #define M_DST_INTERN(a,b,c) M_STFD_INTERN(a,b,c)
1110 #endif /* !defined(ENABLE_SOFTFLOAT) */
1113 #endif /* _CODEGEN_H */
1117 * These are local overrides for various environment variables in Emacs.
1118 * Please do not remove this and leave it at the end of the file, where
1119 * Emacs will automagically detect them.
1120 * ---------------------------------------------------------------------
1123 * indent-tabs-mode: t
1127 * vim:noexpandtab:sw=4:ts=4: