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23 #include "../read_ordered.h"
25 #ifndef AO_ASSUME_WINDOWS98
26 /* CAS is always available */
27 # define AO_ASSUME_WINDOWS98
29 #include "common32_defs.h"
30 /* FIXME: Do _InterlockedOps really have a full memory barrier? */
31 /* (MSDN WinCE docs say nothing about it.) */
34 /* ARMv6 is the first architecture providing support for simple LL/SC. */
36 #include "../standard_ao_double_t.h"
38 /* If only a single processor is used, we can define AO_UNIPROCESSOR */
39 /* and do not need to access CP15 for ensuring a DMB at all. */
40 #ifdef AO_UNIPROCESSOR
41 AO_INLINE void AO_nop_full(void) {}
42 # define AO_HAVE_nop_full
44 /* AO_nop_full() is emulated using AO_test_and_set_full(). */
47 #include "../test_and_set_t_is_ao_t.h"
48 /* AO_test_and_set() is emulated using CAS. */
51 AO_load(const volatile AO_t *addr)
53 /* Cast away the volatile in case it adds fence semantics */
54 return (*(const AO_t *)addr);
59 AO_store_full(volatile AO_t *addr, AO_t value)
61 /* Emulate atomic store using CAS. */
62 AO_t old = AO_load(addr);
64 # ifdef AO_OLD_STYLE_INTERLOCKED_COMPARE_EXCHANGE
65 while ((current = (AO_t)_InterlockedCompareExchange(
66 (PVOID AO_INTERLOCKED_VOLATILE *)addr,
67 (PVOID)value, (PVOID)old)) != old)
70 while ((current = (AO_t)_InterlockedCompareExchange(
71 (LONG AO_INTERLOCKED_VOLATILE *)addr,
72 (LONG)value, (LONG)old)) != old)
76 #define AO_HAVE_store_full
78 /* FIXME: implement AO_compare_double_and_swap_double() */
80 #else /* _M_ARM < 6 */
82 /* Some slide set, if it has been red correctly, claims that Loads */
83 /* followed by either a Load or a Store are ordered, but nothing */
84 /* else is. It appears that SWP is the only simple memory barrier. */
85 #include "../all_atomic_load_store.h"
87 #include "../test_and_set_t_is_ao_t.h"
88 /* AO_test_and_set_full() is emulated using CAS. */
90 #endif /* _M_ARM < 6 */