2 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
3 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
4 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
7 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
8 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
10 * Permission is hereby granted to use or copy this program
11 * for any purpose, provided the above notices are retained on all copies.
12 * Permission to modify the code and to distribute modified code is granted,
13 * provided the above notices are retained, and a notice that the code was
14 * modified is included with the above copyright notice.
16 * Some of the machine specific code was borrowed from our GC distribution.
19 #include "../all_aligned_atomic_load_store.h"
21 /* Real X86 implementations, appear */
22 /* to enforce ordering between memory operations, EXCEPT that a later */
23 /* read can pass earlier writes, presumably due to the visible */
24 /* presence of store buffers. */
25 /* We ignore the fact that the official specs */
26 /* seem to be much weaker (and arguably too weak to be usable). */
28 #include "../ordered_except_wr.h"
30 #include "../test_and_set_t_is_char.h"
32 #include "../standard_ao_double_t.h"
37 /* Note: "mfence" (SSE2) is supported on all x86_64/amd64 chips. */
38 __asm__ __volatile__("mfence" : : : "memory");
41 #define AO_HAVE_nop_full
43 /* As far as we can tell, the lfence and sfence instructions are not */
44 /* currently needed or useful for cached memory accesses. */
47 AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
51 __asm__ __volatile__ ("lock; xaddq %0, %1" :
52 "=r" (result), "=m" (*p) : "0" (incr) /* , "m" (*p) */
57 #define AO_HAVE_fetch_and_add_full
59 AO_INLINE unsigned char
60 AO_char_fetch_and_add_full (volatile unsigned char *p, unsigned char incr)
64 __asm__ __volatile__ ("lock; xaddb %0, %1" :
65 "=q" (result), "=m" (*p) : "0" (incr) /* , "m" (*p) */
70 #define AO_HAVE_char_fetch_and_add_full
72 AO_INLINE unsigned short
73 AO_short_fetch_and_add_full (volatile unsigned short *p, unsigned short incr)
75 unsigned short result;
77 __asm__ __volatile__ ("lock; xaddw %0, %1" :
78 "=r" (result), "=m" (*p) : "0" (incr) /* , "m" (*p) */
83 #define AO_HAVE_short_fetch_and_add_full
85 AO_INLINE unsigned int
86 AO_int_fetch_and_add_full (volatile unsigned int *p, unsigned int incr)
90 __asm__ __volatile__ ("lock; xaddl %0, %1" :
91 "=r" (result), "=m" (*p) : "0" (incr) /* , "m" (*p) */
96 #define AO_HAVE_int_fetch_and_add_full
99 AO_or_full (volatile AO_t *p, AO_t incr)
101 __asm__ __volatile__ ("lock; orq %1, %0" :
102 "=m" (*p) : "r" (incr) /* , "m" (*p) */
106 #define AO_HAVE_or_full
108 AO_INLINE AO_TS_VAL_t
109 AO_test_and_set_full(volatile AO_TS_t *addr)
112 /* Note: the "xchg" instruction does not need a "lock" prefix */
113 /* Note 2: "xchgb" is not recognized by Sun CC assembler yet. */
114 __asm__ __volatile__("xchgl %0, %1"
115 : "=q"(oldval), "=m"(*addr)
116 : "0"(0xff) /* , "m"(*addr) */
118 return (AO_TS_VAL_t)oldval;
121 #define AO_HAVE_test_and_set_full
123 /* Returns nonzero if the comparison succeeded. */
125 AO_compare_and_swap_full(volatile AO_t *addr,
126 AO_t old, AO_t new_val)
129 __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
130 : "=m"(*addr), "=q"(result)
131 : "r" (new_val), "a"(old) : "memory");
135 #define AO_HAVE_compare_and_swap_full
137 #ifdef AO_CMPXCHG16B_AVAILABLE
138 /* NEC LE-IT: older AMD Opterons are missing this instruction.
139 * On these machines SIGILL will be thrown.
140 * Define AO_WEAK_DOUBLE_CAS_EMULATION to have an emulated
141 * (lock based) version available */
142 /* HB: Changed this to not define either by default. There are
143 * enough machines and tool chains around on which cmpxchg16b
144 * doesn't work. And the emulation is unsafe by our usual rules.
145 * Hoewever both are clearly useful in certain cases.
148 AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
149 AO_t old_val1, AO_t old_val2,
150 AO_t new_val1, AO_t new_val2)
153 __asm__ __volatile__("lock; cmpxchg16b %0; setz %1"
154 : "=m"(*addr), "=q"(result)
159 "b" (new_val1) : "memory");
162 #define AO_HAVE_compare_double_and_swap_double_full
164 /* this one provides spinlock based emulation of CAS implemented in */
165 /* atomic_ops.c. We probably do not want to do this here, since it is */
166 /* not atomic with respect to other kinds of updates of *addr. On the */
167 /* other hand, this may be a useful facility on occasion. */
168 #ifdef AO_WEAK_DOUBLE_CAS_EMULATION
169 int AO_compare_double_and_swap_double_emulation(volatile AO_double_t *addr,
170 AO_t old_val1, AO_t old_val2,
171 AO_t new_val1, AO_t new_val2);
174 AO_compare_double_and_swap_double_full(volatile AO_double_t *addr,
175 AO_t old_val1, AO_t old_val2,
176 AO_t new_val1, AO_t new_val2)
178 return AO_compare_double_and_swap_double_emulation(addr,
182 #define AO_HAVE_compare_double_and_swap_double_full
183 #endif /* AO_WEAK_DOUBLE_CAS_EMULATION */
184 #endif /* AO_CMPXCHG16B_AVAILABLE */