2 * Copyright (c) 2003 Hewlett-Packard Development Company, L.P.
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9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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23 /* The following really assume we have a 486 or better. */
24 /* If ASSUME_WINDOWS98 is defined, we assume Windows 98 or newer. */
26 #include "../all_aligned_atomic_load_store.h"
28 /* Real X86 implementations, except for some old WinChips, appear */
29 /* to enforce ordering between memory operations, EXCEPT that a later */
30 /* read can pass earlier writes, presumably due to the visible */
31 /* presence of store buffers. */
32 /* We ignore both the WinChips, and the fact that the official specs */
33 /* seem to be much weaker (and arguably too weak to be usable). */
35 #include "../ordered_except_wr.h"
37 #include "../test_and_set_t_is_char.h"
40 /* Seems like over-kill, but that's what MSDN recommends. */
41 /* And apparently winbase.h is not always self-contained. */
45 #define _InterlockedIncrement InterlockedIncrement
46 #define _InterlockedDecrement InterlockedDecrement
47 #define _InterlockedExchange InterlockedExchange
48 #define _InterlockedCompareExchange InterlockedCompareExchange
55 #pragma intrinsic (_ReadWriteBarrier)
62 LONG __cdecl _InterlockedIncrement(LONG volatile *Addend);
63 LONG __cdecl _InterlockedDecrement(LONG volatile *Addend);
64 LONG __cdecl _InterlockedExchangeAdd(LONG volatile* Target, LONG Addend);
65 LONG __cdecl _InterlockedExchange(LONG volatile* Target, LONG Value);
66 LONG __cdecl _InterlockedCompareExchange(LONG volatile* Dest,
67 LONG Exchange, LONG Comp);
72 #endif /* _MSC_VER >= 1400 */
74 #pragma intrinsic (_InterlockedIncrement)
75 #pragma intrinsic (_InterlockedDecrement)
76 #pragma intrinsic (_InterlockedExchange)
77 #pragma intrinsic (_InterlockedExchangeAdd)
78 #pragma intrinsic (_InterlockedCompareExchange)
80 #endif /* _MSC_VER < 1310 */
82 /* As far as we can tell, the lfence and sfence instructions are not */
83 /* currently needed or useful for cached memory accesses. */
85 /* Unfortunately mfence doesn't exist everywhere. */
86 /* IsProcessorFeaturePresent(PF_COMPARE_EXCHANGE128) is */
87 /* probably a conservative test for it? */
89 #if defined(AO_USE_PENTIUM4_INSTRS)
97 #define AO_HAVE_nop_full
101 /* We could use the cpuid instruction. But that seems to be slower */
102 /* than the default implementation based on test_and_set_full. Thus */
103 /* we omit that bit of misinformation here. */
108 AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
110 return _InterlockedExchangeAdd((LONG volatile*)p, (LONG)incr);
113 #define AO_HAVE_fetch_and_add_full
116 AO_fetch_and_add1_full (volatile AO_t *p)
118 return _InterlockedIncrement((LONG volatile *)p) - 1;
121 #define AO_HAVE_fetch_and_add1_full
124 AO_fetch_and_sub1_full (volatile AO_t *p)
126 return _InterlockedDecrement((LONG volatile *)p) + 1;
129 #define AO_HAVE_fetch_and_sub1_full
131 AO_INLINE AO_TS_VAL_t
132 AO_test_and_set_full(volatile AO_TS_t *addr)
138 xchg byte ptr [ebx],al ;
142 #define AO_HAVE_test_and_set_full
144 #ifdef AO_ASSUME_WINDOWS98
145 /* Returns nonzero if the comparison succeeded. */
147 AO_compare_and_swap_full(volatile AO_t *addr,
148 AO_t old, AO_t new_val)
150 return _InterlockedCompareExchange((LONG volatile *)addr,
151 (LONG)new_val, (LONG)old)
155 #define AO_HAVE_compare_and_swap_full
156 #endif /* ASSUME_WINDOWS98 */
159 # error wrong architecture
162 #include "../ao_t_is_int.h"