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4 * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
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18 /* There exist multiprocessor SoC ARM processors, so this matters. */
19 /* This needs to be augmented for later ARM (e.g. V7) procesors. */
21 /* I found a slide set that, if I read it correctly, claims that */
22 /* Loads followed by either a Load or Store are ordered, but nothing */
24 /* It appears that SWP is the only simple memory barrier. */
25 #include "../all_atomic_load_store.h"
27 #include "../read_ordered.h"
29 #include "../test_and_set_t_is_ao_t.h" /* Probably suboptimal */
33 AO_test_and_set_full(volatile AO_TS_t *addr) {
35 /* SWP on ARM is very similar to XCHG on x86. */
36 /* The first operand is the result, the second the value */
37 /* to be stored. Both registers must be different from addr. */
38 /* Make the address operand an early clobber output so it */
39 /* doesn't overlap with the other operands. The early clobber*/
40 /* on oldval is neccessary to prevent the compiler allocating */
41 /* them to the same register if they are both unused. */
42 __asm__ __volatile__("swp %0, %2, [%3]"
43 : "=&r"(oldval), "=&r"(addr)
49 #define AO_HAVE_test_and_set_full