projects
/
coreboot.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
[coreboot.git]
/
src
/
northbridge
/
amd
/
amdmct
/
mct_ddr3
/
mct_d.c
2010-09-05
Zheng Bao
Trivial. Currently the max frequency is preset as 400Mh...
blob
|
commitdiff
|
raw
2010-09-04
Kerry She
AMD DDR2 and DDR3 MCT function InitPhyCompensation...
blob
|
commitdiff
|
raw
|
diff to current
2010-08-31
Zheng Bao
Get Byte65/66 for register manufacture ID code. RegMan1...
blob
|
commitdiff
|
raw
|
diff to current
2010-08-30
Kerry She
Trivial syntax correction of AMD mct_ddr3 dir.
blob
|
commitdiff
|
raw
|
diff to current
2010-04-23
Zheng Bao
DDR3 support for AMD Fam10.
blob
|
commitdiff
|
raw
|
diff to current
projects / coreboot.git / history