Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build.
Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time
which model of I945 the driver is built for.
Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/684
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_MFCPGA478
- select NORTHBRIDGE_INTEL_I945GM
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_TI_PCIXX12
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_MFCPGA478
- select NORTHBRIDGE_INTEL_I945GM
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627EHG
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_441
- select NORTHBRIDGE_INTEL_I945GC
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_SMSC_LPC47M15X
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_MFCPGA478
- select NORTHBRIDGE_INTEL_I945GM
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627THG
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_MFCPGA478
- select NORTHBRIDGE_INTEL_I945GM
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_NSC_PC87382
select SUPERIO_NSC_PC87384
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_MFCPGA478
- select NORTHBRIDGE_INTEL_I945GM
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_RICOH_RL5C476
select SUPERIO_NSC_PC87382
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_MFCPGA478
- select NORTHBRIDGE_INTEL_I945GM
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SOUTHBRIDGE_TI_PCI7420
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-config NORTHBRIDGE_INTEL_I945GC
+config NORTHBRIDGE_INTEL_I945
bool
- select HAVE_DEBUG_RAM_SETUP
-config NORTHBRIDGE_INTEL_I945GM
- bool
+if NORTHBRIDGE_INTEL_I945
+
+config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
+ def_bool y
select HAVE_DEBUG_RAM_SETUP
-if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM
+config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ def_bool n
+config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+ def_bool n
config VGA_BIOS_ID
string
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_I945GC
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
#endif
}
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
#endif
}
static int memclk(void)
{
int offset = 0;
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
offset++;
#endif
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
return -1;
}
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
}
return 0xffff;
}
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
return nc;
}
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
/* Strength multiplier tables */
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
};
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
/**
* We add the indices according to our clocks from CLKCFG.
*/
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
static const u32 data_clock_crossing[] = {
0x00100401, 0x00000000, /* DDR400 FSB400 */
0xffffffff, 0xffffffff, /* nonexistant */
0xffffffff, 0xffffffff, /* nonexistant */
};
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
/* i945 G/P */
static const u32 data_clock_crossing[] = {
0xffffffff, 0xffffffff, /* nonexistant */
{
u8 clocks[2] = { 0, 0 };
-#if CONFIG_NORTHBRIDGE_INTEL_I945GM
+#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
#define CLOCKS_WIDTH 2
-#elif CONFIG_NORTHBRIDGE_INTEL_I945GC
+#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)