S3 feanture of SB800. Compiliant with SB700.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index e9325043b5922e43c8b250b21ec5bcb4b3e2bf67..248b1f50826870bf5a503fc97af90de72afc5926 100644 (file)
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -646,4 +646,54 @@ static int smbus_read_byte(u32 device, u32 address)
 {
        return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
+
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos) {
+       int i;
+       printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+
+       for (i = 0; i<size; i++) {
+               outb(nvram_pos, BIOSRAM_INDEX);
+               outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+               nvram_pos++;
+       }
+
+       return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+       u32 data = *old_dword;
+       int i;
+       for (i = 0; i<size; i++) {
+               outb(nvram_pos, BIOSRAM_INDEX);
+               data &= ~(0xff << (i * 8));
+               data |= inb(BIOSRAM_DATA) << (i *8);
+               nvram_pos++;
+       }
+       *old_dword = data;
+       printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size,
+               nvram_pos-size);
+       return nvram_pos;
+}
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+static int acpi_is_wakeup_early(void) {
+       u16 tmp;
+       tmp = inw(ACPI_PM1_CNT_BLK);
+       printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
+       return (((tmp & (7 << 10)) >> 10) == 3);
+}
+#endif
+
+struct cbmem_entry *get_cbmem_toc(void) {
+       uint32_t xdata = 0;
+       int xnvram_pos = 0xfc, xi;
+       for (xi = 0; xi<4; xi++) {
+               outb(xnvram_pos, BIOSRAM_INDEX);
+               xdata &= ~(0xff << (xi * 8));
+               xdata |= inb(BIOSRAM_DATA) << (xi *8);
+               xnvram_pos++;
+       }
+       return (struct cbmem_entry *) xdata;
+}
+
 #endif

diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index 870e36ad97b26b453da12da65d61cd269c294c26..cd9fb9ba9c61912b3cc57a28398346c822d051dc 100644 (file)
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -24,6 +24,8 @@
 #include "chip.h"
 
 /* Power management index/data registers */
+#define BIOSRAM_INDEX  0xcd4
+#define BIOSRAM_DATA   0xcd5
 #define PM_INDEX       0xcd6
 #define PM_DATA                0xcd7
 #define PM2_INDEX      0xcd0
@@ -47,6 +49,8 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
 #define REV_SB800_A11  0x11
 #define REV_SB800_A12  0x12
 
+void sb800_enable(device_t dev);
+
 #ifdef __PRE_RAM__
 void sb800_lpc_port80(void);
 void sb800_pci_port80(void);
@@ -55,7 +59,9 @@ void sb800_clk_output_48Mhz(void);
 /* void sb800_setup_sata_phys(struct device *dev); */
 #endif
 
-void sb800_enable(device_t dev);
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+
 void sb800_enable_usbdebug(unsigned int port);
 
 #endif /* SB800_H */