This patch corrects a coding error in the original implementation

of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
sets msr c001_102a bit 3 when bit 35 was intended.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 218a538c3576d33c17adf5e247aae8d48d09e2cf..e4f1ba426d5c344ca35979f538410f989e1e2f62 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -129,8 +129,8 @@ CAR_FAM10_out:
        /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
        rdmsr
 
-       /* Set bit 35 to 1 in EAX */
-       bts     $35, %eax
+       /* Set bit 35 to 1 in EAX:EDX */
+       bts     $35-32, %edx
 
        /* write back the modified register EDX:EAX to the MSR specified in ECX */
        wrmsr