- // Command register (offset 04)
- pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
- // Cache Line Size Register (offset 0x0C)
- pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
- // CardBus latency timer register (offset 1B)
- pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
- // Bridge control register (offset 3E)
- pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
- /** Enable change sub-vendor id
- * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
- pci_write_config32( dev, 0x80, 0x10 );
- pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
- // Now write the correct value for SCR
- // System Control Register (offset 0x80)
- pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
- // Multifunction routing register
- pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
- // Set Device Control Register (0x92) accordingly
- pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
- return;
+
+ /* Command (offset 04) */
+ pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
+ /* Cache Line Size (offset 0x0C) */
+ pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
+ /* CardBus latency timer (offset 0x1B) */
+ pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
+ /* Bridge control (offset 0x3E) */
+ pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
+ /*
+ * Enable change sub-vendor ID. Clear the bit 5 to enable to write
+ * to the sub-vendor/device ids at 40 and 42.
+ */
+ pci_write_config32(dev, 0x80, 0x10);
+ pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
+ /* Now write the correct value for SCR. */
+ /* System control (offset 0x80) */
+ pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
+ /* Multifunction routing */
+ pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
+ /* Set the device control register (0x92) accordingly. */
+ pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);