sys_clk : in std_logic;
sys_res_n : in std_logic;
-- PC-komm
- -- TODO: pins
+ pc_get : in std_logic;
+ pc_spalte : in hspalte;
+ pc_zeile : in hzeile;
+ pc_char : out hbyte;
+ pc_done : out std_logic;
-- Scanner
s_char : in hbyte;
s_take : in std_logic;
architecture beh of history is
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
- S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1);
+ S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
signal state_int, state_next : HISTORY_STATE;
signal was_bs_int, was_bs_next : std_logic;
signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
signal p_read_int, p_read_next : hbyte;
signal p_sp_read_int, p_sp_read_next : hspalte;
signal p_sp_write_int, p_sp_write_next : hspalte;
+ signal pc_char_next ,pc_char_int : hbyte;
+ signal pc_done_next, pc_done_int : std_logic;
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
p_sp_read_int <= (others => '0');
p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
+ pc_char_int <= (others => '0');
+ pc_done_int <= '0';
+
address_int <= (0 => '1', others => '0');
data_in_int <= x"00";
wr_int <= '0';
p_sp_read_int <= p_sp_read_next;
p_sp_write_int <= p_sp_write_next;
+ pc_char_int <= pc_char_next;
+ pc_done_int <= pc_done_next;
+
address_int <= address_next;
data_in_int <= data_in_next;
wr_int <= wr_next;
end process;
-- next state
- process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
+ process(state_int, d_get, pc_get, p_finished, s_take, s_backspace, was_bs_int,
p_rget, p_wtake, pos_int, s_cnt_int)
begin
state_next <= state_int;
state_next <= S_S_FIN;
elsif d_get = '1' then
state_next <= S_D_INIT;
+ elsif pc_get = '1' then
+ state_next <= S_PC_INIT;
end if;
when S_S_INIT =>
if s_backspace = '1' then
if d_get = '0' then
state_next <= SIDLE;
end if;
-
+ when S_PC_INIT =>
+ state_next <= S_PC_READ;
+ when S_PC_READ =>
+ if d_get = '0' then
+ state_next <= SIDLE;
+ end if;
when S_P_READ =>
state_next <= S_P_READ_DONE;
when S_P_READ_DONE =>
wr_next <= '0';
address_next <= address_int;
data_in_next <= data_in_int;
+ pc_done <= '0';
+ pc_char <= (others => '0');
p_rdone_next <= p_rdone_int;
p_wdone_next <= p_wdone_int;
p_read_next <= p_read_int;
d_char_next <= data_out;
d_done_next <= '1';
+ when S_PC_INIT =>
+ addr_tmp := (others => '0');
+ addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
+ mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
+ addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
+ addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
+ address_next <= addr_tmp;
+ when S_PC_READ =>
+ pc_char_next <= data_out;
+ pc_done_next <= '1';
when S_P_READ =>
wr_next <= '0';
spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);