// This file may be distributed under the terms of the GNU LGPLv3 license.
#include "geodevga.h" // geodevga_init
-#include "ioport.h" // outb
#include "farptr.h" // SET_FARVAR
#include "biosvar.h" // GET_BDA
#include "vgabios.h" // VGAREG_*
#include "util.h" // memset
-#include "stdvga.h" // VGAREG_VGA_CRTC_ADDRESS
+#include "stdvga.h" // stdvga_crtc_write
+#include "pci.h" // pci_config_readl
+#include "pci_regs.h" // PCI_BASE_ADDRESS_0
/****************************************************************
****************************************************************/
static void crtce_lock(void)
{
- outb(EXTENDED_REGISTER_LOCK , VGAREG_VGA_CRTC_ADDRESS);
- outb(CRTCE_LOCK, VGAREG_VGA_CRTC_DATA);
+ stdvga_crtc_write(VGAREG_VGA_CRTC_ADDRESS, EXTENDED_REGISTER_LOCK
+ , CRTCE_LOCK);
}
static void crtce_unlock(void)
{
- outb(EXTENDED_REGISTER_LOCK , VGAREG_VGA_CRTC_ADDRESS);
- outb(CRTCE_UNLOCK, VGAREG_VGA_CRTC_DATA);
+ stdvga_crtc_write(VGAREG_VGA_CRTC_ADDRESS, EXTENDED_REGISTER_LOCK
+ , CRTCE_UNLOCK);
}
static u8 crtce_read(u8 reg)
{
- u8 val;
-
crtce_unlock();
- outb(reg , VGAREG_VGA_CRTC_ADDRESS);
- val = inb(VGAREG_VGA_CRTC_DATA);
+ u8 val = stdvga_crtc_read(VGAREG_VGA_CRTC_ADDRESS, reg);
crtce_lock();
-
return val;
}
static void crtce_write(u8 reg, u8 val)
{
crtce_unlock();
- outb(reg , VGAREG_VGA_CRTC_ADDRESS);
- outb(val, VGAREG_VGA_CRTC_DATA);
+ stdvga_crtc_write(VGAREG_VGA_CRTC_ADDRESS, reg, val);
crtce_lock();
}
/* read fb-bar from pci, then point dc to the fb base */
dc_fb = dc_read(seg,DC_GLIU0_MEM_OFFSET);
- outl(GEODE_PCI_FB,PORT_PCI_CMD);
- fb = inl(PORT_PCI_DATA);
+ fb = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0);
if (fb!=dc_fb) {
dc_write(seg,DC_GLIU0_MEM_OFFSET,fb);
}
dprintf(2,"VP_SETUP\n");
/* set output to crt and RGB/YUV */
if (CONFIG_VGA_GEODEGX2)
- geode_msrWrite(VP_MSR_CONFIG_GX2,~0 ,~0xf8,0,0);
+ geode_msrWrite(VP_MSR_CONFIG_GX2, ~0, ~0xf8, 0, 0);
else
- geode_msrWrite(VP_MSR_CONFIG_LX,~0 ,~0xf8,0,0);
+ geode_msrWrite(VP_MSR_CONFIG_LX, ~0, ~0xf8, 0, 0);
/* get vp register base from pci */
- outl(GEODE_PCI_VP,PORT_PCI_CMD);
- vp = inl(PORT_PCI_DATA);
+ vp = pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_3);
/* Set mmio registers
* there may be some timing issues here, the reads seem
int i;
for (i=0; i<ARRAY_SIZE(new_crtc); i++) {
u8 *crtc = GET_GLOBAL(new_crtc[i]);
- if (!crtc)
- continue;
- struct vgamode_s *vmode_g = find_vga_entry(i);
- if (!vmode_g)
- continue;
- SET_VGA(vmode_g->crtc_regs, crtc);
+ if (crtc)
+ stdvga_override_crtc(i, crtc);
}
+ if (GET_GLOBAL(VgaBDF) < 0)
+ // Device should be at 00:01.1
+ SET_VGA(VgaBDF, pci_to_bdf(0, 1, 1));
ret |= vp_setup();
ret |= dc_setup();