This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / util / romcc / tests / raminit_test.c

diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c
index 9b6cf5d31c4791bd3b3c744fe2ad9a6b11283ac6..2c6fa8c750d845c66a8c29a4d23075db0e1efebb 100644 (file)
--- a/util/romcc/tests/raminit_test.c
+++ b/util/romcc/tests/raminit_test.c
@@ -83,27 +83,27 @@ static void pcibios_write_config_dword(
 }
 
 /* Base Address */
-#ifndef TTYS0_BASE
-#define TTYS0_BASE 0x3f8
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE 0x3f8
 #endif
 
-#ifndef TTYS0_BAUD
-#define TTYS0_BAUD 115200
+#ifndef CONFIG_TTYS0_BAUD
+#define CONFIG_TTYS0_BAUD 115200
 #endif
 
-#if ((115200%TTYS0_BAUD) != 0)
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
 #error Bad ttys0 baud rate
 #endif
 
-#define TTYS0_DIV      (115200/TTYS0_BAUD)
+#define CONFIG_TTYS0_DIV       (115200/CONFIG_TTYS0_BAUD)
 
 /* Line Control Settings */
-#ifndef TTYS0_LCS
+#ifndef CONFIG_TTYS0_LCS
 /* Set 8bit, 1 stop bit, no parity */
-#define TTYS0_LCS      0x3
+#define CONFIG_TTYS0_LCS       0x3
 #endif
 
-#define UART_LCS       TTYS0_LCS
+#define UART_LCS       CONFIG_TTYS0_LCS
 
 /* Data */
 #define UART_RBR 0x00
@@ -125,7 +125,7 @@ static void pcibios_write_config_dword(
 
 int uart_can_tx_byte(void)
 {
-       return inb(TTYS0_BASE + UART_LSR) & 0x20;
+       return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
 }
 
 void uart_wait_to_tx_byte(void)
@@ -136,14 +136,14 @@ void uart_wait_to_tx_byte(void)
 
 void uart_wait_until_sent(void)
 {
-       while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) 
+       while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) 
                ;
 }
 
 void uart_tx_byte(unsigned char data)
 {
        uart_wait_to_tx_byte();
-       outb(data, TTYS0_BASE + UART_TBR);
+       outb(data, CONFIG_TTYS0_BASE + UART_TBR);
        /* Make certain the data clears the fifos */
        uart_wait_until_sent();
 }
@@ -151,14 +151,14 @@ void uart_tx_byte(unsigned char data)
 void uart_init(void)
 {
        /* disable interrupts */
-       outb(0x0, TTYS0_BASE + UART_IER);
+       outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
        /* enable fifo's */
-       outb(0x01, TTYS0_BASE + UART_FCR);
+       outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
        /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
-       outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
-       outb(TTYS0_DIV & 0xFF,   TTYS0_BASE + UART_DLL);
-       outb((TTYS0_DIV >> 8) & 0xFF,    TTYS0_BASE + UART_DLM);
-       outb(UART_LCS, TTYS0_BASE + UART_LCR);
+       outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
+       outb(CONFIG_TTYS0_DIV & 0xFF,   CONFIG_TTYS0_BASE + UART_DLL);
+       outb((CONFIG_TTYS0_DIV >> 8) & 0xFF,    CONFIG_TTYS0_BASE + UART_DLM);
+       outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
 }
 
 void __console_tx_char(unsigned char byte)