#define OHCI_INTR_OC (1 << 30) /* ownership change */
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
-#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
-#define OHCI_INTR_SF (1 << 2) /* start frame */
-#define OHCI_INTR_RD (1 << 3) /* resume detect */
-#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
-#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
-#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
-#define OHCI_INTR_OC (1 << 30) /* ownership change */
-#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
-
/* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT (3 << 0)
#define OHCI_INTR_INIT \
- (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
- | OHCI_INTR_RD | OHCI_INTR_WDH)
+ (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE)
/* OHCI ROOT HUB REGISTER MASKS */
} ALIGNED(256);
struct endpoint_descriptor {
+ /* required by HC */
u32 flags;
u32 tailp;
u32 headp;
u32 nexted;
+
+ /* required by software */
+ u32 tdcount;
} ALIGNED(16);
#define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f
struct general_td {
+ /* required by HC */
u32 flags;
u32 cbp;
u32 nexttd;
u32 be;
+
+ /* required by software */
+ u32 bufaddr;
+ u32 buflen;
+ u32 pad1;
+ u32 pad2;
} ALIGNED(16);
#define OHCI_TD_BUFFER_ROUNDING 0x00040000