We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / via / vt8237r / vt8237r_lpc.c

diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 11b0279dcfcf0294e28ff0cf995217909afbc35f..2de64f03ce1dd0e1598a37954bd1ab5169d18a4f 100644 (file)
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -34,7 +34,6 @@
 #include "vt8237r.h"
 #include "chip.h"
 
-extern void dump_south(device_t dev);
 static void southbridge_init_common(struct device *dev);
 
 #if CONFIG_EPIA_VT8237R_INIT
@@ -66,7 +65,6 @@ static void pci_routing_fixup(struct device *dev)
 {
 #if CONFIG_EPIA_VT8237R_INIT
        device_t pdev;
-       u8 reg;
 #endif
 
        /* PCI PNP Interrupt Routing INTE/F - disable */
@@ -189,7 +187,7 @@ static void setup_pm(device_t dev)
         * 6 = SUSST# Deasserted Before PWRGD for STD
         * 5 = Keyboard/Mouse Swap
         * 4 = PWRGOOD reset on VT8237A/S
-        * 3 = GPO26/GPO27 is GPO 
+        * 3 = GPO26/GPO27 is GPO
         * 2 = Disable Alert on Lan
         * 1 = SUSCLK/GPO4
         * 0 = USB Wakeup
@@ -238,7 +236,7 @@ static void setup_pm(device_t dev)
        tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
 #if CONFIG_HAVE_ACPI_RESUME == 1
        acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
-       printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
+       printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
 #endif
        /* clear sleep */
        tmp &= ~(7 << 10);
@@ -248,10 +246,10 @@ static void setup_pm(device_t dev)
 
 static void vt8237r_init(struct device *dev)
 {
-       u8 enables, reg8;
-       
+       u8 enables;
+
 #if CONFIG_EPIA_VT8237R_INIT
-       printk_spew("Entering vt8237r_init, for EPIA.\n");
+       printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
        /*
         * TODO: Looks like stock BIOS can do this but causes a hang
         * Enable SATA LED, disable special CPU Frequency Change -
@@ -262,9 +260,9 @@ static void vt8237r_init(struct device *dev)
        enables = pci_read_config8(dev, 0xe5);
        enables |= 0x23;
        pci_write_config8(dev, 0xe5, enables);
-       
-       /* 
-        * Enable Flash Write Access. 
+
+       /*
+        * Enable Flash Write Access.
         * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
         */
        enables = pci_read_config8(dev, 0xe4);
@@ -276,14 +274,14 @@ static void vt8237r_init(struct device *dev)
        enables |= 0x80;
        pci_write_config8(dev, 0x4E, enables);
 
-#else 
-       printk_spew("Entering vt8237r_init.\n");
+#else
+       printk(BIOS_SPEW, "Entering vt8237r_init.\n");
        /*
         * Enable SATA LED, disable special CPU Frequency Change -
         * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
         */
        pci_write_config8(dev, 0xe5, 0x09);
-       
+
        /* REQ5 as PCI request input - should be together with INTE-INTH. */
        pci_write_config8(dev, 0xe4, 0x4);
 #endif
@@ -318,7 +316,7 @@ static void vt8237r_init(struct device *dev)
        outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
 #endif
 
-       printk_spew("Leaving %s.\n", __func__);
+       printk(BIOS_SPEW, "Leaving %s.\n", __func__);
 }
 
 static void vt8237s_init(struct device *dev)
@@ -331,7 +329,7 @@ static void vt8237s_init(struct device *dev)
                           (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
 
        /*
-        * REQ5 as PCI request input - should be together with INTE-INTH. 
+        * REQ5 as PCI request input - should be together with INTE-INTH.
         */
        pci_write_config8(dev, 0xe4, 0x04);
 
@@ -492,7 +490,7 @@ static void vt8237r_read_resources(device_t dev)
 
        /* Fixed APIC resource */
        res = new_resource(dev, 0x44);
-       res->base = VT8237R_APIC_BASE;
+       res->base = IO_APIC_ADDR;
        res->size = 256;
        res->limit = 0xffffffffUL;
        res->align = 8;
@@ -507,29 +505,18 @@ static void vt8237r_read_resources(device_t dev)
        res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-/**
- * The VT8237R is not a PCI bridge and has no resources of its own (other
- * than standard PC I/O addresses), however it does control the ISA bus
- * and so we need to manually call enable childrens resources on that bus.
- */
-static void vt8237r_enable_resources(device_t dev)
-{
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static void init_keyboard(struct device *dev)
 {
        u8 regval = pci_read_config8(dev, 0x51);
        if (regval & 0x1)
-               init_pc_keyboard(0x60, 0x64, 0);
+               pc_keyboard_init(0);
 }
 
 static void southbridge_init_common(struct device *dev)
 {
        vt8237_common_init(dev);
        pci_routing_fixup(dev);
-       setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID);
+       setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
        setup_i8259();
        init_keyboard(dev);
 }
@@ -537,16 +524,16 @@ static void southbridge_init_common(struct device *dev)
 static const struct device_operations vt8237r_lpc_ops_s = {
        .read_resources         = vt8237r_read_resources,
        .set_resources          = pci_dev_set_resources,
-       .enable_resources       = vt8237r_enable_resources,
-       .init                   = &vt8237s_init,
+       .enable_resources       = pci_dev_enable_resources,
+       .init                   = vt8237s_init,
        .scan_bus               = scan_static_bus,
 };
 
 static const struct device_operations vt8237r_lpc_ops_r = {
        .read_resources         = vt8237r_read_resources,
        .set_resources          = pci_dev_set_resources,
-       .enable_resources       = vt8237r_enable_resources,
-       .init                   = &vt8237r_init,
+       .enable_resources       = pci_dev_enable_resources,
+       .init                   = vt8237r_init,
        .scan_bus               = scan_static_bus,
 };