#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
-
#include <pc80/mc146818rtc.h>
-
-#include "vt8235.h"
+#include <arch/ioapic.h>
#include "chip.h"
/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
static void pci_routing_fixup(struct device *dev)
{
- printk_info("%s: dev is %p\n", __func__, dev);
+ printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
/* set up PCI IRQ routing */
pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
// firewire built into southbridge
- printk_info("setting firewire\n");
+ printk(BIOS_INFO, "setting firewire\n");
pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins));
// Standard usb components
- printk_info("setting usb\n");
+ printk(BIOS_INFO, "setting usb\n");
pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
// VT8235 + sound hardware
- printk_info("setting vt8235\n");
+ printk(BIOS_INFO, "setting vt8235\n");
pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins));
// Ethernet built into southbridge
- printk_info("setting ethernet\n");
+ printk(BIOS_INFO, "setting ethernet\n");
pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
// VGA
- printk_info("setting vga\n");
+ printk(BIOS_INFO, "setting vga\n");
pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
// PCI slot
- printk_info("setting pci slot\n");
+ printk(BIOS_INFO, "setting pci slot\n");
pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
- // Cardbus slot
- printk_info("setting cardbus slot\n");
+ // Cardbus slot
+ printk(BIOS_INFO, "setting cardbus slot\n");
pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
// Via 2 slot riser card 2nd slot
- printk_info("setting riser slot\n");
+ printk(BIOS_INFO, "setting riser slot\n");
pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
- printk_spew("%s: DONE\n", __func__);
+ printk(BIOS_SPEW, "%s: DONE\n", __func__);
}
-/*
+/*
* Set up the power management capabilities directly into ACPI mode. This
* avoids having to handle any System Management Interrupts (SMI's) which I
* can't figure out how to do !!!!
- */
+ */
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
{
-
// Set gen config 0
pci_write_config8(dev, 0x80, 0x20);
- // Set ACPI base address to IO 0x4000
+ // Set ACPI base address to IO 0x400
pci_write_config16(dev, 0x88, 0x0401);
-
+
// set ACPI irq to 5
pci_write_config8(dev, 0x82, 0x45);
outw(0xffff, 0x420);
outw(0xffff, 0x428);
outl(0xffffffff, 0x430);
-
+
outw(0x0, 0x424);
outw(0x0, 0x42a);
outw(0x1, 0x42c);
static void vt8235_init(struct device *dev)
{
unsigned char enables;
-
- printk_debug("vt8235 init\n");
+
+ printk(BIOS_DEBUG, "vt8235 init\n");
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
-
+
// Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x7f);
-
+
// Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
+ // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
enables |= 0x45;
pci_write_config8(dev, 0x40, enables);
-
+
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev, 0x42);
enables |= 0xf0;
pci_write_config8(dev, 0x42, enables);
-
+
/* Set 0x58 to 0x03 to match Award */
pci_write_config8(dev, 0x58, 0x03);
enables = pci_read_config8(dev, 0x4a);
enables |= 0x08;
pci_write_config8(dev, 0x4a, enables);
-
+
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
-
+
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
-
-
+
+
/* enable serial irq */
pci_write_config8(dev, 0x52, 0x9);
// Power management setup
setup_pm(dev);
-
+
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
-
+
// Start the rtc
rtc_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
device has a resource to set - so set a dummy one */
-void vt8235_read_resources(device_t dev)
+static void vt8235_read_resources(device_t dev)
{
+ struct resource *res;
- struct resource *resource;
pci_dev_read_resources(dev);
- resource = new_resource(dev, 1);
- resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED;
- resource->size = 2;
- resource->base = 0x2e;
+ res = new_resource(dev, 1);
+ res->base = 0x0UL;
+ res->size = 0x1000UL;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-void vt8235_set_resources(device_t dev)
+
+static void vt8235_set_resources(device_t dev)
{
- struct resource *resource;
+ //struct resource *resource;
//resource = find_resource(dev,1);
//resource->flags |= IORESOURCE_STORED;
pci_dev_set_resources(dev);
}
-void vt8235_enable_resources(device_t dev)
-{
- /* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses)
- however it does control the isa bus and so we need to manually call enable childrens resources on that bus */
- pci_dev_enable_resources(dev);
- enable_childrens_resources(dev);
-
-}
-
static void southbridge_init(struct device *dev)
{
vt8235_init(dev);
static struct device_operations vt8235_lpc_ops = {
.read_resources = vt8235_read_resources,
.set_resources = vt8235_set_resources,
- .enable_resources = vt8235_enable_resources,
- .init = &southbridge_init,
+ .enable_resources = pci_dev_enable_resources,
+ .init = southbridge_init,
.scan_bus = scan_static_bus,
};
projects / coreboot.git / blobdiff