We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
[coreboot.git] / src / southbridge / via / vt8235 / vt8235_lpc.c
index 153c405513e01463ed9b1abddff94ca030898865..b355ad0d88fec3c197eda93ab41942daba4d5e53 100644 (file)
@@ -4,9 +4,8 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
-
 #include <pc80/mc146818rtc.h>
-
+#include <arch/ioapic.h>
 #include "chip.h"
 
 /* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C.
@@ -228,7 +227,7 @@ static void vt8235_read_resources(device_t dev)
        res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
@@ -241,14 +240,6 @@ static void vt8235_set_resources(device_t dev)
        pci_dev_set_resources(dev);
 }
 
-static void vt8235_enable_resources(device_t dev)
-{
-       /* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses)
-           however it does control the isa bus and so we need to manually call enable childrens resources on that bus */
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static void southbridge_init(struct device *dev)
 {
        vt8235_init(dev);
@@ -258,8 +249,8 @@ static void southbridge_init(struct device *dev)
 static struct device_operations vt8235_lpc_ops = {
        .read_resources   = vt8235_read_resources,
        .set_resources    = vt8235_set_resources,
-       .enable_resources = vt8235_enable_resources,
-       .init             = &southbridge_init,
+       .enable_resources = pci_dev_enable_resources,
+       .init             = southbridge_init,
        .scan_bus         = scan_static_bus,
 };