/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2003 Linux Networx
* Copyright (C) 2003 SuSE Linux AG
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
+#include <stdlib.h>
#include "mcp55.h"
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base)
-{
- int i;
- unsigned long value_low, value_high;
-// unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid()<<(56-32);
-
- l = (unsigned long *) ioapic_base;
-
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#define SLOW_CPU_OFF 0
-#define SLOW_CPU__ON 1
+#define SLOW_CPU_OFF 0
+#define SLOW_CPU__ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-static void lpc_common_init(device_t dev)
+static void lpc_common_init(device_t dev, int master)
{
uint8_t byte;
- uint32_t dword;
+ uint32_t ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
-
- setup_ioapic(dword);
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ if (master)
+ setup_ioapic(ioapic_base, 0);
+ else
+ clear_ioapic(ioapic_base);
}
static void lpc_slave_init(device_t dev)
{
- lpc_common_init(dev);
+ lpc_common_init(dev, 0);
}
-#if 0
static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
pci_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
- printk_debug("enabling HPET @0x%x\n", hpet_address);
+ printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
}
-#endif
static void lpc_init(device_t dev)
{
int on;
int nmi_option;
- lpc_common_init(dev);
+ lpc_common_init(dev, 1);
#if 0
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
-
#endif
/* power after power fail */
#if 1
- on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
- printk_info("set power %s after power fail\n", on?"on":"off");
+ printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
#endif
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
- printk_debug("Throttling CPU %2d.%1.1d percent.\n",
- (on*12)+(on>>1),(on&1)*5);
+ printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
+ (on*12)+(on>>1),(on&1)*5);
}
#if 0
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
- outb(0x70, byte);
+ outb(byte, 0x70);
}
/* Initialize the real time clock */
isa_dma_init();
/* Initialize the High Precision Event Timers */
-// enable_hpet(dev);
+ enable_hpet(dev);
}
static void mcp55_lpc_read_resources(device_t dev)
{
struct resource *res;
- unsigned long index;
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
+ /* Get the normal PCI resources of this device. */
+ /* We got one for APIC, or one more for TRAP. */
+ pci_dev_read_resources(dev);
- /* Add an extra subtractive resource for both memory and I/O */
+ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
/**
*
* @param dev the device whos children's resources are to be enabled
*
- * This function is call by the global enable_resources() indirectly via the
- * device_operation::enable_resources() method of devices.
- *
- * Indirect mutual recursion:
- * enable_childrens_resources() -> enable_resources()
- * enable_resources() -> device_operation::enable_resources()
- * device_operation::enable_resources() -> enable_children_resources()
*/
static void mcp55_lpc_enable_childrens_resources(device_t dev)
{
- unsigned link;
uint32_t reg, reg_var[4];
int i;
int var_num = 0;
+ struct bus *link;
reg = pci_read_config32(dev, 0xa0);
- for (link = 0; link < dev->links; link++) {
+ for (link = dev->link_list; link; link = link->next) {
device_t child;
- for (child = dev->link[link].children; child; child = child->sibling) {
- enable_resources(child);
- if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
- for(i=0;i<child->resources;i++) {
- struct resource *res;
+ for (child = link->children; child; child = child->sibling) {
+ if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+ struct resource *res;
+ for(res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long
- res = &child->resource[i];
if(!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
- printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
+ printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) {
case 0x3f8: // COM1
reg |= (1<<0); break;
// .enable = mcp55_enable,
.ops_pci = &lops_pci,
};
-static struct pci_driver lpc_driver __pci_driver = {
+static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC,
};
-static struct pci_driver lpc_driver_pro __pci_driver = {
+static const struct pci_driver lpc_driver_pro __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO,
};
-static struct pci_driver lpc_driver_lpc2 __pci_driver = {
+static const struct pci_driver lpc_driver_lpc2 __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2,
};
-static struct pci_driver lpc_driver_lpc3 __pci_driver = {
+static const struct pci_driver lpc_driver_lpc3 __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3,
};
-static struct pci_driver lpc_driver_lpc4 __pci_driver = {
+static const struct pci_driver lpc_driver_lpc4 __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4,
};
-static struct pci_driver lpc_driver_lpc5 __pci_driver = {
+static const struct pci_driver lpc_driver_lpc5 __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5,
};
-static struct pci_driver lpc_driver_lpc6 __pci_driver = {
+static const struct pci_driver lpc_driver_lpc6 __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6,
.ops_pci = &lops_pci,
};
-static struct pci_driver lpc_driver_slave __pci_driver = {
+static const struct pci_driver lpc_driver_slave __pci_driver = {
.ops = &lpc_slave_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE,
projects / coreboot.git / blobdiff