#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
-
-#define DEBUG_SMI
#define APM_CNT 0xb2
-#define CST_CONTROL 0x85 // 0x85 crashes the box
-#define PST_CONTROL 0x80 // 0x80 crashes the box
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
#define ACPI_DISABLE 0x1e
#define ACPI_ENABLE 0xe1
#define GNVS_UPDATE 0xea
#define G_SMRANE (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-/* ICH7 */
-#define PM1_STS 0x00
-#define PM1_EN 0x02
-#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define GBL_RLS (1 << 2)
-#define BM_RLD (1 << 1)
-#define SCI_EN (1 << 0)
-#define PM1_TMR 0x08
-#define PROC_CNT 0x10
-#define LV2 0x14
-#define LV3 0x15
-#define LV4 0x16
-#define PM2_CNT 0x20 // mobile only
-#define GPE0_STS 0x28
-#define GPE0_EN 0x2c
-#define PME_B0_EN (1 << 13)
-#define SMI_EN 0x30
-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define MCSMI_EN (1 << 11) // Trap microcontroller range access
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
-#define SMI_STS 0x34
-#define ALT_GP_SMI_EN 0x38
-#define ALT_GP_SMI_STS 0x3a
-#define GPE_CNTL 0x42
-#define DEVACT_STS 0x44
-#define SS_CNT 0x50
-#define C3_RES 0x54
-
#include "i82801gx_nvs.h"
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
u16 pmbase = DEFAULT_PMBASE;
+u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
void *smi1 = (void *)0x0;
/**
- * @brief read and clear PM1_STS
+ * @brief read and clear PM1_STS
* @return PM1_STS register
*/
static u16 reset_pm1_status(void)
{
u16 reg16;
-
+
reg16 = inw(pmbase + PM1_STS);
/* set status bits are cleared by writing 1 to them */
outw(reg16, pmbase + PM1_STS);
-
+
return reg16;
}
static void dump_pm1_status(u16 pm1_sts)
{
- printk_debug("PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk_debug("WAK ");
- if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk_debug("RTC ");
- if (pm1_sts & (1 << 8)) printk_debug("PWRBTN ");
- if (pm1_sts & (1 << 5)) printk_debug("GBL ");
- if (pm1_sts & (1 << 4)) printk_debug("BM ");
- if (pm1_sts & (1 << 0)) printk_debug("TMROF ");
- printk_debug("\n");
+ printk(BIOS_SPEW, "PM1_STS: ");
+ if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
+ if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
+ if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
+ if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
+ if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
+ if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
+ if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
+ if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
+ printk(BIOS_SPEW, "\n");
+ int reg16 = inw(pmbase + PM1_EN);
+ printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
}
/**
- * @brief read and clear SMI_STS
+ * @brief read and clear SMI_STS
* @return SMI_STS register
*/
static u32 reset_smi_status(void)
{
u32 reg32;
-
+
reg32 = inl(pmbase + SMI_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + SMI_STS);
-
+
return reg32;
}
static void dump_smi_status(u32 smi_sts)
{
- printk_debug("SMI_STS: ");
- if (smi_sts & (1 << 26)) printk_debug("SPI ");
- if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
- if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
- if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
- if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
- if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
- if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
- if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
- if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
- if (smi_sts & (1 << 13)) printk_debug("TCO ");
- if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
- if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
- if (smi_sts & (1 << 10)) printk_debug("GPI ");
- if (smi_sts & (1 << 9)) printk_debug("GPE0 ");
- if (smi_sts & (1 << 8)) printk_debug("PM1 ");
- if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR ");
- if (smi_sts & (1 << 5)) printk_debug("APM ");
- if (smi_sts & (1 << 4)) printk_debug("SLP_SMI ");
- if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB ");
- if (smi_sts & (1 << 2)) printk_debug("BIOS ");
- printk_debug("\n");
+ printk(BIOS_DEBUG, "SMI_STS: ");
+ if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+ if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+ if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+ if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+ if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+ if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+ if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+ if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+ if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+ if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+ if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+ if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+ if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+ if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
+ if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
+ if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+ if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
+ if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
+ if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+ if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
+ printk(BIOS_DEBUG, "\n");
}
static u32 reset_gpe0_status(void)
{
u32 reg32;
-
+
reg32 = inl(pmbase + GPE0_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + GPE0_STS);
-
+
return reg32;
}
static void dump_gpe0_status(u32 gpe0_sts)
{
int i;
- printk_debug("GPE0_STS: ");
+ printk(BIOS_DEBUG, "GPE0_STS: ");
for (i=31; i<= 16; i--) {
- if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+ if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
}
- if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
- if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
- if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
- if (gpe0_sts & (1 << 11)) printk_debug("PME ");
- if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
- if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP ");
- if (gpe0_sts & (1 << 8)) printk_debug("RI ");
- if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK ");
- if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI ");
- if (gpe0_sts & (1 << 5)) printk_debug("AC97 ");
- if (gpe0_sts & (1 << 4)) printk_debug("USB2 ");
- if (gpe0_sts & (1 << 3)) printk_debug("USB1 ");
- if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG ");
- if (gpe0_sts & (1 << 0)) printk_debug("THRM ");
- printk_debug("\n");
+ if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+ if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+ if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+ if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+ if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+ if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
+ if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
+ if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
+ if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
+ if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
+ if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
+ if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
+ if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+ if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
+ printk(BIOS_DEBUG, "\n");
}
/**
- * @brief read and clear TCOx_STS
+ * @brief read and clear TCOx_STS
* @return TCOx_STS registers
*/
static u32 reset_tco_status(void)
{
u32 tcobase = pmbase + 0x60;
u32 reg32;
-
+
reg32 = inl(tcobase + 0x04);
/* set status bits are cleared by writing 1 to them */
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
if (reg32 & (1 << 18))
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
-
+
return reg32;
}
static void dump_tco_status(u32 tco_sts)
{
- printk_debug("TCO_STS: ");
- if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
- if (tco_sts & (1 << 18)) printk_debug("BOOT ");
- if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
- if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
- if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
- if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
- if (tco_sts & (1 << 9)) printk_debug("DMISCI ");
- if (tco_sts & (1 << 8)) printk_debug("BIOSWR ");
- if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY ");
- if (tco_sts & (1 << 3)) printk_debug("TIMEOUT ");
- if (tco_sts & (1 << 2)) printk_debug("TCO_INT ");
- if (tco_sts & (1 << 1)) printk_debug("SW_TCO ");
- if (tco_sts & (1 << 0)) printk_debug("NMI2SMI ");
- printk_debug("\n");
+ printk(BIOS_DEBUG, "TCO_STS: ");
+ if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+ if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+ if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+ if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+ if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+ if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+ if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
+ if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
+ if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+ if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
+ if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
+ if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
+ if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
+ printk(BIOS_DEBUG, "\n");
}
/* We are using PCIe accesses for now
{
switch (smif) {
case 0x32:
- printk_debug("OS Init\n");
+ printk(BIOS_DEBUG, "OS Init\n");
+ /* gnvs->smif:
+ * On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ */
gnvs->smif = 0;
- break;
- default:
- /* Not handled */
- return 0;
+ return 1; /* IO trap handled */
}
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1; /* IO trap handled */
+ /* Not handled */
+ return 0;
}
/**
outb(reg8, pmbase + SMI_EN);
}
+static void busmaster_disable_on_bus(int bus)
+{
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
+}
+
static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
{
u8 reg8;
u32 reg32;
u8 slp_typ;
- /* FIXME: the power state on boot should be read from
+ /* FIXME: the power state on boot should be read from
* CMOS or even better from GNVS. Right now it's hard
* coded at compile time.
*/
- u8 s5pwr = MAINBOARD_POWER_ON_AFTER_FAIL;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT);
- printk_spew("SMI#: SLP = 0x%08x\n", reg32);
+ printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = (reg32 >> 10) & 7;
/* Next, do the deed.
*/
switch (slp_typ) {
- case 0: printk_debug("SMI#: Entering S0 (On)\n"); break;
- case 1: printk_debug("SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+ case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+ case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
case 5:
- printk_debug("SMI#: Entering S3 (Suspend-To-RAM)\n");
+ printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
- case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+ case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
case 7:
- printk_debug("SMI#: Entering S5 (Soft Power off)\n");
-#if 0
- /* Set PME_B0_EN before going to S5 */
- reg32 = inl(pmbase + GPE0_EN);
- reg32 |= PME_B0_EN;
- outl(reg32, pmbase + GPE0_EN);
-#endif
+ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+
+ outl(0, pmbase + GPE0_EN);
+
/* Should we keep the power state after a power loss?
* In case the setting is "ON" or "OFF" we don't have
* to do anything. But if it's "KEEP" we have to switch
reg8 |= 1;
pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
}
+
+ /* also iterates over all bridges on bus 0 */
+ busmaster_disable_on_bus(0);
break;
- default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break;
+ default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
}
/* Write back to the SLP register to cause the originally intended
- * event again. We need to set BIT13 (SLP_EN) though to make the
+ * event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
outl(reg32 | SLP_EN, pmbase + PM1_CNT);
* some kind of race condition in Linux
* and causes a kernel oops
*/
- printk_debug("C-state control\n");
+ printk(BIOS_DEBUG, "C-state control\n");
break;
case PST_CONTROL:
/* Calling this function seems to cause
* some kind of race condition in Linux
* and causes a kernel oops
*/
- printk_debug("P-state control\n");
+ printk(BIOS_DEBUG, "P-state control\n");
break;
case ACPI_DISABLE:
pmctrl = inl(pmbase + PM1_CNT);
pmctrl &= ~SCI_EN;
outl(pmctrl, pmbase + PM1_CNT);
- printk_debug("SMI#: ACPI disabled.\n");
+ printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case ACPI_ENABLE:
pmctrl = inl(pmbase + PM1_CNT);
pmctrl |= SCI_EN;
outl(pmctrl, pmbase + PM1_CNT);
- printk_debug("SMI#: ACPI enabled.\n");
+ printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case GNVS_UPDATE:
+ if (smm_initialized) {
+ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
+ return;
+ }
gnvs = *(global_nvs_t **)0x500;
tcg = *(void **)0x504;
smi1 = *(void **)0x508;
- printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
+ smm_initialized = 1;
+ printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
break;
default:
- printk_debug("SMI#: Unknown function APM_CNT=%02x\n", reg8);
+ printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
}
}
pm1_sts = reset_pm1_status();
dump_pm1_status(pm1_sts);
+
+ /* While OSPM is not active, poweroff immediately
+ * on a power button event.
+ */
+ if (pm1_sts & PWRBTN_STS) {
+ // power button pressed
+ u32 reg32;
+ reg32 = (7 << 10) | (1 << 13);
+ outl(reg32, pmbase + PM1_CNT);
+ }
}
static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
dump_gpe0_status(gpe0_sts);
}
+void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
+
+static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u16 reg16;
+ reg16 = inw(pmbase + ALT_GP_SMI_STS);
+ outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+ reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+
+ if (mainboard_smi_gpi) {
+ mainboard_smi_gpi(reg16);
+ } else {
+ if (reg16)
+ printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
+ }
+}
+
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
{
u32 reg32;
if ((reg32 & MCSMI_EN) == 0)
return;
- printk_debug("Microcontroller SMI.\n");
+ printk(BIOS_DEBUG, "Microcontroller SMI.\n");
}
* resolute answer would be to power down the
* box.
*/
- printk_debug("Switching back to RO\n");
+ printk(BIOS_DEBUG, "Switching back to RO\n");
pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
- printk_debug("TCO Timeout.\n");
+ printk(BIOS_DEBUG, "TCO Timeout.\n");
} else if (!tco_sts) {
dump_tco_status(tco_sts);
}
if ((reg32 & PERIODIC_EN) == 0)
return;
- printk_debug("Periodic SMI.\n");
+ printk(BIOS_DEBUG, "Periodic SMI.\n");
}
static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
/* IOTRAP(0) SMIC */
if (IOTRAP(0)) {
if (!(trap_cycle & (1 << 24))) { // It's a write
- printk_debug("SMI1 command\n");
+ printk(BIOS_DEBUG, "SMI1 command\n");
data = RCBA32(0x1e18);
data &= mask;
// if (smi1)
// Fall through to debug
}
- printk_debug(" trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk_debug(" TRAP = %d\n", i);
- printk_debug(" AHBE = %x\n", (trap_cycle >> 16) & 0xf);
- printk_debug(" MASK = 0x%08x\n", mask);
- printk_debug(" read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
+ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+ for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
+ printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
+ printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) {
/* Write Cycle */
data = RCBA32(0x1e18);
- printk_debug(" iotrap written data = 0x%08x\n", data);
+ printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
}
#undef IOTRAP
}
-typedef void (*smi_handler)(unsigned int node,
+typedef void (*smi_handler_t)(unsigned int node,
smm_state_save_area_t *state_save);
-smi_handler southbridge_smi[32] = {
+smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
NULL, // [1] reserved
NULL, // [2] BIOS_STS
NULL, // [7] reserved
southbridge_smi_pm1, // [8] PM1_STS
southbridge_smi_gpe0, // [9] GPE0_STS
- NULL, // [10] GPI_STS
+ southbridge_smi_gpi, // [10] GPI_STS
southbridge_smi_mc, // [11] MCSMI_STS
NULL, // [12] DEVMON_STS
southbridge_smi_tco, // [13] TCO_STS
NULL, // [28] reserved
NULL, // [29] reserved
NULL, // [30] reserved
- NULL // [31] reserved
+ NULL // [31] reserved
};
/**
* happening in the following calls.
*/
smi_sts = reset_smi_status();
-
+
/* Filter all non-enabled SMI events */
// FIXME Double check, this clears MONITOR
// smi_sts &= inl(pmbase + SMI_EN);
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < 31; i++) {
- if (smi_sts & (1 << i)) {
+ if (smi_sts & (1 << i)) {
if (southbridge_smi[i])
southbridge_smi[i](node, state_save);
else {
- printk_debug("SMI_STS[%d] occured, but no "
+ printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
"handler available.\n", i);
dump = 1;
}
projects / coreboot.git / blobdiff