#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
#include "i82801gx.h"
-#include "i82801gx_power.h"
-
-#define DEBUG_SMI
#define APM_CNT 0xb2
-#define CST_CONTROL 0x85 // 0x85 crashes the box
-#define PST_CONTROL 0x80 // 0x80 crashes the box
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
#define ACPI_DISABLE 0x1e
#define ACPI_ENABLE 0xe1
#define GNVS_UPDATE 0xea
#define G_SMRANE (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-/* ICH7 */
-#define PM1_STS 0x00
-#define PM1_EN 0x02
-#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define GBL_RLS (1 << 2)
-#define BM_RLD (1 << 1)
-#define SCI_EN (1 << 0)
-#define PM1_TMR 0x08
-#define PROC_CNT 0x10
-#define LV2 0x14
-#define LV3 0x15
-#define LV4 0x16
-#define PM2_CNT 0x20 // mobile only
-#define GPE0_STS 0x28
-#define GPE0_EN 0x2c
-#define PME_B0_EN (1 << 13)
-#define SMI_EN 0x30
-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define MCSMI_EN (1 << 11) // Trap microcontroller range access
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
-#define SMI_STS 0x34
-#define ALT_GP_SMI_EN 0x38
-#define ALT_GP_SMI_STS 0x3a
-#define GPE_CNTL 0x42
-#define DEVACT_STS 0x44
-#define SS_CNT 0x50
-#define C3_RES 0x54
-
#include "i82801gx_nvs.h"
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
u16 pmbase = DEFAULT_PMBASE;
+u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
static void dump_pm1_status(u16 pm1_sts)
{
- printk_debug("PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk_debug("WAK ");
- if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk_debug("RTC ");
- if (pm1_sts & (1 << 8)) printk_debug("PWRBTN ");
- if (pm1_sts & (1 << 5)) printk_debug("GBL ");
- if (pm1_sts & (1 << 4)) printk_debug("BM ");
- if (pm1_sts & (1 << 0)) printk_debug("TMROF ");
- printk_debug("\n");
+ printk_spew("PM1_STS: ");
+ if (pm1_sts & (1 << 15)) printk_spew("WAK ");
+ if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK ");
+ if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR ");
+ if (pm1_sts & (1 << 10)) printk_spew("RTC ");
+ if (pm1_sts & (1 << 8)) printk_spew("PWRBTN ");
+ if (pm1_sts & (1 << 5)) printk_spew("GBL ");
+ if (pm1_sts & (1 << 4)) printk_spew("BM ");
+ if (pm1_sts & (1 << 0)) printk_spew("TMROF ");
+ printk_spew("\n");
+ int reg16 = inw(pmbase + PM1_EN);
+ printk_spew("PM1_EN: %x\n", reg16);
}
/**
switch (smif) {
case 0x32:
printk_debug("OS Init\n");
+ /* gnvs->smif:
+ * On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ */
gnvs->smif = 0;
- break;
- default:
- /* Not handled */
- return 0;
+ return 1; /* IO trap handled */
}
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- *
- * For now, we force the return value to 0 and log all traps to
- * see what's going on.
- */
- //gnvs->smif = 0;
- return 1; /* IO trap handled */
+ /* Not handled */
+ return 0;
}
/**
outb(reg8, pmbase + SMI_EN);
}
+static void busmaster_disable_on_bus(int bus)
+{
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
+}
+
static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
{
case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
case 7:
printk_debug("SMI#: Entering S5 (Soft Power off)\n");
-#if 0
- /* Set PME_B0_EN before going to S5 */
- reg32 = inl(pmbase + GPE0_EN);
- reg32 |= PME_B0_EN;
- outl(reg32, pmbase + GPE0_EN);
-#endif
+
+ outl(0, pmbase + GPE0_EN);
+
/* Should we keep the power state after a power loss?
* In case the setting is "ON" or "OFF" we don't have
* to do anything. But if it's "KEEP" we have to switch
reg8 |= 1;
pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
}
+
+ /* also iterates over all bridges on bus 0 */
+ busmaster_disable_on_bus(0);
break;
default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break;
}
printk_debug("SMI#: ACPI enabled.\n");
break;
case GNVS_UPDATE:
+ if (smm_initialized) {
+ printk_debug("SMI#: SMM structures already initialized!\n");
+ return;
+ }
gnvs = *(global_nvs_t **)0x500;
tcg = *(void **)0x504;
smi1 = *(void **)0x508;
+ smm_initialized = 1;
printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
break;
default:
pm1_sts = reset_pm1_status();
dump_pm1_status(pm1_sts);
+
+ /* While OSPM is not active, poweroff immediately
+ * on a power button event.
+ */
+ if (pm1_sts & PWRBTN_STS) {
+ // power button pressed
+ u32 reg32;
+ reg32 = (7 << 10) | (1 << 13);
+ outl(reg32, pmbase + PM1_CNT);
+ }
}
static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
dump_gpe0_status(gpe0_sts);
}
+void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
+
+static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+{
+ u16 reg16;
+ reg16 = inw(pmbase + ALT_GP_SMI_STS);
+ outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+ reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+
+ if (mainboard_smi_gpi) {
+ mainboard_smi_gpi(reg16);
+ } else {
+ if (reg16)
+ printk_debug("GPI (mask %04x)\n",reg16);
+ }
+}
+
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
{
u32 reg32;
#undef IOTRAP
}
-typedef void (*smi_handler)(unsigned int node,
+typedef void (*smi_handler_t)(unsigned int node,
smm_state_save_area_t *state_save);
-smi_handler southbridge_smi[32] = {
+smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
NULL, // [1] reserved
NULL, // [2] BIOS_STS
NULL, // [7] reserved
southbridge_smi_pm1, // [8] PM1_STS
southbridge_smi_gpe0, // [9] GPE0_STS
- NULL, // [10] GPI_STS
+ southbridge_smi_gpi, // [10] GPI_STS
southbridge_smi_mc, // [11] MCSMI_STS
NULL, // [12] DEVMON_STS
southbridge_smi_tco, // [13] TCO_STS
projects / coreboot.git / blobdiff