/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 coresystems GmbH
+ * Copyright (C) 2008-2009 coresystems GmbH
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801gx.h"
-#include "../../../northbridge/intel/i945/ich7.h"
+#define NMI_OFF 0
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
+#define ENABLE_ACPI_MODE_IN_COREBOOT 0
+#define TEST_SMM_FLASH_LOCKDOWN 0
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
-#endif
-
-#define NMI_OFF 0
-
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
- */
-
-#define PIRQA 0x03
-#define PIRQB 0x05
-#define PIRQC 0x06
-#define PIRQD 0x07
-#define PIRQE 0x09
-#define PIRQF 0x0A
-#define PIRQG 0x0B
-#define PIRQH 0x0C
+typedef struct southbridge_intel_i82801gx_config config_t;
static void i82801gx_enable_apic(struct device *dev)
{
int i;
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
- volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
+ volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+ volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
- /* Enable ACPI I/O and power management. */
+ /* Enable ACPI I/O and power management.
+ * Set SCI IRQ to IRQ9
+ */
pci_write_config8(dev, ACPI_CNTL, 0x80);
*ioapic_index = 0;
*ioapic_index = 0;
reg32 = *ioapic_data;
- printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+ printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
if (reg32 != (1 << 25))
die("APIC Error\n");
- printk_spew("Dumping IOAPIC registers\n");
+ printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
for (i=0; i<3; i++) {
*ioapic_index = i;
- printk_spew(" reg 0x%04x:", i);
+ printk(BIOS_SPEW, " reg 0x%04x:", i);
reg32 = *ioapic_data;
- printk_spew(" 0x%08x\n", reg32);
+ printk(BIOS_SPEW, " 0x%08x\n", reg32);
}
*ioapic_index = 3; /* Select Boot Configuration register. */
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
}
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
static void i82801gx_pirq_init(device_t dev)
{
- pci_write_config8(dev, PIRQA_ROUT, 0x85);
- pci_write_config8(dev, PIRQB_ROUT, 0x87);
- pci_write_config8(dev, PIRQC_ROUT, 0x86);
- pci_write_config8(dev, PIRQD_ROUT, 0x87);
-
- pci_write_config8(dev, PIRQE_ROUT, 0x80);
- pci_write_config8(dev, PIRQF_ROUT, 0x80);
- pci_write_config8(dev, PIRQG_ROUT, 0x80);
- pci_write_config8(dev, PIRQH_ROUT, 0x85);
+ device_t irq_dev;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+ pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+ pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+ pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+ pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+ pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+ pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+ pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+ /* Eric Biederman once said we should let the OS do this.
+ * I am not so sure anymore he was right.
+ */
+
+ for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin=0, int_line=0;
+
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
+
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+ switch (int_pin) {
+ case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+ case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+ case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+ case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ }
+
+ if (!int_line)
+ continue;
+
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
}
+static void i82801gx_gpi_routing(device_t dev)
+{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+ u32 reg32 = 0;
+
+ /* An array would be much nicer here, or some
+ * other method of doing this.
+ */
+ reg32 |= (config->gpi0_routing & 0x03) << 0;
+ reg32 |= (config->gpi1_routing & 0x03) << 2;
+ reg32 |= (config->gpi2_routing & 0x03) << 4;
+ reg32 |= (config->gpi3_routing & 0x03) << 6;
+ reg32 |= (config->gpi4_routing & 0x03) << 8;
+ reg32 |= (config->gpi5_routing & 0x03) << 10;
+ reg32 |= (config->gpi6_routing & 0x03) << 12;
+ reg32 |= (config->gpi7_routing & 0x03) << 14;
+ reg32 |= (config->gpi8_routing & 0x03) << 16;
+ reg32 |= (config->gpi9_routing & 0x03) << 18;
+ reg32 |= (config->gpi10_routing & 0x03) << 20;
+ reg32 |= (config->gpi11_routing & 0x03) << 22;
+ reg32 |= (config->gpi12_routing & 0x03) << 24;
+ reg32 |= (config->gpi13_routing & 0x03) << 26;
+ reg32 |= (config->gpi14_routing & 0x03) << 28;
+ reg32 |= (config->gpi15_routing & 0x03) << 30;
+
+ pci_write_config32(dev, 0xb8, reg32);
+}
+
+extern u8 acpi_slp_type;
+
static void i82801gx_power_options(device_t dev)
{
u8 reg8;
- u16 reg16;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
- int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
- get_option(&pwr_on, "power_on_after_fail");
+ if (get_option(&pwr_on, "power_on_after_fail") < 0)
+ pwr_on = MAINBOARD_POWER_ON;
+
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= 0xfe;
- if (pwr_on) {
- reg8 &= ~1;
- } else {
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
reg8 |= 1;
+ state = "off";
+ break;
+ case MAINBOARD_POWER_ON:
+ reg8 &= ~1;
+ state = "on";
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg8 &= ~1;
+ state = "state keep";
+ break;
+ default:
+ state = "undefined";
}
+
reg8 |= (3 << 4); /* avoid #S4 assertions */
+ reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
pci_write_config8(dev, GEN_PMCON_3, reg8);
- printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
+ printk(BIOS_INFO, "Set power %s after power failure.\n", state);
/* Set up NMI on errors. */
reg8 = inb(0x61);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
- printk_info ("NMI sources enabled.\n");
+ printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
} else {
- printk_info ("NMI sources disabled.\n");
+ printk(BIOS_INFO, "NMI sources disabled.\n");
reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
}
outb(reg8, 0x70);
- // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+ /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
reg16 = pci_read_config16(dev, GEN_PMCON_1);
- reg16 &= ~3;
- reg16 |= (1 << 3) | (1 << 5) | (1 << 10);
+ reg16 &= ~(3 << 0); // SMI# rate 1 minute
+ reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
+ reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
+ reg16 |= (1 << 5); // CPUSLP_EN Desktop only
+ // another laptop wants this?
+ // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
+ reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
+#if DEBUG_PERIODIC_SMIS
+ /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
+ * periodic SMIs.
+ */
+ reg16 |= (3 << 0); // Periodic SMI every 8s
+#endif
pci_write_config16(dev, GEN_PMCON_1, reg16);
- // Set GPIO13 to SCI (?)
- // This might be board specific
- pci_write_config32(dev, 0xb8, 0x08000000);
+ // Set the board's GPI routing.
+ i82801gx_gpi_routing(dev);
+
+ pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+ outl(config->gpe0_en, pmbase + GPE0_EN);
+ outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); // PM1_CNT
+
+ reg32 &= ~(7 << 10); // SLP_TYP
+ reg32 |= (1 << 1); // enable C3->C0 transition on bus master
+ reg32 |= (1 << 0); // SCI_EN
+ outl(reg32, pmbase + 0x04);
}
-void i82801gx_rtc_init(struct device *dev)
+static void i82801gx_configure_cstates(device_t dev)
+{
+ u8 reg8;
+
+ reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
+ reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
+ pci_write_config8(dev, 0xa9, reg8);
+
+ // Set Deeper Sleep configuration to recommended values
+ reg8 = pci_read_config8(dev, 0xaa);
+ reg8 &= 0xf0;
+ reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us
+ reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us
+ pci_write_config8(dev, 0xaa, reg8);
+}
+
+static void i82801gx_rtc_init(struct device *dev)
{
u8 reg8;
- u32 reg32;
int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
}
- printk_debug("rtc_failed = 0x%x\n", rtc_failed);
+ printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
rtc_init(rtc_failed);
}
-static void enable_hpet(struct device *dev)
+static void enable_hpet(void)
{
u32 reg32;
- u32 code = (0 & 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 << 17); /* Enable HPET. */
- /*
- * Bits [16:15] Memory Address Range
- * 00 FED0_0000h - FED0_03FFh
- * 01 FED0_1000h - FED0_13FFh
- * 10 FED0_2000h - FED0_23FFh
- * 11 FED0_3000h - FED0_33FFh
- */
- reg32 &= ~(3 << 15); /* Clear it */
- reg32 |= (code << 15);
- /* TODO: reg32 is never written to anywhere? */
- printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
+
+ /* Move HPET to default address 0xfed00000 and enable it */
+ reg32 = RCBA32(HPTC);
+ reg32 |= (1 << 7); // HPET Address Enable
+ reg32 &= ~(3 << 0);
+ RCBA32(HPTC) = reg32;
+}
+
+static void enable_clock_gating(void)
+{
+ u32 reg32;
+
+ /* Enable Clock Gating for most devices */
+ reg32 = RCBA32(CG);
+ reg32 |= (1 << 31); // LPC clock gating
+ reg32 |= (1 << 30); // PATA clock gating
+ // SATA clock gating
+ reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+ reg32 |= (1 << 23); // AC97 clock gating
+ reg32 |= (1 << 19); // USB EHCI clock gating
+ reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
+ reg32 |= (1 << 2); // PCIe clock gating;
+ reg32 &= ~(1 << 20); // No static clock gating for USB
+ reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
+ RCBA32(CG) = reg32;
}
+#if CONFIG_HAVE_SMI_HANDLER
static void i82801gx_lock_smm(struct device *dev)
{
void smm_lock(void);
+#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
+#endif
#if ENABLE_ACPI_MODE_IN_COREBOOT
- printk_debug("Enabling ACPI via APMC:\n");
+ printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#else
- printk_debug("Disabling ACPI via APMC:\n");
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(0x1e, 0xb2); // Disable ACPI mode
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
- /* Don't allow evil boot loaders, kernels, or
+ /* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/
smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
- printk_debug("Locking BIOS to RO... ");
+ printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
- printk_debug("ok.\n");
+ printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
- printk_debug("Writing:\n");
+ printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
- printk_debug("Testing:\n");
+ printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
- printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
- printk_debug("Done.\n");
+ printk(BIOS_DEBUG, "Done.\n");
+#endif
+}
#endif
+
+#define SPIBASE 0x3020
+static void i82801gx_spi_init(void)
+{
+ u16 spicontrol;
+
+ spicontrol = RCBA16(SPIBASE + 2);
+ spicontrol &= ~(1 << 0); // SPI Access Request
+ RCBA16(SPIBASE + 2) = spicontrol;
+}
+
+static void i82801gx_fixups(struct device *dev)
+{
+ /* This needs to happen after PCI enumeration */
+ RCBA32(0x1d40) |= 1;
+
+ /* USB Transient Disconnect Detect:
+ * Prevent a SE0 condition on the USB ports from being
+ * interpreted by the UHCI controller as a disconnect
+ */
+ pci_write_config8(dev, 0xad, 0x3);
}
static void lpc_init(struct device *dev)
{
- printk_debug("i82801gx: lpc_init\n");
+ printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* Setup power options. */
i82801gx_power_options(dev);
+ /* Configure Cx state registers */
+ i82801gx_configure_cstates(dev);
+
/* Set the state of the GPIO lines. */
//gpio_init(dev);
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
- enable_hpet(dev);
+ enable_hpet();
+
+ /* Initialize Clock Gating */
+ enable_clock_gating();
setup_i8259();
+ /* The OS should do this? */
+ /* Interrupt 9 should be level triggered (SCI) */
+ i8259_configure_irq_trigger(9, 1);
+
+#if CONFIG_HAVE_SMI_HANDLER
i82801gx_lock_smm(dev);
+#endif
+
+ i82801gx_spi_init();
+
+ i82801gx_fixups(dev);
}
static void i82801gx_lpc_read_resources(device_t dev)
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
-static void i82801gx_lpc_enable_resources(device_t dev)
-{
- pci_dev_enable_resources(dev);
- enable_childrens_resources(dev);
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = IO_APIC_ADDR;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- printk_debug("Setting LPC bridge subsystem ID\n");
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, 0));
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
}
static struct pci_operations pci_ops = {
static struct device_operations device_ops = {
.read_resources = i82801gx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801gx_lpc_enable_resources,
+ .enable_resources = pci_dev_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
.enable = i82801gx_enable,
.ops_pci = &pci_ops,
};
-/* ICH7 / ICH7R */
+/* 82801GH (ICH7 DH) */
+static const struct pci_driver ich7_dh_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x27b0,
+};
+
+/* 82801GB/GR (ICH7/ICH7R) */
static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27b8,
};
-/* ICH7M / ICH7U */
+/* 82801GBM/GU (ICH7-M/ICH7-U) */
static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27b9,
};
-/* ICH7M DH */
+/* 82801GHM (ICH7-M DH) */
static const struct pci_driver ich7m_dh_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27bd,
};
-
projects / coreboot.git / blobdiff