We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / southbridge / intel / i82801dx / i82801dx_lpc.c

diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
index c57bf0919b6dc27248bcd7e0f8e86fc171c169b5..768e70096bbf809aa9fb31a3c4759e57953d2c0c 100644 (file)
--- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
@@ -29,6 +29,7 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include "i82801dx.h"
 
 #define NMI_OFF 0
@@ -133,7 +134,7 @@ static void i82801dx_power_options(device_t dev)
        reg8 &= ~(1 << 3);      /* minimum asssertion is 1 to 2 RTCCLK */
 
        pci_write_config8(dev, GEN_PMCON_3, reg8);
-       printk_info("Set power %s after power failure.\n", state);
+       printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 
        /* Set up NMI on errors. */
        reg8 = inb(0x61);
@@ -147,10 +148,10 @@ static void i82801dx_power_options(device_t dev)
        nmi_option = NMI_OFF;
        get_option(&nmi_option, "nmi");
        if (nmi_option) {
-               printk_info ("NMI sources enabled.\n");
+               printk(BIOS_INFO, "NMI sources enabled.\n");
                reg8 &= ~(1 << 7);      /* Set NMI. */
        } else {
-               printk_info ("NMI sources disabled.\n");
+               printk(BIOS_INFO, "NMI sources disabled.\n");
                reg8 |= ( 1 << 7);      /* Disable NMI. */
        }
        outb(reg8, 0x70);
@@ -232,7 +233,7 @@ static void enable_hpet(struct device *dev)
        u32 reg32, hpet, val;
 
        /* Set HPET base address and enable it */
-       printk_debug("Enabling HPET at 0x%x\n", HPET_ADDR);
+       printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR);
        reg32 = pci_read_config32(dev, GEN_CNTL);
        /*
         * Bit 17 is HPET enable bit.
@@ -253,9 +254,9 @@ static void enable_hpet(struct device *dev)
        val &= 0x7;
 
        if ((val & 0x4) && (hpet == (val & 0x3))) {
-               printk_debug("HPET enabled at 0x%x\n", HPET_ADDR);
+               printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR);
        } else {
-               printk_err("HPET was not enabled correctly\n");
+               printk(BIOS_WARNING, "HPET was not enabled correctly\n");
                reg32 &= ~(1 << 17);    /* Clear Enable */
                pci_write_config32(dev, GEN_CNTL, reg32);
        }
@@ -317,21 +318,15 @@ static void i82801dx_lpc_read_resources(device_t dev)
                     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void i82801dx_lpc_enable_resources(device_t dev)
-{
-       pci_dev_enable_resources(dev);
-       enable_childrens_resources(dev);
-}
-
 static struct device_operations lpc_ops = {
        .read_resources         = i82801dx_lpc_read_resources,
        .set_resources          = pci_dev_set_resources,
-       .enable_resources       = i82801dx_lpc_enable_resources,
+       .enable_resources       = pci_dev_enable_resources,
        .init                   = lpc_init,
        .scan_bus               = scan_static_bus,
        .enable                 = i82801dx_enable,